JP2010109130A - Manufacturing method of electric solid state device, electric solid state device, and electro-optic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of an electric solid state device capable of forming microscopic patterns without generating unetched portions, even in the case that wet etching has been adopted, and to provide an electrical solid state device and an electro-optic device. <P>SOLUTION: In forming a translucent pixel electrode 7a having a slit 7b on the element substrate of an electro-optic device, wet etching is performed after a resist mask 96 is formed on a translucent conductive film 7. In the resist mask 96, the side surface 96f of a mask linear portion 96e that sandwiches a mask aperture 96b is in a shape of a taper surface facing upward in a slant manner. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing an electric solid state device having a thin film pattern formed on a substrate, an electric solid state device manufactured by the method, and an electro optical device using the electro optical device as an element substrate. .

  In an electrical solid state device such as a semiconductor device or various circuit boards, at least a thin film pattern is formed on the substrate. For example, an element substrate used in an FFS (Fringe Field Switching) type liquid crystal device or the like is configured as an electric solid-state device in which a slit-like opening pattern is formed on a light-transmitting pixel electrode (Patent Documents 1 and 2). reference).

In order to form a pixel electrode on such an element substrate, a resist mask is formed on the upper surface of the ITO film as a thin film by using a photolithography technique, and the ITO film is etched in this state. Such a resist mask is formed by applying a photosensitive resist, and then exposing and developing.
JP 2008-076800 A JP 2008-116485 A

  In such an element substrate, it is desired to reduce the width dimension of the slit-like opening pattern of the pixel electrode. To meet such a requirement, the width dimension of the mask opening of the resist mask may be reduced. .

  However, in order to reduce the width of the mask opening of the resist mask, the limit of the width of the mask opening of the resist mask is 2.0 μm in terms of the resolution of the exposure apparatus used when forming the resist mask. is there. Further, when wet etching is performed after the resist mask is formed, side etching of about 0.5 μm occurs on both sides. For this reason, the opening pattern of the slit of the pixel electrode has a problem that the width dimension cannot be reduced to 3.0 μm or less. In addition, in the case of wet etching, if the width dimension of the mask opening of the resist mask is narrowed to 2.0 μm, the etching solution does not enter the mask opening of the resist mask and an unetched portion is generated. is there. In addition, if the width dimension of the mask opening is narrow, it is difficult for the etching solution to flow in and out of the mask opening and the outflow of dissolved components from the thin film to the outside of the mask opening. Even in this respect, an unetched portion is likely to occur.

  If dry etching is performed instead of wet etching, the progress of side etching can be suppressed. However, since dry etching has a lower etching selectivity than wet etching, the bottom of the opening pattern is etched to the ground. End up. In particular, when the ITO film or the IZO film is dry-etched on a base made of a silicon oxide film or a silicon nitride film, there is a problem that the base is easily etched.

  Therefore, it is desired to form a fine pattern by wet etching. Such a requirement is not limited to the case of forming a pixel electrode having a slit-like opening pattern, and is not limited to the field of liquid crystal devices, but is common to electrical solid-state devices having a step of etching a thin film to form a thin film pattern. It is a problem.

  Accordingly, an object of the present invention is to provide an electrical solid state device manufacturing method capable of forming a fine pattern without generating an unetched portion even when wet etching is employed, and an electrical solid manufactured by the method. An apparatus and an electro-optical device using the electro-optical device as an element substrate are provided.

  Another object of the present invention is to provide an electrical solid state device in which the wiring is not etched by a stripping solution used when the resist mask is stripped even when used as an aluminum-based wiring material. An object of the present invention is to provide an electro-optical device used as an element substrate and a method for manufacturing an electrical solid state device.

  In order to solve the above-described problems, a method of manufacturing an electrical solid state device according to the present invention includes a thin film forming step of forming a thin film on a substrate, and side surfaces facing each other across a mask opening are formed with an obliquely upward tapered surface. An etching mask forming step of forming an etching mask formed on the upper surface of the thin film; and an etching step of performing wet etching on the thin film from the mask opening.

  In the present invention, when forming a thin film pattern having an opening pattern by etching a thin film using a photolithography technique and an etching technique, side surfaces facing each other with a mask opening interposed therebetween become an obliquely upward tapered surface. An etching mask is used. In such an etching mask, the side surface portion is a tapered surface. Therefore, even if the upper end opening of the mask opening portion has a wide opening width, the width dimension of the portion where the thin film is exposed at the bottom portion of the mask opening portion is narrow. Therefore, the width dimension of the opening pattern formed in the thin film after the etching is narrow even if the side etching when the wet etching is adopted is taken into consideration. In the resist mask, the side surfaces facing each other across the mask opening are tapered upward, so that even if the width of the mask opening is narrow, the etching solution smoothly flows inside the mask opening. Since it enters, an unetched part does not occur. In addition, since the etchant flows in and out between the inside and outside of the mask opening and the dissolved component from the thin film flows out of the mask opening smoothly, an unetched portion does not occur.

  In the present invention, the thickness of the etching mask is preferably 0.7 μm or less. When the thickness of the etching mask is reduced to 0.7 μm or less, the aspect ratio of the mask opening can be reduced. Therefore, it is easy for the etchant to enter the mask opening, the inflow and outflow of the etchant between the inside and outside of the mask opening, and the outflow of dissolved components from the thin film to the outside of the mask opening. Etched part does not occur.

  In the present invention, the tapered surface preferably forms an angle of 60 ° or less with respect to the substrate surface of the substrate. When the tapered surface forms an angle of 60 ° or less with respect to the substrate surface of the substrate, the etching solution enters the mask opening, and the etching solution between the inside and the outside of the mask opening. Since inflow and outflow and outflow of dissolved components from the thin film to the outside of the mask opening portion easily occur, an unetched portion does not occur. Further, when the tapered surface forms an angle of 60 ° or less with respect to the substrate surface, even if the opening width of the upper end opening of the mask opening is wide, the portion where the thin film is exposed at the bottom of the mask opening Can be sufficiently narrowed, so that the thin film can be etched finely.

  In this invention, it is preferable that the width dimension in the bottom part of the said mask opening part is 1.5 micrometers or less in the said etching mask. Moreover, in this invention, it is preferable that the opening width of the opening pattern formed in the said thin film by the said etching process is 2.5 micrometers or less. The structure of the etching mask in which the width dimension of the portion where the thin film is exposed at the bottom of the mask opening is 1.5 μm or less is a level that cannot be achieved by an etching mask formed by a conventional photolithography technique. The utility value is great. In addition, when an etching mask having such a configuration is used, the width dimension of the opening formed in the thin film is 2.5 μm or less even when side etching during wet etching is taken into consideration. Such a configuration is at a level that cannot be achieved by conventional photolithography technology and etching technology, and has great industrial utility value.

  In the present invention, the etching mask forming step includes a resist coating step of applying a positive photoresist on the upper surface of the thin film, an exposure step of exposing a region where the mask opening is to be formed in the photoresist, and an exposure step. It is preferable to have a developing step for developing the subsequent photoresist. With this configuration, the exposure dose distribution in the depth direction of the photoresist is such that the exposure dose is attenuated as the depth increases. Therefore, after development, the resist mask (etching) in which the side surface portion becomes an obliquely upward tapered surface is developed. Mask).

  In the present invention, the photoresist is preferably mixed with a dye. If comprised in this way, the sensitivity of a photoresist can be adjusted with absorption of the light by dye. Further, since the sensitivity can be adjusted only by blending the dye, the development period of the photoresist material itself can be greatly reduced.

  In the present invention, the etching mask includes, for example, a plurality of linear mask portions arranged in parallel, and the mask opening is formed in a slit shape between the plurality of linear mask portions. In this case, the side surface portion of the linear mask portion is the tapered surface.

  The present invention is effective when applied to the case where the thin film is an ITO (Indium Tin Oxide) film or an IZO (Indium Zinc Oxide) film. When an ITO film or an IZO film is dry-etched on a base made of a silicon oxide film or a silicon nitride film, there is a problem that the base is easily etched. However, according to the present invention, fine etching is performed even by wet etching. Therefore, it is not necessary to employ dry etching having such a problem.

  The present invention can be applied to various electric solid-state devices such as semiconductor devices and circuit boards. For example, an electro-solid device manufactured by the method of the present invention can be configured as an element substrate for an electro-optical device having a pixel electrode on the substrate in the electro-optical device. In this case, for example, a common electrode that forms a horizontal electric field with respect to the liquid crystal is formed between the pixel electrode and the pixel electrode, and at least one of the pixel electrode and the common electrode is formed by the etching process. A configuration constituted by the thin film in which a slit-like opening pattern is formed can be adopted. According to such a configuration, in the FFS mode liquid crystal device, a slit-like opening pattern can be formed with a narrow width in the pixel electrode or the common electrode, so that display performance can be improved.

  Hereinafter, as an embodiment of the present invention, an example in which the method for manufacturing an electrical solid state device according to the present invention is applied to a method for manufacturing an element substrate of a liquid crystal device which is a typical electro-optical device will be mainly described. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. Further, illustration of a color filter, an alignment film, and the like is omitted. In the field-effect transistor, the source and the drain are switched depending on the polarity of the applied voltage. In the following description, for convenience of explanation, the side to which the pixel electrode is connected will be described as the drain.

[Embodiment 1]
(overall structure)
FIGS. 1A and 1B are a plan view of an electro-optical device to which the present invention is applied, as viewed from the counter substrate side, together with the components formed thereon, and a cross-sectional view taken along the line H-H ′. is there. 1A and 1B, an electro-optical device 100 according to this embodiment is a transmissive active matrix liquid crystal device, and an element substrate 10 (semiconductor device) as an electrical solid device and a counter substrate 20 are described. It is bonded by a sealant 107 through a predetermined gap. The counter substrate 20 has substantially the same contour as that of the seal material 107, and the homogeneously aligned liquid crystal 50 is held in a region partitioned by the seal material 107 between the element substrate 10 and the counter substrate 20. . The liquid crystal 50 is a liquid crystal composition having a positive dielectric anisotropy having a dielectric constant in the alignment direction larger than the normal direction, and exhibits a nematic phase in a wide temperature range.

  In the element substrate 10, the data line driving circuit 101 and the mounting terminals 102 are provided along one side of the element substrate 10 in a region outside the sealant 107, and 2 adjacent to the side where the mounting terminals 102 are arranged. A scanning line driving circuit 104 is formed along the side. On the remaining side of the element substrate 10, a plurality of wirings 105 are provided for connecting between the scanning line driving circuits 104 provided on both sides of the image display region 10a. In some cases, peripheral circuits such as a precharge circuit and an inspection circuit are provided.

  As will be described in detail later, pixel electrodes 7 a are formed in a matrix on the element substrate 10. On the other hand, a frame 108 made of a light-shielding material is formed in the inner area of the sealing material 107 on the counter substrate 20, and the inner side is an image display area 10 a. In the counter substrate 20, a light shielding film 23 called a black matrix or a black stripe is formed in a region facing the vertical and horizontal boundary regions of the pixel electrode 7 a of the element substrate 10.

  The electro-optical device 100 according to this embodiment drives the liquid crystal 50 by the FFS method. For this reason, a common electrode (not shown) is also formed on the element substrate 10 in addition to the pixel electrode 7a, and no counter electrode is formed on the counter substrate 20. When such a structure is adopted, since static electricity easily enters from the counter substrate 20 side, a shield layer made of an ITO film or the like may be formed on the surface of the counter substrate 20 opposite to the element substrate 10 side. .

  In the electro-optical device 100 according to this embodiment, the counter substrate 20 is disposed so as to be positioned on the display light emitting side, and a backlight device (not shown) is provided on the side opposite to the counter substrate 20 with respect to the element substrate 10. ) Is arranged. An optical member such as a polarizing plate is disposed on each of the counter substrate 20 side and the element substrate 10 side. The electro-optical device 100 may be configured as a reflection type or a transflective type. In the case of the transflective type, the phase difference layer is formed on the reflective display region on the surface of the counter substrate 20 facing the element substrate 10. May be formed.

(Detailed configuration of electro-optical device 100)
With reference to FIG. 2, the configuration of the electro-optical device 100 according to the first embodiment of the present invention and the element substrate used therefor will be described. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of the image display region 10a of the element substrate 10 used in the electro-optical device 100 according to Embodiment 1 of the present invention.

  As shown in FIG. 2, a plurality of pixels 100 a are formed in a matrix in the image display region 10 a of the electro-optical device 100. In each of the plurality of pixels 100a, a pixel electrode 7a and a field effect transistor 30 (pixel transistor) for controlling the pixel electrode 7a are formed, and data for supplying a data signal (image signal) in a line sequential manner. The line 5 a is electrically connected to the source of the field effect transistor 30. The scanning line 3a is electrically connected to the gate of the field effect transistor 30, and a scanning signal is applied to the scanning line 3a line by line at a predetermined timing. The pixel electrode 7a is electrically connected to the drain of the field effect transistor 30. By turning on the field effect transistor 30 for a certain period, a data signal supplied from the data line 5a is supplied to each pixel. Write to 100a at a predetermined timing. The pixel signal of a predetermined level written in the liquid crystal 50 shown in FIG. 1B through the pixel electrode 7a in this way is constant between the pixel electrode 7a formed on the element substrate 10 and the common electrode 9a. Hold for a period. Here, a storage capacitor 60 is formed between the pixel electrode 7a and the common electrode 9a, and the voltage of the pixel electrode 7a is held, for example, for a time that is three orders of magnitude longer than the time when the source voltage is applied. The As a result, the charge retention characteristic is improved, and the electro-optical device 100 capable of performing display with a high contrast ratio is realized.

  In FIG. 2, the common electrode 9 a is shown as a wiring extending from the scanning line driving circuit 104, but it is formed on substantially the entire surface of the image display region 10 a of the element substrate 10 and is held at a predetermined potential. The common electrode 9a may be formed across the plurality of pixels 100a or for each of the plurality of pixels 100a. In either case, a common potential is applied.

(Detailed configuration of each pixel)
3A and 3B are a cross-sectional view of one pixel of the electro-optical device 100 according to Embodiment 1 of the present invention, and a plan view of adjacent pixels in the element substrate 10, respectively. 3A corresponds to a cross-sectional view when the electro-optical device 100 is cut at a position corresponding to the line A1-A1 ′ in FIG. In FIG. 3B, the pixel electrode 7a is indicated by a thick and long dotted line, the data line 5a and a thin film formed simultaneously with it are indicated by a one-dot chain line, the scanning line 3a is indicated by a two-dot chain line, and the semiconductor layer is thin. It is shown with a short dotted line.

  As shown in FIGS. 3A and 3B, on the element substrate 10, a light-transmitting pixel electrode 7a (a region surrounded by a thick and long dotted line) is formed for each pixel 100a and adjacent thereto. A data line 5a (a region indicated by a one-dot chain line) and a scanning line 3a (a region indicated by a two-dot chain line) extend between the pixel electrodes 7a. A translucent common electrode 9a is formed on substantially the entire surface of the image display region 10a of the element substrate 10. Both the pixel electrode 7a and the common electrode 9a are made of an ITO film.

  In this embodiment, the common electrode 9a is formed as a lower electrode, and the pixel electrode 7a is formed as an upper electrode. Therefore, the upper pixel electrode 7a has a plurality of fringe electric field forming slits 7b formed in parallel to each other, and a linear electrode portion 7e is formed in a region sandwiched between the slits 7b. In this embodiment, the slit 7b and the linear electrode portion 7e extend with an inclination of 5 degrees with respect to the scanning line 3a. Moreover, the slit 7b has a closed shape without any open end.

  Here, when the width dimension Lt of the slit 7b is narrow, a fringe electric field can be generated more efficiently, and a high-quality image can be displayed. Therefore, in this embodiment, the width dimension Lt of the slit 7b is narrowed to 2.5 μm or less by adopting the method described with reference to FIGS.

  The base of the element substrate 10 shown in FIG. 3A includes a light-transmitting substrate 10b such as a quartz substrate or a heat-resistant glass substrate, and the base of the counter substrate 20 is a transparent substrate such as a quartz substrate or a heat-resistant glass substrate. It consists of the optical substrate 20b. In this embodiment, a glass substrate is used for both of the translucent substrates 10b and 20b. In the element substrate 10, a base protective film (not shown) made of a silicon oxide film or the like is formed on the surface of the translucent substrate 10b, and on the surface side, the top is located at a position corresponding to each pixel electrode 7a. A gate-effect field effect transistor 30 is formed.

  As shown in FIGS. 3A and 3B, in the field effect transistor 30, the semiconductor layer 1a constituting the active layer has a planar shape that is bent so as to intersect the scanning line 3a at two locations. The field effect transistor 30 has a twin gate structure using two locations of the scanning line 3a as gate electrodes. The field effect transistor 30 includes a source region and a drain region on both sides of the two channel regions 1b. The field effect transistor 30 has an LDD (Lightly Doped Drain) structure, and the source region and the drain region are a low concentration source region 1c and a low concentration drain region 1d, a high concentration source 1e, and a high concentration drain, respectively. Region 1f. In this embodiment, the semiconductor layer 1a is a polysilicon film that has been polycrystallized by laser annealing or lamp annealing after an amorphous silicon film is formed on the element substrate 10. A gate insulating layer 2 made of a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed above the semiconductor layer 1a, and a scanning line 3a is formed above the gate insulating layer 2.

  An interlayer insulating film 4 made of a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed on the upper layer side of the gate electrode (scanning line 3a). A data line 5a is formed on the surface of the interlayer insulating film 4, and the data line 5a is electrically connected to a source region located closest to the data line 5a through a contact hole 4a formed in the interlayer insulating film 4. is doing. A drain electrode 5b is formed on the surface of the interlayer insulating film 4, and the drain electrode 5b is a conductive film formed simultaneously with the data line 5a. An interlayer insulating film 6 is formed on the upper side of the data line 5a and the drain electrode 5b. In this embodiment, the interlayer insulating film 6 is formed as a planarizing film made of a thick photosensitive resin having a thickness of 1.5 to 2.0 μm.

  A common electrode 9a made of an ITO film is formed on the surface of the interlayer insulating film 6, and a notch 9c is formed in the common electrode 9a at a portion overlapping the drain electrode 5b. An insulating film 8 (dielectric film) made of a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed on the surface of the common electrode 9a. A pixel electrode 7 a made of an ITO film is formed in an island shape on the insulating film 8. A contact hole 6a is formed in the interlayer insulating film 6, and a contact hole 8a is formed in the insulating film 8 inside the contact hole 6a. Therefore, the pixel electrode 7a is electrically connected to the drain electrode 5b at the bottom of the contact holes 6a and 8a. The drain electrode 5b is connected to the interlayer insulating film 4 and the contact hole 4b formed in the gate insulating layer 2. Are electrically connected to the high concentration drain region 1f.

  Although not shown, an alignment film is formed on the element substrate 10 and the counter substrate 20, and the alignment film on the counter substrate 20 side is subjected to a rubbing process in parallel with the scanning line 3a. A rubbing treatment in the direction opposite to the rubbing direction with respect to the alignment film of the counter substrate 20 is performed on the alignment film. For this reason, the liquid crystal 50 can be homogeneously aligned. Here, the slits 7b formed in the pixel electrode 7a of the element substrate 10 are formed in parallel to each other, but extend with an inclination of 5 degrees with respect to the scanning line 3a. For this reason, the alignment film is rubbed at an angle of 5 degrees in the direction in which the slits 7b extend. The polarizing plates are arranged so that their polarization axes are orthogonal to each other. The polarizing axis of the polarizing plate on the counter substrate 20 side is orthogonal to the rubbing direction with respect to the alignment film, and the polarization of the polarizing plate on the element substrate 10 side. The axis is parallel to the rubbing direction with respect to the alignment film.

  In the electro-optical device 100 configured as described above, the insulating film 8 is interposed between the common electrode 9a and the pixel electrode 7a, and a plurality of slits 7b for forming a fringe electric field are formed in the upper pixel electrode 7a. Yes. Therefore, the liquid crystal 50 can be driven by a fringe electric field formed between the upper pixel electrode 9a and the lower common electrode 9a. Further, a capacitance component formed in a portion where the upper pixel electrode 7 a and the lower common electrode 9 a are opposed to each other with the insulating film 8 interposed therebetween can be used as the storage capacitor 60.

(Method for manufacturing element substrate 10)
FIG. 4 is a process cross-sectional view illustrating the method for manufacturing the element substrate used in the electro-optical device according to the first embodiment of the present invention, and shows a position corresponding to FIG.

  In the manufacturing process of the element substrate 10 to which the present invention is applied, as shown in FIGS. 3A and 3B, a base protective film (not shown) made of a silicon oxide film is formed on the surface of the translucent substrate 10b made of a glass substrate. )), A thin film transistor forming step is performed. Specifically, first, the semiconductor layer 1a made of a polysilicon film is formed in an island shape. For this purpose, a semiconductor layer made of an amorphous silicon film is formed to a thickness of, for example, 40 to 50 nm on the entire surface of the translucent substrate 10b by plasma CVD under a temperature condition of 150 to 450 ° C. Thereafter, the silicon film is polycrystallized by a laser annealing method or the like, and then patterned using a photolithography technique to form the semiconductor layer 1a. Next, a gate insulating layer 2 made of a silicon nitride film, a silicon oxide film, or a laminated film thereof is formed on the surface of the semiconductor layer 1a by using a CVD method or the like. Next, after forming a metal film such as a molybdenum film, an aluminum film, a titanium film, a tungsten film, or a tantalum film on the entire surface of the light-transmitting substrate 10b, patterning is performed using a photolithography technique, and scanning lines 3a (gate electrodes) are formed. ). Next, impurities are introduced into the semiconductor layer 1a to form the source region 1c, the drain region 1d, and the like.

  Next, in the first interlayer insulating film forming step, an interlayer insulating film 4 made of a silicon nitride film, a silicon oxide film, or a laminated film thereof is formed using a CVD method or the like. Next, contact holes 4a and 4b are formed in the interlayer insulating film 4 by using a photolithography technique. Next, in the data line forming step, a metal film such as a molybdenum film, an aluminum film, a titanium film, a tungsten film, a tantalum film, or a laminated film thereof is formed on the entire surface of the translucent substrate 10b, and then a photolithography technique. The data line 5a and the drain electrode 5b are formed by patterning using. Next, in the second interlayer insulating film forming step, a photosensitive resin is applied, exposed and developed, and the interlayer insulating film 6 (flattened film) provided with the contact holes 6a is formed to a thickness of 1.5 to 2.0 μm. To form.

  Next, in the common electrode forming step, after forming a light-transmitting conductive film made of an ITO film on the entire surface of the light-transmitting substrate 10b, the light-transmitting conductive film 9 is patterned using a photolithography technique, and FIG. As shown in (a), the common electrode 9a is formed. At that time, a notch 9c is formed in the common electrode 9a.

  Next, in the insulating film forming step, as shown in FIG. 4B, an insulating film 8 made of a silicon oxide film, a silicon nitride film, and a laminated film thereof is formed by CVD or the like, and then a photolithography technique is used. A contact hole 8a is formed in the insulating film 8 by using it.

  Next, in the pixel electrode forming step, first, in the thin film forming step shown in FIG. 4C, the translucent conductive film 7 (thin film) made of an ITO film is formed on the entire surface of the translucent substrate 10b.

  Next, in the etching mask formation step shown in FIG. 4D, a resist mask 96 (etching mask) is formed on the upper surface of the translucent conductive film 7 by using a photolithography technique. Here, the resist mask 96 includes a mask opening 96b in a region substantially overlapping with the slit 7b described with reference to FIGS. 3A and 3B, and a mask linear shape in a region substantially overlapping with the linear electrode portion 7e. A portion 96e is provided.

  Next, in the etching process, when wet etching is performed on the translucent conductive film 7 using aqua regia or the like with the resist mask 96 formed on the upper surface of the translucent conductive film 7, FIG. ), And the pixel electrode 7a includes a slit 7b and a linear electrode portion 7e. Thereafter, the resist mask 96 is removed.

(Detailed description of pixel electrode formation process)
FIG. 5 is an explanatory diagram illustrating a pixel electrode forming step in the manufacturing process of the element substrate used in the electro-optical device according to the first embodiment of the invention.

  In the electro-optical device 100 described with reference to FIGS. 1 to 3, when the transparent conductive film 7 is patterned by wet etching, a part of the transparent conductive film 7 is not etched inside the slit 7b. It is not preferable that it remains. Further, when the width dimension Lt of the slit 7b formed in the pixel electrode 7a is narrower, a fringe electric field can be generated efficiently, and a high-quality image can be displayed. However, in order to narrow the width dimension Lt of the slit 7b formed in the pixel electrode 7a, the width dimension of the mask opening 96b shown in FIG. The resolution of the exposure machine is limited. Further, if wet etching is performed when the width of the mask opening 96b is narrow, the etching solution enters the mask opening 96b, and the etching solution flows between the inside and outside of the mask opening 96b. The dissolved component from the translucent conductive film 7 does not smoothly flow out of the mask opening 96b, and a part of the translucent conductive film 7 is likely to remain without being etched inside the slit 7b. In particular, when the slit 7b has a closed shape as in this embodiment, the etching solution does not enter smoothly into the mask opening 96b, so that an unetched portion is likely to be generated in the slit 7b.

  Therefore, in the present embodiment, the method described in detail below is adopted, and the width dimension of the mask opening 96b is substantially 1. even when the resolution of the exposure apparatus for forming the resist mask 96 is 2 μm or more. By forming a resist mask 96 of 5 μm or less, the width dimension Lt of the slit 7 b of the pixel electrode 7 a is narrowed to 1.5 μm or less. Further, even when the width dimension of the mask opening 96b and the width dimension Lt of the slit 7b are narrowed, a part of the translucent conductive film 7 is prevented from being left unetched inside the slit 7b.

  First, in the present embodiment, as shown in FIG. 4D, a resist mask 96 is formed in which the side surface portion 96f of the mask linear portion 96e facing each other with the mask opening portion 96b interposed therebetween is an obliquely upward tapered surface. Then, wet etching is performed on the translucent conductive film 7 using the resist mask 96. Therefore, during the wet etching, the etching solution enters the mask opening 96b, the etching solution flows in and out of the mask opening 96b, and the dissolved components from the translucent conductive film 7 are removed. Outflow from the mask opening 96b to the outside is smooth. Therefore, a part of the translucent conductive film 7 does not remain inside the slit 7b without being etched.

In forming this resist mask 96, in this embodiment, a positive photoresist 960 corresponding to i-line (wavelength 365 nm) is formed on the upper surface of the translucent conductive film 7 in the resist coating step shown in FIG. Apply. In this embodiment, a photoresist 960 having a sensitivity of 100 mj / cm ² or less, preferably 60 mj / cm ² or less is used as the photoresist 960. Next, in the exposure step, the region where the mask opening 96b is to be formed in the photoresist 960 is exposed with i-line (wavelength 365 nm) light through an exposure mask (not shown). In FIG. 5 (a), the exposed portion 960b of the photoresist 960 is indicated by a dotted line descending to the right. Next, when the exposed portion 960b is removed in the development step, a resist mask 96 shown in FIGS. 4D and 5B is obtained.

  In such a resist mask formation step, in the exposure shown in FIG. 5A, the exposure dose is attenuated as the photoresist 960 becomes deeper in the exposure dose distribution in the depth direction. In particular, since the exposure amount is small at the end portion of the exposed portion 960b, it can be considered that an obliquely upward boundary surface 960f is formed between the exposed portion 960b and the non-exposed portion 960e. Therefore, when the exposed portion 960b is removed in the development process, as shown in FIG. 4D and FIG. 5B, the side surface portion 96f of the mask linear portion 96e facing each other across the mask opening portion 96b faces obliquely upward. A resist mask 96 having a tapered surface can be formed.

In the resist mask 96 having such a configuration, the opening width Lc of the upper opening of the mask opening 96b is defined by the resolution of the exposure machine used in the exposure process, and the limit is 2.0 μm. However, in the resist mask 96 of this embodiment, since the side surface portion 96f is an obliquely upward tapered surface, the lower end portion of the side surface portion 96f protrudes by a dimension Lf at the bottom of the mask opening portion 96b. Therefore, the width dimension Lb of the bottom of the mask opening 96b (the width dimension of the translucent conductive film 7 exposed at the bottom of the mask opening 96b) is expressed by the following formula: Lb = Lc−2 × Lf
And is narrower by 2 × Lf than the width dimension Lc of the upper opening of the mask opening 96b.

  Therefore, even if the resolution of the exposure apparatus is 2 μm, it is possible to form a resist mask 96 having a width Lb of the bottom of the mask opening 96b of 1.5 μm or less. The resist mask 96 has a width of the mask opening. It functions in the same way as a resist mask whose size is 1.5 μm or less. Therefore, as shown in FIG. 5C, even when side etching Ls of about 0.5 μm occurs when the light-transmitting conductive film 7 is wet-etched, as shown in FIG. A pixel electrode 7a having a width dimension Lt of 7b of 2.5 μm or less can be formed. Preferably, a resist mask 96 having a width Lb of 1.0 μm or less at the bottom of the mask opening 96b is formed, and a pixel electrode 7a having a width Lt of 2.0 μm or less of the slit 7b is formed.

Here, at the bottom of the mask opening 96b, the dimension Lf at which the lower end of the side surface portion 96f protrudes is the thickness d of the resist mask 96 and the angle Θ formed by the side surface portion 96f (tapered surface) with respect to the substrate surface. By the following formula, Lf = d / tanΘ
It is obtained by

  Therefore, the larger the thickness d of the resist mask 96, the larger the dimension Lf at which the lower end of the side surface part 96f projects, and the smaller the width dimension Lb of the bottom of the mask opening 96b. Further, as the angle Θ formed by the side surface portion 96f (tapered surface) with respect to the substrate surface is smaller, the dimension Lf at which the lower end portion of the side surface portion 96f protrudes can be increased, and the width dimension Lb of the bottom portion of the mask opening 96b. Can be reduced.

  However, if the thickness d of the resist mask 96 is increased, the etchant enters the mask opening 96b and the etchant flows in and out of the mask opening 96b during wet etching. Therefore, the outflow of the dissolved component from the translucent conductive film 7 to the outside of the mask opening 96b does not proceed smoothly. Accordingly, it is preferable that the thickness d of the resist mask 96 is 0.7 μm or less so that the etching solution enters the mask opening 96b smoothly. The lower limit of the thickness d of the resist mask 96 is about 0.2 μm in consideration of the limit that allows the photoresist 960 to be uniformly applied.

  Further, as the angle Θ formed by the side surface portion 96f with respect to the substrate surface is smaller, the dimension Lf at which the lower end portion of the side surface portion 96f protrudes can be increased, and the etchant enters the mask opening 96b. Etc. will proceed smoothly. Therefore, the angle Θ formed by the side surface portion 96f with respect to the substrate surface is preferably 60 ° or less, more preferably 50 ° or less.

  In forming the resist mask 96 with the side surface portion 96f having an obliquely upward tapered surface by the above method, a photoresist 960 containing a dye that absorbs light irradiated at the time of exposure may be used. Good. If such a dye is blended, the sensitivity of the photoresist 960 can be adjusted, and the sensitivity can be adjusted only by blending the dye, so that the development period of the photoresist material itself can be greatly reduced. Therefore, the mask linear portion 96e whose side surface portion 96f has an obliquely upward tapered surface can be surely formed without enormous cost, and the mask linear portion 96e and the mask opening portion 96b can be finely patterned. Can do.

(Main effects of this form)
As described above, in the electro-optical device 100 according to this embodiment, when forming the pixel electrode 7a in which the plurality of fringe electric field forming slits 7b are formed, the mask linear portions 96e that face each other across the mask opening 96b. The resist mask 96 is used in which the side surface portion 96f is a tapered surface that is inclined upward. Since the resist mask 96 has a taper surface on the side surface 96f even if the opening width Lc of the upper end opening of the mask opening 96b is large due to the influence of the resolution of the exposure machine used when forming the resist mask 96. The width Lb of the portion where the transparent conductive film 7 is exposed at the bottom of the mask opening 96b is narrow. Accordingly, even if the side etching Ls when the wet etching is adopted is taken into consideration, the pixel electrode 7a having the width Lt of the slit 7b (opening pattern) of 2.5 μm or less, further 2.0 μm or less can be formed. .

  Further, in the resist mask 96, the side surface portions 96f facing each other with the mask opening portion 96b interposed therebetween are obliquely upward tapered surfaces, so that even if the width dimension of the mask opening portion 96b is narrow, the inside of the mask opening portion 96b. The etching solution enters smoothly. Therefore, the problem that a part of the translucent conductive film 7 remains without being etched inside the slit 7b does not occur. Therefore, according to this embodiment, even in wet etching, an unetched portion is not generated inside the slit 7b, and the width dimension Lt of the slit 7b (opening pattern) is 2.5 μm or less, and further 2.0 μm or less. The pixel electrode 7a can be formed. In addition, since wet etching has higher etching selectivity than dry etching, the underlying insulating film 8 is not damaged.

[Embodiment 2]
6A and 6B are a cross-sectional view of one pixel of the electro-optical device 100 according to the second embodiment of the present invention, and a plan view of adjacent pixels in the element substrate 10, respectively. 6A corresponds to a cross-sectional view when the electro-optical device 100 is cut at a position corresponding to the line A4-A4 ′ in FIG. Since the basic configuration of this embodiment is the same as the configuration described with reference to FIGS. 1 to 5, common portions are denoted by the same reference numerals as much as possible so that the correspondence can be easily understood. A description will be given.

  In the above embodiment, the field effect transistor 30 having the top gate structure is used as the pixel transistor. However, as described below with reference to FIGS. 6A and 6B, the bottom gate is used as the pixel transistor. The present invention may be applied to the electro-optical device 100 used by the field effect transistor 30 having the structure.

  In the electro-optical device 100 shown in FIGS. 6A and 6B, a light-transmitting pixel electrode 7a made of an ITO film is formed on the element substrate 10 for each pixel 100a. A data line 5a and a scanning line 3a electrically connected to the field effect transistor 30 are formed along the vertical and horizontal boundary regions of the pixel electrode 7a. A common wiring 3c is formed so as to be parallel to the scanning line 3a, and the common wiring 3c is a wiring layer formed simultaneously with the scanning line 3a. On the lower layer side of the common wiring 3c, a translucent common electrode 9a made of an ITO film extends in a strip shape in the same direction as the extending direction of the scanning line 3a and the common wiring 3c, and the common wiring 3c and the common electrode 9a The end is electrically connected. Therefore, the common electrode 9a is formed so as to straddle the plurality of pixels 100a. However, the common electrode 9a may be formed for each of the plurality of pixels 100a. In either case, the common electrode 9a is electrically connected to the common wiring 3c, and a common potential is applied to each pixel 100a.

  In this embodiment, the field effect transistor 30 has a bottom gate structure. In the field effect transistor 30, the gate electrode formed of a part of the scanning line 3 a, the gate insulating layer 2, and the active layer of the field effect transistor 30. A semiconductor layer 1a made of an amorphous silicon film and a contact layer (not shown) are stacked in this order. In the semiconductor layer 1a, the data line 5a overlaps with the end on the source side via the contact layer, and the drain electrode 5b overlaps with the end on the drain side via the contact layer. The data line 5a and the drain electrode 5b are made of a conductive film formed simultaneously. An insulating protective film 11 made of a silicon nitride film or the like is formed on the surface side of the data line 5a and the drain electrode 5b. A pixel electrode 7 a made of an ITO film is formed on the insulating protective film 11.

  In the pixel electrode 7a, a plurality of slits 7b for forming a fringe electric field are formed in parallel to each other, and a linear electrode portion 7e is formed between the slits 7b. A contact hole 11a is formed in the insulating protective film 11 in a region overlapping with the drain electrode 5b, and the pixel electrode 7a is electrically connected to the drain electrode 5b through the contact hole 11a.

  In the element substrate 10, a common wiring 3 c is formed on the lower layer side of the gate insulating layer 2. A common electrode 9a made of an ITO film is formed below the common wiring 3c, and the end of the common electrode 9a is electrically connected to the common wiring 3c. A gate insulating layer 2 and an insulating protective film 11 are formed on the surface of the common electrode 9a. Therefore, the insulating film 18 composed of the gate insulating layer 2 and the insulating protective film 11 is interposed between the common electrode 9a and the pixel electrode 7a. In the electro-optical device 100 configured as described above, a plurality of slits 7b for forming a fringe electric field are formed in the upper pixel electrode 7a, and a portion sandwiched between the slits 7b is a linear electrode portion 7e. Therefore, the liquid crystal 50 can be driven by a fringe electric field formed between the upper pixel electrode 9a and the lower common electrode 9a. In addition, a capacitance component formed in a portion where the upper pixel electrode 7 a and the lower common electrode 9 a face each other with the insulating film 18 interposed therebetween can be used as the storage capacitor 60.

  Also in the electro-optical device 100 configured as described above, the method described with reference to FIG. 5 may be employed when forming the pixel electrode 7a including the slit 7b by wet etching, as in the first embodiment. .

[Other embodiments]
In the first and second embodiments, the pixel electrode 7a is formed of an ITO film. However, the present invention may be applied when the pixel electrode 7a is formed of an IZO film.

  In the first and second embodiments, the slit 7b formed in the pixel electrode 7a extends with an inclination of 5 degrees with respect to the scanning line 3a. However, the present invention is not limited to this, and the slit 7b is parallel to the scanning line 3a or the data line 5a. It may extend in a direction parallel to. Moreover, you may employ | adopt the structure which the slit 7b bends in the middle of the length direction.

  In the first and second embodiments, since the common electrode 9a is formed on the lower layer side and the pixel electrode 7a is formed on the upper layer side, the slit is formed on the pixel electrode 7a, but the common electrode 9a is formed on the upper layer side. The pixel electrode 7a may be formed on the lower layer side. In this case, a configuration in which slits are formed in the upper common electrode 9a is employed.

  In the first and second embodiments, the present invention is applied to the electro-optical device 100 adopting the FFS method. However, other types such as an IPS (In Plane Switching) method liquid crystal device that drives a liquid crystal by a lateral electric field. The present invention may be applied when forming pixel electrodes of the liquid crystal device (electro-optical device). Furthermore, not only in a horizontal electric field type liquid crystal device (electro-optical device), but also in a TN (Twisted Nematic) method, ECB (Electrically Controlled Birefringence) method, or VAN (Vertical Aligned Nematic) type liquid crystal device (electro-optical device), The present invention may be applied when forming a thin film pattern having a narrow opening pattern by wet etching.

  In the above embodiment, a polysilicon film or an amorphous silicon film is used as the semiconductor layer. However, the present invention may be applied to an electro-optical device using a single crystal silicon layer as the semiconductor layer.

  In the first and second embodiments, the case where the electro-optical device 100 is a liquid crystal device has been described as an example. However, an element substrate used for an electro-optical device such as an organic electroluminescence device is also an element substrate used for the liquid crystal device. Similarly to the above, it is configured as an electrical solid state device in which wirings and field effect transistors are formed. Therefore, the present invention may be applied to an element substrate used for an organic electroluminescence device or the like.

  Furthermore, the present invention may be applied to devices other than the element substrate of the electro-optical device as long as it is a device (electric solid device) in which a thin film pattern such as wiring is formed on the substrate.

[Example of mounting on electronic devices]
Next, an electronic apparatus to which the electro-optical device 100 according to the above-described embodiment is applied will be described. FIG. 7A shows a configuration of a mobile personal computer including the electro-optical device 100. The personal computer 2000 includes an electro-optical device 100 as a display unit and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. FIG. 7B shows a configuration of a mobile phone provided with the electro-optical device 100. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 100 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled. FIG. 7C shows a configuration of a personal digital assistant (PDA) to which the electro-optical device 100 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 as a display unit. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 100.

  As an electronic apparatus to which the electro-optical device 100 is applied, in addition to those shown in FIG. 7, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, Examples include calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. The electro-optical device 100 described above can be applied as a display unit of these various electronic devices.

(A), (b) is the top view which looked at the electro-optical apparatus to which this invention is applied from the opposite substrate side with each component formed on it, and its HH 'sectional drawing, respectively. FIG. 6 is an equivalent circuit diagram illustrating an electrical configuration of an image display region of an element substrate used in an electro-optical device to which the present invention is applied. 2A and 2B are a cross-sectional view of one pixel of the electro-optical device according to Embodiment 1 of the present invention and a plan view of pixels adjacent to each other in the element substrate. FIG. 5 is a process cross-sectional view illustrating a method for manufacturing an element substrate used in the electro-optical device according to Embodiment 1 of the invention. It is explanatory drawing of the pixel electrode formation process shown in FIG. FIGS. 7A and 7B are a cross-sectional view of one pixel of the electro-optical device according to Embodiment 2 of the present invention, and a plan view of adjacent pixels on the element substrate, respectively. It is explanatory drawing of the electronic device using the electro-optical apparatus which concerns on this invention.

Explanation of symbols

1a..Semiconductor layer, 3a..Scan line, 5a..Data line, 7..Translucent conductive film (thin film), 7a..Pixel electrode (thin film pattern), 7b..Slit of pixel electrode (opening pattern) ), 7e..Linear electrode portion, 9a..Common electrode, 10..Element substrate (electrical solid state device), 20..Counter substrate, 30..Field effect transistor, 96..Resist mask (etching mask) 96b ... Mask opening, 96e ... Mask linear part, 96f ... Side face of mask linear part, 100 ... Electro-optical device

Claims (12)

A thin film forming step of forming a thin film on the substrate;
An etching mask forming step of forming, on the upper surface of the thin film, an etching mask in which side surfaces facing each other across the mask opening are inclined upwardly;
An etching step of performing wet etching on the thin film from the mask opening;
A method for manufacturing an electrical solid state device.   The method of manufacturing an electrical solid state device according to claim 1, wherein the etching mask has a thickness of 0.7 μm or less.   The method of manufacturing an electrical solid state device according to claim 1, wherein the tapered surface forms an angle of 60 ° or less with respect to the substrate surface of the substrate.   4. The method for manufacturing an electrical solid state device according to claim 1, wherein a width dimension of the bottom of the mask opening in the etching mask is 1.5 μm or less. 5.   5. The method of manufacturing an electrical solid state device according to claim 1, wherein an opening width of the opening pattern formed in the thin film by the etching step is 2.5 μm or less.   The etching mask forming step includes a resist coating step of applying a positive photoresist on the upper surface of the thin film, an exposure step of exposing a region where the mask opening is to be formed in the photoresist, and the exposed photomask. A method for producing an electrical solid state device according to claim 1, further comprising: a developing step for developing the resist.   The method of manufacturing an electrical solid state device according to claim 6, wherein the photoresist contains a dye. The etching mask includes a plurality of linear mask portions arranged in parallel,
The mask opening is formed in a slit shape between each of the plurality of linear mask portions,
The method for manufacturing an electrical solid state device according to any one of claims 1 to 7, wherein a side surface portion of the linear mask portion is the tapered surface.   The method of manufacturing an electrical solid state device according to any one of claims 1 to 8, wherein the thin film is an ITO film or an IZO film.   An electrical solid state device manufactured by the method according to any one of claims 1 to 9. An electro-optical device comprising the electrical solid device according to claim 10,
The electro-optical device is an element substrate for an electro-optical device having a pixel electrode on the substrate. A common electrode is formed on the element substrate to form a horizontal electric field with respect to the liquid crystal with the pixel electrode.
12. The electro-optical device according to claim 11, wherein one of the pixel electrode and the common electrode is configured by the thin film in which a slit-shaped opening pattern is formed by the etching process.

Images