JP2010103350A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010103350A
JP2010103350A JP2008274256A JP2008274256A JP2010103350A JP 2010103350 A JP2010103350 A JP 2010103350A JP 2008274256 A JP2008274256 A JP 2008274256A JP 2008274256 A JP2008274256 A JP 2008274256A JP 2010103350 A JP2010103350 A JP 2010103350A
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semiconductor chip
convex portion
solder
metal plate
semiconductor device
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JP5131148B2 (en
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Akihiro Niimi
新美　　彰浩
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To reduce stress generated at an end of solder joined to an electrode on an upper surface of a semiconductor chip as much as possible. <P>SOLUTION: The semiconductor device is provided with a projection 22 from a position on an upper surface of a first metal plate 13 which corresponds to an end of an electrode for soldering to a position corresponding to inside an end of a metal block 15, and the film thickness of solder 16 between an upper surface of the projection 22 and a lower surface of the semiconductor chip 12 is made less than the film thickness of solder 16 between the upper surface of the first metal plate 13 other than the projection 22 and the lower surface of the semiconductor chip 12, thereby reducing the stress generated at the end of the solder 16 joined to the electrode for soldering on the upper surface of the semiconductor chip 12 as much as possible. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体チップの両面にヒートシンクを半田付けするように構成された半導体装置に関する。   The present invention relates to a semiconductor device configured to solder heat sinks to both surfaces of a semiconductor chip.

高耐圧・大電流用のパワーＩＣ（ＩＧＢＴやＭＯＳＦＥＴ等）の半導体チップ（半導体素子）は、使用時の発熱が大きいため、半導体チップからの放熱性を向上させるための構成が必要である。この構成の一例として、半導体チップの両面にヒートシンク（金属板）を半田付けする構成が考えられており、例えば特許文献１に記載されている。   A semiconductor chip (semiconductor element) of a power IC (IGBT, MOSFET, etc.) for high withstand voltage and large current generates a large amount of heat during use, and thus requires a configuration for improving heat dissipation from the semiconductor chip. As an example of this configuration, a configuration in which a heat sink (metal plate) is soldered to both surfaces of a semiconductor chip is considered, and is described in Patent Document 1, for example.

上記構成の半導体装置１は、図１１に示すように、例えばＩＧＢＴからなる半導体チップ２と、下側ヒートシンク３と、上側ヒートシンク４と、ターミナルブロック５とを備えて構成されている。半導体チップ２の下面全体と下側ヒートシンク３との間は半田６により接合され、半導体チップ２の上面に設けられた半田付け用の電極（エミッタ電極）７（図１２参照）とターミナルブロック５との間は半田６により接合されている。ターミナルブロック５の上面と上側ヒートシンク４の下面との間は半田６により接合されている。尚、図１２において、８はシリコン基板、８ａは活性領域、９ａはＡｌ層、９ｂは保護膜である。
特開２００５−１１６８７５号公報 As shown in FIG. 11, the semiconductor device 1 having the above configuration includes a semiconductor chip 2 made of, for example, an IGBT, a lower heat sink 3, an upper heat sink 4, and a terminal block 5. The entire lower surface of the semiconductor chip 2 and the lower heat sink 3 are joined by solder 6, soldering electrodes (emitter electrodes) 7 (see FIG. 12) provided on the upper surface of the semiconductor chip 2, the terminal block 5, and the like. These are joined by solder 6. The upper surface of the terminal block 5 and the lower surface of the upper heat sink 4 are joined by solder 6. In FIG. 12, 8 is a silicon substrate, 8a is an active region, 9a is an Al layer, and 9b is a protective film.
JP 2005-116875 A

上記構成の場合、半導体チップ２のオンオフに伴う温度変化が繰り返されたときに、半導体チップ２を構成するシリコンの線膨張係数と半田６の線膨張係数の違いにより、繰り返し応力が発生し、半田６が劣化することがあった。特に、半導体チップ２の上面の電極７に接合された半田６の端部（エッジ部）には、大きな繰り返し応力が作用して、クラック６ａが生ずることがあった（図１２）。クラック６ａが生ずると、図１２に示すように、電流集中が発生する部分Ａが発生する。そして、電流集中が発生すると、その部分Ａが発熱し、該熱により半導体チップ２が破壊されるという問題点があった。このため、半導体チップ２の上面の電極７に接合された半田６の端部に発生する応力を極力低減することが望まれている。   In the case of the above configuration, when the temperature change accompanying the on / off of the semiconductor chip 2 is repeated, a stress is repeatedly generated due to the difference between the linear expansion coefficient of the silicon constituting the semiconductor chip 2 and the linear expansion coefficient of the solder 6. 6 sometimes deteriorated. In particular, a large repetitive stress acts on the end portion (edge portion) of the solder 6 joined to the electrode 7 on the upper surface of the semiconductor chip 2 to cause a crack 6a (FIG. 12). When the crack 6a occurs, a portion A where current concentration occurs is generated as shown in FIG. When current concentration occurs, the portion A generates heat, and the semiconductor chip 2 is destroyed by the heat. For this reason, it is desired to reduce the stress generated at the end portion of the solder 6 joined to the electrode 7 on the upper surface of the semiconductor chip 2 as much as possible.

そこで、本発明の目的は、半導体チップの上面の電極に接合された半田の端部に発生する応力を極力低減することができる半導体装置を提供することにある。   Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing as much as possible the stress generated at the end portion of the solder bonded to the electrode on the upper surface of the semiconductor chip.

請求項１の発明によれば、第１の金属板の上面における半田付け用電極の端部に対応する部位から金属ブロックの端部の内側に対応する部位まで凸部を設け、この凸部の上面と半導体チップの下面との間の半田の膜厚を、第１の金属板の凸部以外の部分の上面と半導体チップの下面との間の半田の膜厚よりも薄くするように構成したので、半導体チップの上面の半田付け用電極に接合された半田の端部に発生する応力を極力低減することができる。   According to the first aspect of the present invention, the convex portion is provided from the portion corresponding to the end portion of the soldering electrode on the upper surface of the first metal plate to the portion corresponding to the inner side of the end portion of the metal block. The thickness of the solder between the upper surface and the lower surface of the semiconductor chip is configured to be smaller than the thickness of the solder between the upper surface of the portion other than the convex portion of the first metal plate and the lower surface of the semiconductor chip. Therefore, the stress generated at the end of the solder joined to the soldering electrode on the upper surface of the semiconductor chip can be reduced as much as possible.

請求項２の発明によれば、凸部を半導体チップの下面に設けるように構成したので、請求項１の発明と同じ作用効果を得ることができる。
請求項３の発明によれば、凸部の高さ寸法を、前記第１の金属板の前記凸部以外の部分の上面と前記半導体チップの下面との間の半田の膜厚のほぼ５０％〜８０％程度としたので、前記応力を確実に低減することができる。 According to the second aspect of the invention, since the convex portion is provided on the lower surface of the semiconductor chip, the same effect as that of the first aspect of the invention can be obtained.
According to invention of Claim 3, the height dimension of a convex part is about 50% of the film thickness of the solder between the upper surface of parts other than the said convex part of the said 1st metal plate, and the lower surface of the said semiconductor chip. Since it is about -80%, the stress can be surely reduced.

また、請求項４の発明のように、前記凸部は、前記半田付け用電極の外周部に沿うように全周に設けられていることが好ましい。更に、請求項５の発明のように、前記凸部は、前記半田付け用電極の外周部に沿うように間欠的に設けられていることが好ましい。   Further, as in the invention of claim 4, it is preferable that the convex portion is provided on the entire periphery along the outer peripheral portion of the soldering electrode. Further, as in the invention of claim 5, the convex portion is preferably provided intermittently along the outer peripheral portion of the soldering electrode.

以下、本発明の第１の実施例について、図１ないし図７を参照して説明する。まず、図１は、本実施例の半導体装置の概略構成を示す断面図である。この図１に示すように、本実施例の半導体装置１１は、半導体チップ（半導体素子）１２と、下側ヒートシンク（第１の金属板）１３と、上側ヒートシンク（第２の金属板）１４と、ヒートシンクを構成するターミナルブロック（金属ブロック）１５とを備えて構成されている。   Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. First, FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device of this embodiment. As shown in FIG. 1, the semiconductor device 11 of this embodiment includes a semiconductor chip (semiconductor element) 12, a lower heat sink (first metal plate) 13, and an upper heat sink (second metal plate) 14. And a terminal block (metal block) 15 constituting a heat sink.

上記半導体チップ１２は、例えばＩＧＢＴやＭＯＳＦＥＴやサイリスタやダイオード等のパワー半導体素子から構成されている。この半導体チップ１２の形状は、本実施例の場合、矩形（例えば一辺が１３ｍｍ程度の正方形）の薄板状である。また、下側ヒートシンク１３、上側ヒートシンク１４及びターミナルブロック１５は、例えばＣｕで構成されている。尚、上記Ｃｕに代えて、Ａｌ等の熱伝導性及び電気伝導性の良い金属で構成しても良い。   The semiconductor chip 12 is composed of a power semiconductor element such as an IGBT, MOSFET, thyristor, or diode. In the case of the present embodiment, the shape of the semiconductor chip 12 is a thin plate shape of a rectangle (for example, a square having a side of about 13 mm). The lower heat sink 13, the upper heat sink 14, and the terminal block 15 are made of Cu, for example. Note that, instead of Cu, a metal having good thermal conductivity and electrical conductivity such as Al may be used.

半導体チップ１２の下面の全面は、半田付け用の電極（チップ１２が例えばＩＧＢＴである場合、コレクタ電極）となっている。この半導体チップ１２の下面全面と下側ヒートシンク１３の上面との間は、接合部材である例えば半田１６によって接合されている。   The entire lower surface of the semiconductor chip 12 is an electrode for soldering (a collector electrode when the chip 12 is an IGBT, for example). The entire lower surface of the semiconductor chip 12 and the upper surface of the lower heat sink 13 are joined by, for example, solder 16 which is a joining member.

また、半導体チップ１２の上面には、半田付け用の電極（チップ１２が例えばＩＧＢＴである場合、エミッタ電極）１７（図２参照）と、図示しないワイヤボンディング用の電極（チップ１２が例えばＩＧＢＴである場合、ゲート電極や各種センサ用電極等）と、図示しないガードリング等が設けられている。半導体チップ１２の上面の半田付け用電極１７とターミナルブロック１５の下面全面との間は、半田１６によって接合されている。尚、半導体チップ１２のワイヤボンディング用の電極とリードフレーム１９との間は、ボンディングワイヤ２０により接続されている。   Further, on the upper surface of the semiconductor chip 12, an electrode 17 for soldering (emitter electrode when the chip 12 is an IGBT, for example) 17 (see FIG. 2) and an electrode for wire bonding (not shown) (the chip 12 is an IGBT, for example). In some cases, a gate electrode, various sensor electrodes, etc.) and a guard ring (not shown) are provided. The soldering electrode 17 on the upper surface of the semiconductor chip 12 and the entire lower surface of the terminal block 15 are joined by solder 16. A wire bonding electrode of the semiconductor chip 12 and the lead frame 19 are connected by a bonding wire 20.

更に、ターミナルブロック１５の上面と上側ヒートシンク１４の下面との間は、半田１６によって接合されている。そして、半導体装置１１のほぼ全体は、樹脂（例えばエポキシ樹脂）２１によりモールドされている。尚、半導体装置１１を樹脂２１でモールドするに当たっては、上下型からなる成形型（図示しない）を使用している。また、下側ヒートシンク１３の下面、上側ヒートシンク１４の上面、各ヒートシンク１３、１４の端子部（図示しない）及びリードフレーム１９の端子部は、モールド樹脂２１（成形体）から露出または突出するように構成されている。上記構成においては、半導体チップ１２の両面からヒートシンク１３、１４及びターミナルブロック１５を介して放熱される構成となっている。   Furthermore, the upper surface of the terminal block 15 and the lower surface of the upper heat sink 14 are joined by solder 16. Then, almost the entire semiconductor device 11 is molded with a resin (for example, epoxy resin) 21. Note that when the semiconductor device 11 is molded with the resin 21, a molding die (not shown) composed of an upper and lower mold is used. The lower surface of the lower heat sink 13, the upper surface of the upper heat sink 14, the terminal portions (not shown) of the heat sinks 13 and 14, and the terminal portions of the lead frame 19 are exposed or protruded from the mold resin 21 (molded body). It is configured. In the above configuration, heat is radiated from both surfaces of the semiconductor chip 12 through the heat sinks 13 and 14 and the terminal block 15.

さて、図２に示すように、下側ヒートシンク１３の上面における半田付け用電極１７の端部１７ａに対応する部位からターミナルブロック１５の端部１５ａの内側に対応する部位までの部分に凸部２２を設けた。この場合、凸部２２の中心位置を半田１６の端部にほぼ一致させるように配置している（図８（ｃ）参照）。尚、凸部２２の中心位置を左右に多少シフトさせても良い。上記凸部２２の高さ寸法ｈは、下側ヒートシンク１３の上記凸部２２以外の部分の上面と、半導体チップ１２の下面との間に設けられた半田１６の膜厚ｄのほぼ５０％程度となるように構成されている。   Now, as shown in FIG. 2, the convex portion 22 extends from a portion corresponding to the end portion 17 a of the soldering electrode 17 on the upper surface of the lower heat sink 13 to a portion corresponding to the inside of the end portion 15 a of the terminal block 15. Was provided. In this case, it arrange | positions so that the center position of the convex part 22 may correspond with the edge part of the solder 16 (refer FIG.8 (c)). The center position of the convex portion 22 may be shifted slightly to the left and right. The height h of the convex portion 22 is about 50% of the film thickness d of the solder 16 provided between the upper surface of the lower heat sink 13 other than the convex portion 22 and the lower surface of the semiconductor chip 12. It is comprised so that.

具体的には、凸部２２の高さ寸法ｈは例えば０．０４ｍｍ程度に設定されている。上記半田１６の膜厚ｄは例えば０．０８ｍｍ程度に設定されている。これにより、凸部２２の上面と半導体チップ１２の下面との間の半田１６の膜厚（例えば０．０４ｍｍ程度）が、下側ヒートシンク１３の凸部２２以外の部分の上面と半導体チップ１２の下面との間の半田１６の膜厚（例えば０．０８ｍｍ程度）よりも薄くなるように構成した。ここで、凸部２２を下側ヒートシンク１３に形成するに際しては、例えばプレス成形により形成したり、エッチングにより形成したり、金属層を堆積することにより形成したりする方法が好ましい。   Specifically, the height h of the convex portion 22 is set to about 0.04 mm, for example. The film thickness d of the solder 16 is set to about 0.08 mm, for example. Thereby, the film thickness (for example, about 0.04 mm) of the solder 16 between the upper surface of the convex portion 22 and the lower surface of the semiconductor chip 12 is set so that the upper surface of the lower heat sink 13 other than the convex portion 22 and the semiconductor chip 12 It was configured to be thinner than the film thickness (for example, about 0.08 mm) of the solder 16 between the lower surface. Here, when forming the convex part 22 in the lower heat sink 13, for example, a method of forming by pressing, forming by etching, or depositing a metal layer is preferable.

尚、半導体チップ１２の上面の半田付け用電極１７とターミナルブロック１５の下面との間に設けられた半田１６の膜厚、並びに、ターミナルブロック１５の上面と上側ヒートシンク１４の下面との間に設けられた半田１６の膜厚も、例えば０．０８ｍｍ程度に設定されている。ここで、０．０８ｍｍ程度の膜厚の半田１６を形成するに際しては、半田１６の膜中に外径寸法が０．０８ｍｍ程度のボールやワイヤを埋設するような周知の方法を用いることが好ましい。   Incidentally, the film thickness of the solder 16 provided between the soldering electrode 17 on the upper surface of the semiconductor chip 12 and the lower surface of the terminal block 15, and between the upper surface of the terminal block 15 and the lower surface of the upper heat sink 14 are provided. The film thickness of the solder 16 thus set is also set to about 0.08 mm, for example. Here, when forming the solder 16 having a thickness of about 0.08 mm, it is preferable to use a known method in which a ball or wire having an outer diameter of about 0.08 mm is embedded in the film of the solder 16. .

また、下側ヒートシンク１３及び上側ヒートシンク１４は、厚さ寸法が例えば約２ｍｍ程度の板材で形成されている。ターミナルブロック１５は、厚さ寸法が例えば約１．５ｍｍ程度の板材で形成されており、その大きさは、半導体チップ１２の上面の半田付け用電極１７の大きさとほぼ同じ大きさである。また、半導体チップ１２の厚さ寸法は、例えば約０．１４ｍｍ程度である。   The lower heat sink 13 and the upper heat sink 14 are formed of a plate material having a thickness dimension of about 2 mm, for example. The terminal block 15 is formed of a plate material having a thickness of about 1.5 mm, for example, and the size thereof is approximately the same as the size of the soldering electrode 17 on the upper surface of the semiconductor chip 12. Moreover, the thickness dimension of the semiconductor chip 12 is about 0.14 mm, for example.

また、図３に示すように、上記凸部２２は、半田付け用電極１７の外周部に沿うように全周に、即ち、矩形枠状をなすように設けられている。凸部２２の幅寸法ｗ（図２参照）は、例えば２．０ｍｍ程度に設定されている。ここで、半導体チップ１２に冷熱サイクル（１８０℃から２５℃へ（モールド成形時の温度変化）、更に１５０℃と−４０℃との間の冷熱サイクルを１回）を加えた後、半導体チップ１２の上面の応力分布を測定した結果を、図４に示す。   Further, as shown in FIG. 3, the convex portion 22 is provided along the outer peripheral portion of the soldering electrode 17 so as to form a rectangular frame shape. The width dimension w (see FIG. 2) of the convex portion 22 is set to about 2.0 mm, for example. Here, after the semiconductor chip 12 is subjected to a cooling cycle (from 180 ° C. to 25 ° C. (temperature change during molding), and further a cooling cycle between 150 ° C. and −40 ° C. once), the semiconductor chip 12 FIG. 4 shows the result of measuring the stress distribution on the upper surface.

この図４において、実線Ｐ１は本実施例（凸部２２の幅寸法ｗ＝２．０ｍｍ）の測定結果を示し、実線Ｐ２は本実施例において凸部２２の幅寸法ｗを１．０ｍｍに設定した場合の測定結果を示し、実線Ｐ３は本実施例において凸部２２の幅寸法ｗを０．５ｍｍに設定した場合の測定結果を示し、実線Ｐ４は従来構成（即ち、凸部２２を設けない構成）の測定結果を示している。尚、図４の左右両端の位置が半導体チップ１２の両端の位置に対応し、図４中の位置ｔ１、ｔ２がターミナルブロック１５の両端の位置に対応している。   In FIG. 4, the solid line P1 shows the measurement result of the present example (width dimension w = 2.0 mm of the convex portion 22), and the solid line P2 sets the width dimension w of the convex portion 22 to 1.0 mm in the present example. In this embodiment, the solid line P3 indicates the measurement result when the width dimension w of the convex portion 22 is set to 0.5 mm, and the solid line P4 indicates the conventional configuration (that is, the convex portion 22 is not provided). The measurement result of (configuration) is shown. 4 correspond to the positions of both ends of the semiconductor chip 12, and the positions t 1 and t 2 in FIG. 4 correspond to the positions of both ends of the terminal block 15.

上記図４の実線Ｐ１、Ｐ４から、本実施例の凸部２２を下側ヒートシンク１３の上面に設けたことにより、半導体チップ１２の上面に発生する応力を大幅に小さく（２８．４ＭＰａから１７．７ＭＰａへ）できたことがわかる。   From the solid lines P1 and P4 in FIG. 4, the stress generated on the upper surface of the semiconductor chip 12 is significantly reduced (from 28.4 MPa to 17.5) by providing the convex portion 22 of this embodiment on the upper surface of the lower heat sink 13. It can be seen that it was possible to 7 MPa).

尚、半導体チップ１２に上記した冷熱サイクルを加えた後、半導体チップ１２の下面の応力分布を測定した結果を、図５に示す。この図５において、実線Ｑ１は本実施例（凸部２２の幅寸法ｗ＝２．０ｍｍ）の測定結果を示し、実線Ｑ２は本実施例において凸部２２の幅寸法ｗを１．０ｍｍに設定した場合の測定結果を示し、実線Ｑ３は本実施例において凸部２２の幅寸法ｗを０．５ｍｍに設定した場合の測定結果を示し、実線Ｑ４は従来構成（即ち、凸部２２を設けない構成）の測定結果を示している。   In addition, the result of having measured the stress distribution of the lower surface of the semiconductor chip 12 after applying the above-mentioned cooling / heating cycle to the semiconductor chip 12 is shown in FIG. In FIG. 5, the solid line Q1 indicates the measurement result of the present example (width dimension w = 2.0 mm of the convex portion 22), and the solid line Q2 indicates the width dimension w of the convex portion 22 is set to 1.0 mm in the present example. In this embodiment, the solid line Q3 shows the measurement result when the width dimension w of the convex portion 22 is set to 0.5 mm, and the solid line Q4 shows the conventional configuration (that is, the convex portion 22 is not provided). The measurement result of (configuration) is shown.

次に、上記凸部２２の高さ寸法ｈを変化させたときに、半導体チップ１２に発生する応力の測定結果を図６に示す。この図６において、横軸は凸部２２の高さ寸法を示し、縦軸は応力の大きさを示す。図６中の実線Ｒ１は半導体チップ１２の上面に発生する応力の大きさを示し、実線Ｒ２は半導体チップ１２の下面に発生する応力の大きさを示している。尚、冷熱サイクルの条件は、図４、図５の場合と同じである。   Next, FIG. 6 shows a measurement result of stress generated in the semiconductor chip 12 when the height dimension h of the convex portion 22 is changed. In FIG. 6, the horizontal axis indicates the height dimension of the convex portion 22, and the vertical axis indicates the magnitude of stress. A solid line R1 in FIG. 6 indicates the magnitude of stress generated on the upper surface of the semiconductor chip 12, and a solid line R2 indicates the magnitude of stress generated on the lower surface of the semiconductor chip 12. The conditions for the cooling / heating cycle are the same as those in FIGS.

上記図６の実線Ｒ１から、凸部２２の高さ寸法が高くなるほど、半導体チップ１２の上面に発生する応力の大きさが小さくなる。これに対して、図６の実線Ｒ２から、凸部２２の高さ寸法が高くなるほど、半導体チップ１２の下面に発生する応力の大きさが大きくなる。従って、凸部２２の高さ寸法を、半田１６の膜厚のほぼ８０％程度に設定すると、半導体チップ１２の上面に発生する応力を最も低減できることがわかる。ただし、下側ヒートシンク１３の加工性や、下側ヒートシンク１３および半導体チップ１２の半田付け性等を考慮して実現性の面から判断すると、凸部２２の高さ寸法を、半田１６の膜厚のほぼ５０％程度に設定することが好ましい。   From the solid line R <b> 1 in FIG. 6, the magnitude of the stress generated on the upper surface of the semiconductor chip 12 decreases as the height of the convex portion 22 increases. On the other hand, from the solid line R2 in FIG. 6, the magnitude of the stress generated on the lower surface of the semiconductor chip 12 increases as the height dimension of the convex portion 22 increases. Therefore, it can be seen that the stress generated on the upper surface of the semiconductor chip 12 can be reduced most when the height of the convex portion 22 is set to about 80% of the film thickness of the solder 16. However, when considering the workability of the lower heat sink 13 and the solderability of the lower heat sink 13 and the semiconductor chip 12 and the like from the viewpoint of feasibility, the height dimension of the protrusion 22 is determined by the film thickness of the solder 16. It is preferable to set it to about 50%.

一方、図７は、凸部２２の位置を変化させたときに、半導体チップ１２の上面に発生する応力の測定結果を示す図である。この図７において、横軸は凸部２２の位置のシフト量を示し、縦軸は応力の大きさを示す。ここで、シフト量とは、凸部２２の中心位置を半田１６（半田付け用の電極１７）の端部に一致させた位置をシフト量が０であるとし、この位置から内側へシフトさせる、または外側へシフトさせるようにしている（図８参照）。この場合、凸部２２の幅寸法は１ｍｍ程度に設定している。尚、冷熱サイクルの条件は、図４、図５、図６の場合と同じである。   On the other hand, FIG. 7 is a diagram illustrating a measurement result of stress generated on the upper surface of the semiconductor chip 12 when the position of the convex portion 22 is changed. In FIG. 7, the horizontal axis indicates the shift amount of the position of the convex portion 22, and the vertical axis indicates the magnitude of stress. Here, the shift amount means that the position where the center position of the convex portion 22 coincides with the end of the solder 16 (soldering electrode 17) is 0 and the shift amount is shifted inward from this position. Alternatively, it is shifted outward (see FIG. 8). In this case, the width dimension of the convex part 22 is set to about 1 mm. The conditions for the cooling / heating cycle are the same as those in FIGS. 4, 5, and 6.

上記図７から、凸部２２の中心位置を半田１６の端部に一致させた位置（即ち、シフト量が０の位置）のときに、半導体チップ１２の上面に発生する応力の大きさを最も低減できることがわかる。そして、凸部２２の一部が半田１６の端部にかかる位置（シフト量が±０．５ｍｍの位置）であれば、半導体チップ１２の上面に発生する応力の大きさを十分低減できることがわかる。   From FIG. 7, the magnitude of the stress generated on the upper surface of the semiconductor chip 12 is maximized when the center position of the convex portion 22 is aligned with the end of the solder 16 (that is, the position where the shift amount is 0). It can be seen that it can be reduced. Then, it can be seen that if the part of the convex portion 22 is located at the end of the solder 16 (the position where the shift amount is ± 0.5 mm), the magnitude of the stress generated on the upper surface of the semiconductor chip 12 can be sufficiently reduced. .

上記した構成の本実施例によれば、下側ヒートシンク１３の上面における半田付け用電極１７の端部に対応する部位からターミナルブロック１５の端部の内側に対応する部位までの部分に凸部２２を設け、凸部２２の上面と半導体チップ１２の下面との間の半田１６の膜厚を、下側ヒートシンク１３の凸部２２以外の部分の上面と半導体チッ１２プの下面との間の半田１６の膜厚よりも薄くするように構成したので、半導体チップ１２の上面に発生する応力の大きさを十分低減することができる。   According to the present embodiment having the above-described configuration, the convex portion 22 extends from the portion corresponding to the end portion of the soldering electrode 17 on the upper surface of the lower heat sink 13 to the portion corresponding to the inner side of the end portion of the terminal block 15. The thickness of the solder 16 between the upper surface of the convex portion 22 and the lower surface of the semiconductor chip 12 is set so that the solder between the upper surface of the lower heat sink 13 other than the convex portion 22 and the lower surface of the semiconductor chip 12 is provided. Since the thickness is smaller than 16, the magnitude of the stress generated on the upper surface of the semiconductor chip 12 can be sufficiently reduced.

尚、上記実施例では、図３に示すように、凸部２２の形状を矩形枠状としたが、これに限られるものではなく、図９（ａ）に示すように、丸みを帯びた矩形枠状としても良いし、また、図９（ｂ）に示すように、４５度回転させ、且つ、幅広に形成した矩形枠状としても良い。更に、図９（ｃ）に示すように、間欠的に設けた矩形枠状としても良いし、また、図９（ｄ）に示すように、半田付け用電極１７の４隅部に形状の異なる凸部（同じ形状の凸部であっても良い）２３を形成するように構成しても良い。更にまた、図９（ｅ）に示すように、矩形枠状を止めて、矩形状としても良く、また、図９（ｆ）に示すように、円形状としても良い。   In the above-described embodiment, as shown in FIG. 3, the shape of the convex portion 22 is a rectangular frame shape. However, the shape is not limited to this, and a rounded rectangle as shown in FIG. It is good also as a frame shape, and as shown in FIG.9 (b), it is good also as a rectangular frame shape which rotated 45 degree | times and was formed wide. Furthermore, as shown in FIG. 9 (c), a rectangular frame shape provided intermittently may be used, and as shown in FIG. 9 (d), the shapes of the four corners of the soldering electrode 17 are different. You may comprise so that the convex part (it may be the convex part of the same shape) 23 is formed. Furthermore, as shown in FIG. 9E, the rectangular frame shape may be stopped to form a rectangular shape, or as shown in FIG. 9F, a circular shape may be used.

また、凸部２２を下側ヒートシンク１３に形成するに際しては、図１０（ａ）に示すように、下側ヒートシンク１３の上面における凸部２２以外の部分に凹部を形成するように構成しても良い。更に、図１０（ｂ）に示すように、下側ヒートシンク１３の上面に凸部を形成することを止めて、半導体チップ１２の下面に凸部２４を形成するように構成しても良い。更にまた、図１０（ｃ）に示すように、下側ヒートシンク１３の上面に凸部を形成することを止めると共に、半導体チップ１２の下面に凸部を形成することも止め、両者の間に、半田１６の膜厚を薄くする金属箔２５を配設するように構成しても良い。この金属箔２５は、半田１６と合金化し、且つ、半田１６よりも硬い金属で構成されている。   Further, when the convex portion 22 is formed on the lower heat sink 13, as shown in FIG. 10A, the concave portion may be formed on a portion other than the convex portion 22 on the upper surface of the lower heat sink 13. good. Furthermore, as shown in FIG. 10B, it may be configured such that the convex portion 24 is formed on the lower surface of the semiconductor chip 12 by stopping the formation of the convex portion on the upper surface of the lower heat sink 13. Furthermore, as shown in FIG. 10C, the formation of the convex portion on the upper surface of the lower heat sink 13 is stopped and the formation of the convex portion on the lower surface of the semiconductor chip 12 is also stopped. You may comprise so that the metal foil 25 which makes the film thickness of the solder 16 thin may be arrange | positioned. The metal foil 25 is made of a metal that is alloyed with the solder 16 and harder than the solder 16.

本発明の第１の実施例を示す半導体装置の断面図Sectional drawing of the semiconductor device which shows 1st Example of this invention 凸部周辺の拡大断面図Enlarged sectional view around the convex part 下側ヒートシンクの平面図Top view of lower heat sink 半導体チップの上面に発生する応力を示す特性図Characteristic diagram showing the stress generated on the upper surface of the semiconductor chip 半導体チップの下面に発生する応力を示す特性図Characteristic diagram showing the stress generated on the lower surface of the semiconductor chip 凸部の高さ寸法と半導体チップの上面および下面に発生する応力との関係を示す特性図Characteristic diagram showing the relationship between the height of the protrusion and the stress generated on the upper and lower surfaces of the semiconductor chip 凸部のシフト量と半導体チップの上面に発生する応力との関係を示す特性図Characteristic diagram showing the relationship between the shift amount of the convex part and the stress generated on the upper surface of the semiconductor chip 凸部のシフト量を説明する拡大断面図Enlarged sectional view explaining the shift amount of the convex part 凸部の変形例を示す図３相当図FIG. 3 equivalent view showing a modification of the convex portion 凸部の変形例を示す図１相当図FIG. 1 equivalent view showing a modification of the convex portion 従来構成を示す図１相当図1 equivalent diagram showing the conventional configuration 要部の拡大断面図Enlarged sectional view of the main part

符号の説明Explanation of symbols

図面中、１１は半導体装置、１２は半導体チップ、１３は下側ヒートシンク（第１の金属板）、１４は上側ヒートシンク（第２の金属板）、１５はターミナルブロック（金属ブロック）、１６は半田、１７は半田付け用電極、１９はリードフレーム、２１は樹脂、２２は凸部、２３は凸部、２４は凸部、２５は金属箔を示す。   In the drawings, 11 is a semiconductor device, 12 is a semiconductor chip, 13 is a lower heat sink (first metal plate), 14 is an upper heat sink (second metal plate), 15 is a terminal block (metal block), and 16 is solder. , 17 is a soldering electrode, 19 is a lead frame, 21 is a resin, 22 is a protrusion, 23 is a protrusion, 24 is a protrusion, and 25 is a metal foil.

Claims (5)

半導体チップと、前記半導体チップの下面全面に半田付けされた第１の金属板と、前記半導体チップの上面に設けられた半田付け用電極に半田付けされた金属ブロックと、前記金属ブロックの上面全面に半田付けされた第２の金属板とを備えて成る半導体装置において、
前記第１の金属板の上面における前記半田付け用電極の端部に対応する部位から前記金属ブロックの端部の内側に対応する部位まで凸部を設け、
前記凸部の上面と前記半導体チップの下面との間の半田の膜厚を、前記第１の金属板の前記凸部以外の部分の上面と前記半導体チップの下面との間の半田の膜厚よりも薄くするように構成したことを特徴とする半導体装置。 A semiconductor chip; a first metal plate soldered to the entire lower surface of the semiconductor chip; a metal block soldered to a soldering electrode provided on the upper surface of the semiconductor chip; and an entire upper surface of the metal block In a semiconductor device comprising a second metal plate soldered to
Providing a convex portion from a portion corresponding to the end of the soldering electrode on the upper surface of the first metal plate to a portion corresponding to the inside of the end of the metal block,
The film thickness of the solder between the upper surface of the convex portion and the lower surface of the semiconductor chip is the thickness of the solder between the upper surface of the portion other than the convex portion of the first metal plate and the lower surface of the semiconductor chip. A semiconductor device characterized by being made thinner. 半導体チップと、前記半導体チップの下面全面に半田付けされた第１の金属板と、前記半導体チップの上面に設けられた半田付け用電極に半田付けされた金属ブロックと、前記金属ブロックの上面全面に半田付けされた第２の金属板とを備えて成る半導体装置において、
前記半導体チップの下面における前記半田付け用電極の端部に対応する部位から前記金属ブロックの端部の内側に対応する部位まで凸部を設け、
前記凸部の下面と前記第１の金属板の上面との間の半田の膜厚を、前記半導体チップの前記凸部以外の部分のした面と前記第１の金属板の上面との間の半田の膜厚よりも薄くするように構成したことを特徴とする半導体装置。 A semiconductor chip; a first metal plate soldered to the entire lower surface of the semiconductor chip; a metal block soldered to a soldering electrode provided on the upper surface of the semiconductor chip; and an entire upper surface of the metal block In a semiconductor device comprising a second metal plate soldered to
Providing a convex portion from a portion corresponding to the end of the soldering electrode on the lower surface of the semiconductor chip to a portion corresponding to the inside of the end of the metal block,
The thickness of the solder between the lower surface of the convex portion and the upper surface of the first metal plate is set between the surface of the semiconductor chip other than the convex portion and the upper surface of the first metal plate. A semiconductor device configured to be thinner than the thickness of solder. 前記凸部の高さ寸法は、前記第１の金属板の前記凸部以外の部分の上面と前記半導体チップの下面との間の半田の膜厚のほぼ５０％〜８０％程度であることを特徴とする請求項１または２記載の半導体装置。   The height of the convex portion is approximately 50% to 80% of the thickness of the solder between the upper surface of the portion other than the convex portion of the first metal plate and the lower surface of the semiconductor chip. 3. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: 前記凸部は、前記半田付け用電極の外周部に沿うように全周に設けられていることを特徴とする請求項１ないし３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the convex portion is provided on the entire periphery along the outer peripheral portion of the soldering electrode. 5. 前記凸部は、前記半田付け用電極の外周部に沿うように間欠的に設けられていることを特徴とする請求項１ないし３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the convex portion is provided intermittently along the outer peripheral portion of the soldering electrode.
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