JP2010093171A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress a current leak from an upper electrode, and a method of manufacturing the same. <P>SOLUTION: The semiconductor device has a semiconductor bottom structure portion 30, lower electrode wiring 41, a lower electrode 51, a dielectric film 61, and an upper electrode 71. The lower electrode wiring 41 is provided on the semiconductor bottom structure 30. The lower electrode 51 is provided on the lower electrode wiring 41. The dielectric film 61 is provided on the lower electrode 51. The upper electrode 71 is electrically insulated from the lower electrode 51, and provided on part of the dielectric film 61. The lower electrode 51 is electrically connected to the lower electrode wiring 41 on a surface SB of the lower electrode 51 which faces the lower electrode wiring 41. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

Some semiconductor devices include an MIM (Metal-Insulator-Metal) capacitor, which is an analog element, in addition to a semiconductor element. The MIM capacitor has a lower electrode formed on the substrate, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film. Such MIM capacitors include, for example, Japanese Patent Application Laid-Open No. 2003-142588 (Patent Document 1), Japanese Patent Application Laid-Open No. 2003-158190 (Patent Document 2), Japanese Patent Application Laid-Open No. 2002-043517 (Patent Document 3), and Japanese Patent Application Laid-Open No. 2005. -285842 (patent document 4) and the like.
JP 2003-142588 A JP 2003-158190 A JP 2002-043517 A JP 2005-285842 A

  The prior art has a problem that current leakage from the upper electrode is likely to occur.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing current leakage from the upper electrode and a method for manufacturing the same.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, wiring, a lower electrode, a dielectric film, and an upper electrode. The wiring is provided on the semiconductor substrate. The lower electrode is provided on the wiring. The dielectric film is provided on the lower electrode. The upper electrode is electrically insulated from the lower electrode and is provided on a part of the dielectric film. The lower electrode is electrically connected to the wiring on the surface facing the wiring of the lower electrode.

  A semiconductor device according to another embodiment of the present invention includes a semiconductor substrate, a lower electrode, a dielectric film, an upper electrode, a coating film, and an insulating film. The lower electrode is provided on the semiconductor substrate. The dielectric film is provided on the lower electrode and is made of the first material. The upper electrode is provided on a part of the dielectric film. The coating film covers the dielectric film and the upper electrode and is made of the first material. The insulating film covers the coating film and is made of a second material different from the first material.

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps.
Wiring is formed on the semiconductor substrate. A lower metal layer electrically connected to the wiring is formed on the wiring. A dielectric layer is formed on the lower metal layer. An upper metal layer is formed on the dielectric layer. The upper metal layer is etched by the first mask pattern formed on the upper metal layer to form the upper electrode. A second mask pattern including the upper electrode in plan view is formed on the dielectric layer and the upper electrode. By patterning the dielectric layer and the lower metal layer by etching using the second mask pattern as a mask, a dielectric film and a lower electrode are formed from the dielectric layer and the lower metal layer, respectively.

A method for manufacturing a semiconductor device according to another embodiment of the present invention includes the following steps.
A lower metal layer is deposited on the semiconductor substrate. A dielectric layer made of a first material is deposited on the lower metal layer. An upper metal layer is formed on the dielectric layer. The upper metal layer is etched by the first mask pattern formed on the upper metal layer to form the upper electrode. A cover layer made of a first material and covering the dielectric layer and the upper electrode is deposited. A second mask pattern including the upper electrode in plan view is formed on the coating layer. By patterning the coating layer, the dielectric layer, and the lower metal layer by etching using the second mask pattern as a mask, the coating film and the dielectric film are respectively formed from the coating layer, the dielectric layer, and the lower metal layer. And a lower electrode are formed. An insulating film made of a second material different from the first material is deposited on the peritoneum.

  According to the semiconductor device according to one embodiment of the present invention, the lower electrode is electrically connected to the wiring on the surface of the lower electrode facing the wiring. Therefore, it is not necessary to establish electrical connection with the lower electrode on the surface of the lower electrode facing the dielectric film, so that leakage occurs along the interface of the dielectric film between the electrical path to the lower electrode and the upper electrode. It is possible to prevent a current from flowing.

  According to the semiconductor device according to another embodiment of the present invention, the upper electrode is provided on the dielectric film made of the first material and is covered with the coating film made of the first material. Shielded from the surroundings by the first material. Therefore, current leakage from the upper electrode can be suppressed.

  According to the method of manufacturing a semiconductor device according to one embodiment of the present invention, the lower electrode electrically connected to the wiring is formed on the wiring. Therefore, it is not necessary to establish electrical connection with the lower electrode on the surface of the lower electrode facing the dielectric film, so that leakage occurs along the interface of the dielectric film between the electrical path to the lower electrode and the upper electrode. It is possible to prevent a current from flowing.

  According to the method for manufacturing a semiconductor device according to another embodiment of the present invention, after the upper electrode is formed on the dielectric layer made of the first material, the covering layer made of the first material covering the upper electrode. Is deposited. Therefore, since the upper electrode is shielded from the surroundings by the first material, current leakage from the upper electrode can be suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device of this embodiment includes a semiconductor bottom structure portion 30, a lower electrode wiring 41, a normal wiring 42, a shield metal 43, an insulating film 80, a via contact 31, and a lower portion. Electrode 51, normal wiring 52, dielectric film 61, insulating film 62, upper electrode 71, insulating film 81, via contact 32, via contact 33, wiring 44, wiring 45, and insulating film 101.

  The semiconductor bottom structure portion 30 includes a semiconductor substrate, a transistor formed on the semiconductor substrate, and an interlayer insulating film that covers the transistor and the semiconductor substrate.

  The upper electrode 71 is electrically insulated by the lower electrode 51 and the dielectric film 61. The lower electrode 51 is electrically connected to the lower electrode wiring 41 by the via contact 31 on the lower surface SB facing the lower electrode wiring 41 of the lower electrode 51.

As a material of the dielectric film 61, at least one of SiO (silicon oxide film), SiON (silicon oxynitride film), SiN (silicon nitride film), SiCN (silicon carbonitride film), and SiC (silicon carbide film) is used. Can be used. For example, in order to set the MIM capacitance to 1 fF / μm ² , when the dielectric film 61 is SiON, the thickness of the dielectric film 61 is about 70 nm.

  The material of the insulating film 81 is different from that of the dielectric film 61. Specifically, the material of the insulating film 81 can be at least one of SiO (silicon oxide film), SiOF (silicon oxyfluoride film), SiOC (silicon oxycarbide film), and MSQ (Methylsilsesquioxane).

  Each of the lower electrode wiring 41, the normal wiring 42, the shield metal 43, the lower electrode 51, and the normal wiring 52 is made of, for example, a laminated film of TiN / Ti / AlCu / TiN / Ti. The upper electrode 71 is made of metal. The polymer film PM is made of a polymer attached as a side effect in etching for patterning the dielectric film 61.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 2 to 7 are partial cross sectional views schematically showing the method for manufacturing the semiconductor device in the first embodiment of the present invention in the order of steps.

  Referring to FIG. 2, first, lower electrode wiring 41, normal wiring 42, and shield metal 43 are formed on semiconductor bottom structure portion 30, each of which is covered with insulating film 101. Next, an insulating film 80 is deposited. Next, via contact 31 electrically connected to lower electrode wiring 41 is formed using, for example, a damascene method.

  Referring to FIG. 3, lower metal layer 50, dielectric layer 60, and upper metal layer 70 are sequentially deposited on insulating film 80 on which via contact 31 is formed.

  Referring mainly to FIG. 4, resist mask pattern MP1 is formed on upper metal layer 70 (FIG. 3). The upper metal layer 70 (FIG. 3) is etched using the resist mask pattern MP1 as a mask and the dielectric layer 60 as an etching stopper. In this etching, overetching may be performed to such an extent that the dielectric layer 60 exposed from the resist mask pattern MP1 is not lost. Next, the resist mask pattern MP1 is removed.

  Depending on the etching conditions, the polymer film PM (FIG. 1) may be formed as a side effect during etching.

  Referring mainly to FIG. 5, the upper electrode 71 is formed from the upper metal layer 70 (FIG. 3) by the above process. Next, a photoresist is applied, exposed and developed. In this exposure, the dielectric layer 60 functions as a BARL (Bottom Antireflective Layer).

  Referring to FIG. 6, resist mask pattern MP2 is formed by the above process. At this time, the resist mask pattern MP2 is formed so as to include the upper electrode 71 in plan view. Next, etching is performed using resist mask pattern MP2 as a mask and insulating film 80 as an etching stopper. Next, the resist mask pattern MP2 is removed.

  Referring mainly to FIG. 7, dielectric film 61 and insulating film 62 are formed from dielectric layer 60 (FIG. 5) by the above-described steps. Further, the lower electrode 51 and the normal wiring 52 are formed from the lower metal layer 50 (FIG. 5). Next, the insulating film 81, the via contact 32, the via contact 33, the wiring 44, and the wiring 45 shown in FIG. 1 are formed by using, for example, a damascene method.

As described above, the semiconductor device of the present embodiment is manufactured.
FIG. 8 is a partial cross-sectional view schematically showing the configuration of the semiconductor device in the first comparative example. Referring mainly to FIG. 8, the semiconductor device of this comparative example has via contact 31C and lower electrode wiring 41C instead of via contact 31 and lower electrode wiring 41 shown in FIG. The via contact 31 </ b> C is connected to the upper surface ST of the lower electrode 51 facing the dielectric film 61.

  In this comparative example, a leak current easily flows through the interface of the dielectric film 61 between the via contact 31C and the upper electrode 71. In particular, when the polymer film PM is formed on the dielectric film 61, the electric resistance at the interface of the dielectric film 61 becomes small, and thus the leak current tends to increase.

  FIG. 9 is a partial cross-sectional view schematically showing the configuration of the semiconductor device in the second comparative example. Referring mainly to FIG. 9, the semiconductor device of this comparative example has a dielectric film 61C instead of the dielectric film 61 (FIG. 1). The dielectric film 61C has the same pattern shape as the upper electrode 71. Therefore, a leak current is likely to be generated between the upper electrode 71 and the lower electrode 51 due to the polymer film PM adhering to the side wall of the dielectric film 61C during the etching.

  A problem also arises when the upper electrode, the dielectric film, and the lower electrode are formed with the same width. The etching of the upper electrode and the dielectric film and the etching of the lower electrode need to be separately performed for capacitance formation and wiring formation, and thus are performed separately. Therefore, if the etching width of the upper electrode and dielectric film is the same as the etching width of the lower electrode, the etching width of the upper electrode and dielectric film and the etching width of the lower electrode will shift due to misalignment and other factors. Etching becomes poor, dust is generated, and the yield decreases.

  According to the present embodiment, as shown in FIG. 1, the lower electrode 51 is electrically connected to the lower electrode wiring 41 on the lower surface SB facing the lower electrode wiring 41 of the lower electrode 51. Therefore, unlike the comparative example (FIG. 8), there is no need to establish electrical connection with the lower electrode 51 on the upper surface ST (FIG. 8) facing the dielectric film 61 of the lower electrode 51. It is possible to prevent a leak current flowing along the interface of the dielectric film 61 between the target path and the upper electrode 71.

  In particular, even when the polymer film PM is formed, the via contact 31 (FIG. 1) is different from the via contact 31C (FIG. 8) and is located away from the polymer film PM. Generation of a large leakage current between the electrode 71 and the electrode 71 is prevented.

  Further, since the width of the lower electrode 51 is larger than the width of the upper electrode 71, even if the upper electrode, the dielectric film, and the lower electrode are shifted from each other due to misalignment or the like, etching defects are less likely to occur. Further, it is possible to prevent the yield from being lowered due to generation of dust.

(Embodiment 2)
FIG. 10 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. Referring to FIG. 10, coating film 91 covers dielectric film 61 and upper electrode 71. The material of the coating film 91 is the same as that of the dielectric film 61. The insulating film 81 covers the coating film 91. The insulating film 81 is made of a material different from that of the dielectric film 61. Each of the lower electrode 51 and the upper electrode 71 is electrically connected (not shown) for using the MIM capacitance.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 11 to 16 are partial cross-sectional views schematically showing a method for manufacturing a semiconductor device in the second embodiment of the present invention in the order of steps.

  Referring to FIG. 11, a lower metal layer 50, a dielectric layer 60, and an upper metal layer 70 are sequentially deposited on the semiconductor bottom structure 30.

  Referring mainly to FIGS. 12 and 13, the same steps as in FIGS. 4 and 5 in the first embodiment are performed in FIGS. 12 and 13.

  Referring to FIG. 14, a coating layer 90 made of the same material as that of dielectric layer 60 and covering dielectric layer 60 and upper electrode 71 is deposited. Next, a photoresist is applied, exposed and developed. During this exposure, the dielectric layer 60 and the covering layer 90 function as a BARL.

  Referring to FIG. 15, resist mask pattern MP2 is formed by the above process. At this time, the resist mask pattern MP2 is formed so as to include the upper electrode 71 in plan view. Next, etching is performed using resist mask pattern MP2 as a mask and semiconductor bottom structure portion 30 as an etching stopper. Next, the resist mask pattern MP2 is removed.

  Referring mainly to FIG. 16, coating film 91 and insulating film 92 are formed from coating layer 90 (FIG. 14) by the above process. A dielectric film 61 and an insulating film 62 are formed from the dielectric layer 60 (FIG. 14). Further, the lower electrode 51 and the normal wiring 52 are formed from the lower metal layer 50 (FIG. 14). Next, an insulating film 81 (FIG. 10) is deposited, and further necessary electrical connections are formed using, for example, a damascene method.

Thus, the semiconductor device of the present embodiment is manufactured.
Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  FIG. 17 is a partial cross-sectional view schematically showing the configuration of the semiconductor device in the third comparative example. Referring mainly to FIG. 17, the semiconductor device of this comparative example does not have a coating film 91, unlike the semiconductor device of this embodiment (FIG. 10). As a result, the interface LP1 between the dielectric film 61 and the insulating film 81 extends from the upper electrode 71. Since this interface LP1 is an interface between different materials, a leak current tends to flow. For this reason, a leak current tends to be generated from the upper electrode 71 via the interface LP1.

  According to the present embodiment, the upper electrode 71 (FIG. 10) is provided on the dielectric film 61 made of one material, and is covered with the coating film 91 made of this one material. Therefore, the upper electrode 71 is shielded from the surroundings by this one material. Therefore, current leakage from the upper electrode 71 can be suppressed.

(Embodiment 3)
FIG. 18 is a partial plan view schematically showing the configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 19 is a schematic partial cross-sectional view taken along line XIX-XIX.

  Referring to FIGS. 18 and 19, the semiconductor device of the present embodiment has a guard ring 72, a via contact 34, a wiring 46 and a via contact 35. The guard ring 72 surrounds the upper electrode 71 with the insulating film 81 interposed therebetween. The guard ring 72 is electrically connected to the lower electrode 51 through the via contact 34, the wiring 46 and the via contact 35.

  FIG. 20 is a partial cross-sectional view showing the configuration of the broken line part XX in FIG. 19 in more detail. Referring to FIG. 20, each of upper electrode 71 and guard ring 72 is entirely surrounded by dielectric film 61 and coating film 91. The dielectric film 61 and the coating film 91 are made of the same material. That is, the upper electrode 71 and the guard ring 72 are separated by a structure made of the same material.

  Since the configuration other than the above is substantially the same as the configuration of the second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  FIG. 21 is a partial cross-sectional view schematically showing the configuration of the semiconductor device in the fourth comparative example. Referring to FIG. 21, in the present comparative example, unlike the present embodiment (FIG. 20), coating film 91 is not formed. For this reason, an interface LP2 between different materials is formed between the upper electrode 71 and the guard ring 72, and a leak current is likely to occur between the upper electrode 71 and the guard ring 72 using the interface LP2 as an electrical path. .

  According to the present embodiment, the upper electrode 71 is wrapped with the same material as in the second embodiment (FIG. 10). Therefore, leakage current from the upper electrode 71 can be suppressed. Thereby, for example, leakage current between the upper electrode 71 and the guard ring 72 can be suppressed.

  Similarly to the upper electrode 71, the guard ring 72 is also wrapped with the same material. Therefore, the leakage current between the upper electrode 71 and the guard ring 72 can be suppressed.

  The side surface of the upper electrode 71 is surrounded by the guard ring 72. Thereby, when the upper electrode 71 and the guard ring 72 are patterned in a lump, the upper electrode 71 does not become an isolated pattern, so that the side surface of the upper electrode 71 can be prevented from being processed into a tapered shape. As a result, the shape of the upper electrode 71 is stabilized, so that the MIM capacitance can be stabilized.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a semiconductor device and a manufacturing method thereof.

1 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a fragmentary sectional view which shows schematically the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a fragmentary sectional view which shows roughly the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a fragmentary sectional view which shows roughly the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a fragmentary sectional view which shows schematically the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a fragmentary sectional view showing roughly the composition of the semiconductor device in the 1st comparative example. It is a fragmentary sectional view showing roughly the composition of the semiconductor device in the 2nd comparative example. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows roughly the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the 4th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows roughly the 5th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the 6th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view showing roughly the composition of the semiconductor device in the 3rd comparative example. It is a fragmentary top view which shows roughly the structure of the semiconductor device in Embodiment 3 of this invention. FIG. 19 is a schematic partial cross-sectional view taken along line XIX-XIX in FIG. 18. It is a fragmentary sectional view which shows the structure of the broken line part XX of FIG. 19 in detail. It is a fragmentary sectional view showing roughly the composition of the semiconductor device in the 4th comparative example.

Explanation of symbols

  30 Semiconductor bottom structure part, 31-35 Via contact, 41 Lower electrode wiring, 42 Normal wiring, 43 Shield metal, 44-46 wiring, 50 Lower metal layer, 51 Lower electrode, 52 Normal wiring, 60 Dielectric layer, 61 Dielectric Body film, 62, 80, 81, 92, 101 Insulating film, 70 Upper metal layer, 71 Upper electrode, 31-35 Via contact, 72 Guard ring, 90 Cover layer, 91 Cover film, MP1, MP2 Resist mask pattern.

Claims (14)

A semiconductor substrate;
Wiring provided on the semiconductor substrate;
A lower electrode provided on the wiring;
A dielectric film provided on the lower electrode;
An upper electrode electrically insulated from the lower electrode and provided on a part of the dielectric film;
The lower electrode is a semiconductor device electrically connected to the wiring on a surface of the lower electrode facing the wiring. A semiconductor substrate;
A lower electrode provided on the semiconductor substrate;
A dielectric film made of a first material provided on the lower electrode;
An upper electrode provided on a part of the dielectric film;
Covering the dielectric film and the upper electrode, and a coating film made of a first material;
A semiconductor device comprising an insulating film made of a second material different from the first material, covering the coating film.   The semiconductor device according to claim 2, wherein the first material includes at least one material selected from the group consisting of SiO, SiON, SiN, SiCN, and SiC.   The semiconductor device according to claim 2, wherein the second material includes at least one material selected from the group consisting of SiO, SiOF, SiOC, and MSQ.   The semiconductor device according to claim 2, further comprising a guard ring surrounding the upper electrode.   The semiconductor device according to claim 1, wherein the lower electrode is made of metal.   The semiconductor device according to claim 1, wherein a width of the lower electrode is wider than a width of the upper electrode. Forming a wiring on a semiconductor substrate;
Forming a lower metal layer electrically connected to the wiring on the wiring;
Forming a dielectric layer on the lower metal layer;
Forming an upper metal layer on the dielectric layer;
Etching the upper metal layer with a first mask pattern formed on the upper metal layer to form an upper electrode;
Forming a second mask pattern including the upper electrode in a plan view on the dielectric layer and the upper electrode;
By patterning the dielectric layer and the lower metal layer by etching using the second mask pattern as a mask, a dielectric film and a lower electrode are formed from the dielectric layer and the lower metal layer, respectively. A method for manufacturing a semiconductor device, comprising: a step. Depositing a lower metal layer on a semiconductor substrate;
Depositing a dielectric layer of a first material on the lower metal layer;
Forming an upper metal layer on the dielectric layer;
Etching the upper metal layer with a first mask pattern formed on the upper metal layer to form an upper electrode;
Depositing a cover layer made of the first material and covering the dielectric layer and the upper electrode;
Forming a second mask pattern including the upper electrode in plan view on the covering layer;
By patterning the coating layer, the dielectric layer, and the lower metal layer by etching using the second mask pattern as a mask, each of the coating layer, the dielectric layer, and the lower metal layer is patterned. Forming a coating film, a dielectric film, and a lower electrode;
Depositing an insulating film made of a second material different from the first material on the peritoneum.   The method of manufacturing a semiconductor device according to claim 9, wherein the first material includes at least one material selected from the group consisting of SiO, SiON, SiN, SiCN, and SiC.   The method for manufacturing a semiconductor device according to claim 9, wherein the second material includes at least one material selected from the group consisting of SiO, SiOF, SiOC, and MSQ.   The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the upper electrode includes a step of forming a guard ring surrounding the upper electrode.   The method for manufacturing a semiconductor device according to claim 8, wherein the lower metal layer is made of metal.   The method for manufacturing a semiconductor device according to claim 8, wherein a width of the lower electrode is wider than a width of the upper electrode.

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