JP2004158598A

JP2004158598A - Mim capacitor

Info

Publication number: JP2004158598A
Application number: JP2002322244A
Authority: JP
Inventors: Takuo Hino; 拓生日野; Yoshihisa Minami; 善久南
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2002-11-06
Filing date: 2002-11-06
Publication date: 2004-06-03
Anticipated expiration: 2022-11-06
Also published as: JP4013734B2

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of characteristics degradation in a circuit comprising a conventional MIM capacitor due to a parasitic element between a metal layer and the substrate. <P>SOLUTION: The capacitor having a laminated metal-insulator-metal structure in a semiconductor device has a first insulating layer between a first metal layer and a second metal layer, and has a third metal layer between the substrate and the second metal layer. Further, a second insulating layer is provided between the second metal layer and the third metal layer, and the third metal layer is connected to the ground potential. The capacitance Q is adjusted by reducing the area of the third metal layer inserted between the second metal layer and making the substrate smaller than that of a metal layer constituting the MIM capacitor. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は半導体集積回路において結合回路に使用する容量の構造に関するものである。
【０００２】
【従来の技術】
従来の半導体で構成されているＭＩＭ容量の従来の構造図を図５、図６に示す。
【０００３】
図５において第１の電極１と第２の電極２と絶縁体３を備え、前記第１、第２の電極が前記絶縁体３を挟んだ構成を有しており、半導体基板５上に絶縁体４で分離されて形成されている（例えば特許文献１参照）。
【０００４】
図６においては第１の電極１と第２の電極２と絶縁体３を備え、前記第１、第２の電極により前記絶縁体３を挟んだ構成を有しており、更に第２の電極２と半導体基板５の間には絶縁体４と絶縁体９で分離され、回路接地に接地された第３の電極８を設ける事で、前記第２の電極と半導体基板５の間を電気シールドする構成をしている。
【０００５】
従来構造における図５、図６に示したＭＩＭ容量の等価回路をそれぞれ図９、図１０に示す。
【０００６】
図９において容量Ｃが図５における第１の電極と第２の電極の電極間容量であり、容量Ｃｓと抵抗Ｒｓは第２の電極の半導体基板５に対する寄生素子である。
【０００７】
図１０において容量Ｃが図６における第１の電極と第２の電極の電極間容量であり、容量Ｃ２はシールド電極となる第３の電極と前記第２の電極間の容量であり、容量Ｃｓと抵抗Ｒｓは前記第３の電極の半導体基板５に対する寄生素子であり、抵抗ＲＩは前記第３の電極を回路接地に接続するために使用する配線の配線抵抗である。
【０００８】
【特許文献１】
特開平７−３２６７１２号公報（第１頁、第１図）
【０００９】
【発明が解決しようとする課題】
最近の通信分野ではＧＨｚ帯の高周波で動作する回路の利用が増え、ＭＩＭ容量の高性能化が必要となってきている。例えば入出力回路等の整合回路で使用した場合、寄生素子の抵抗成分による損失が問題となるし、電圧制御発振器等で使用した場合は寄生素子の抵抗成分がＱ値の劣化を招き発振器の性能を悪化させる。また、信号線路等に使用した場合も寄生素子の時定数の変動が伝送信号の遅延量を変動させシステムを不安定にするなどの問題が発生する。
【００１０】
図６のように図５の第２の電極と半導体基板間に接地された第３の電極を付け加える構成により、第２の電極を半導体基板からシールドし第２の電極に付加される寄生容量を損失抵抗が無く、ばらつきの少ない容量に変換することができる。このことにより図１０の容量Ｃの性能を向上させることができるが、図１０の等価回路の容量Ｃ２を接地する配線の抵抗成分ＲＩのために完全な対策とはなりえない。
【００１１】
これらの、寄生素子の影響を取り除くために、本発明はＭＩＭ容量を使用する上で、これらの寄生容量の影響による回路性能の劣化を防ぐための技術を提供するものである。
【００１２】
【課題を解決するための手段】
ＭＩＭ容量を使用する上で、対基板寄生素子による損失等を削減するために、特に差動線路で使用する場合、２対の容量の半導体基板に近い側の電極と半導体基板間に前記２対の両方の容量から、寄生容量で結合状態にあり、更に前記２対の両方の基板側電極からの対基板への大半の電束を阻止できるぐらいの面積を持ち他の回路へは非接触の別の金属電極を設け、この非接触の電極が前記２対の容量に印加される同振幅、逆位相の信号からの、同量、逆位相の電荷の充放電を受けることでＡＣ接地状態になり、このＡＣ接地状態により非接触電極からの対基板寄生素子を無視する事ができ、結果として差動線路に挿入される２対の容量が対基板寄生素子の影響を受けないように構成する。
【００１３】
【発明の実施の形態】
以下、本発明について、図面を参照しながら説明する。
【００１４】
図１に本発明の第１の実施形態を示す。図１において１は第１の容量の第１の電極、２は前記第１の容量の第２の電極、３，４，９は絶縁層、５は半導体基板、６は第２の容量の第１の電極、７は前記第２の容量の第２の電極、８は前記第１、第２の容量の両方の第２の電極面に対して同時に面対向する様に前記第１、第２の容量の両方の第２の電極と前記半導体基板５の間に設けられる第３の電極である。
【００１５】
前記、図１の等価回路を図１１に示す。
【００１６】
図１１において１００は前記第１の容量、１０１は前記第２の容量、１０２は前記第１の容量に寄生素子として付加される前記第１の容量の第２の電極と前記第３の電極間の容量、１０３は前記第２の容量に寄生素子として付加される前記第２の容量の第２の電極と前記第３の電極間の容量、１０５は前記第３の電極と半導体基板間の寄生容量、１０４は前記寄生容量１０５の内部損失抵抗、１０６は前記第３の電極に相当する部分である。
【００１７】
前記、図１に示した構造の本発明第１の実施形態における、容量対を図１２に示すような差動回路に差動信号を入力するための結合容量として使用すると、図１１の前記第１、第２の容量の各第２の電極に相当するポイントｃ点、ｄ点に加わる信号が同振幅、逆位相になり、前記第１、第２の各第２の電極の寄生容量１０２，１０３を通して前記第３の電極１０６に充放電される電荷の和が相殺して零になる。このことにより前記第３の電極１０６の電位はＡＣ接地状態となり、前記図１１における前記第３の電極１０６と半導体基板間に存在する寄生素子１０４，１０５の影響を受けなくなり、半導体基板の影響による損失や容量のＱ値の劣化が無くなり、差動信号としての２つの信号の位相のずれ、振幅の差等の問題が生じなくなり、高精度での高品質な回路設計が可能となる。
【００１８】
図２に本発明の第２の実施形態を示す。
【００１９】
図２において、１は第１の容量の第１の電極、２は第２の容量の第２の電極としても共用される前記第１、第２の容量の共通の第２の電極、３，４は絶縁層、５は半導体基板である。
【００２０】
前記、図２の等価回路を図１３に示す。
【００２１】
図１３において、２０１は第１の容量、２０２は第２の容量、２０３，２０４は前記第１の容量、前記第２の容量の共通の第２の電極と基板間の寄生容量と寄生容量の損失抵抗であり、２０５は前記第１の容量、前記第２の容量の共通の第２の電極に相当する。
【００２２】
前記、図２の構造の本発明第１の実施形態における容量を図１４に示した差動信号間に挿入される容量Ｃのような条件で使用した場合においては、前記、図１３の等価回路図の第２の電極２０５は端子ｅおよびｆから前記第１の容量２０１と第２の容量２０２を通じて充放電される電荷の総和が零になるため、前記第２の電極２０５の電位がＡＣ接地状態となり前記図２の第２の電極２と半導体基板５の間に存在する前記、図１３の等価回路に示される寄生容量２０３と損失抵抗２０４の影響を受けなくなる。
【００２３】
図３に本発明の第３の実施形態を示す。
【００２４】
図３に示した実施形態は前記第１の請求項の実施形態の第３の電極を回路接地に接続するための取り出し配線を設け、前記第３の電極を回路設置に接続したものである。
【００２５】
前記、第１の実施形態において第１の容量、第２の容量に加えられる信号に歪が含まれている場合や振幅が異なる場合、図１１に示す前記第１の実施形態の第３の電極１０６にリップル電圧が発生し、前記図１１における寄生素子１０４，１０５の影響を若干受けるため、前記第３の電極を回路接地に接続して、更に前記第３の電極のシールド効果を強化する構造を有し、前記第３の電極に接続される回路接地に対して、前記第１、第２の容量の各第２の電極から同一インピーダンスになるような構造で前記第３の電極に接地電位を接続することで、前記第１、第２の容量に加えられる２つの信号のバランスを保持する事ができる。
【００２６】
図４に本発明の第４の実施形態を示す。
【００２７】
図４に示した実施形態は前記第２の請求項の実施形態の第２の電極を回路接地に接続するための取り出し配線を設け、前記第２の電極を回路設置に接続したものである。
【００２８】
前記、第２の実施形態において第１の容量、第２の容量に加えられる信号に歪が含まれている場合や振幅が異なる場合、図１４に示す前記第２の実施形態の第２の電極２０５にリップル電圧が発生し、前記図１４における寄生素子２０３，２０４の影響を若干受けるため、前記第２の電極を回路接地に接続する事でこの寄生素子の影響を無くす構造を有し、前記第２の電極に接続される回路接地に対して、前記第１、第２の容量の各第１の電極から同一インピーダンスになるような構造で前記第２の電極に接地電位を接続することで、前記第１、第２の容量に加えられる２つの信号のバランスを保持する事ができる。
【００２９】
また、本発明１〜４の実施形態において、上部電極の上に更に別の電極を設けて、上部方向のシールド効果を得る構造にしてもよい。
【００３０】
また、図２に示した第２の実施形態において、図８に示すように、第１の電極の周辺に第２の電極に接続されたガードを設けてシールド効果を増す構造にしてもよく、同様に第１の実施形態、第３の実施形態、第４の実施形態に対しても同様のガードを設けてもよい。
【００３１】
【発明の効果】
以上のように本発明は、対基板寄生素子の影響を受けないような条件でのＭＩＭ容量を使用することが可能となり、高周波半導体集積回路において、より高い周波数、より精密な設計を可能とし、高周波半導体集積回路の特性を極めて向上させる事を可能とする手段を実現するための技術を提供するものである。
【図面の簡単な説明】
【図１】本発明におけるＭＩＭ容量において第１の実施形態を示す構造図
【図２】本発明におけるＭＩＭ容量において第２の実施形態を示す構造図
【図３】本発明におけるＭＩＭ容量において第３の実施形態を示す構造図
【図４】本発明におけるＭＩＭ容量において第４の実施形態を示す構造図
【図５】従来のＭＩＭ容量の構造図
【図６】従来のシールド方法を示すためのＭＩＭ容量の構造図
【図７】従来のＭＩＭ容量の使用方法を示すための容量構成図
【図８】本発明の実施形態を補足説明するためのＭＩＭ容量の構成図
【図９】従来の構造におけるＭＩＭ容量の等価回路図
【図１０】従来のシールド方法を利用した場合のＭＩＭ容量の等価回路図
【図１１】本発明の第１の実施形態におけるＭＩＭ容量の等価回路図
【図１２】本発明の第１の実施形態の使用例を示す図
【図１３】本発明の第２の実施形態におけるＭＩＭ容量の等価回路図
【図１４】本発明の第２の実施形態の使用例を示す図
【符号の説明】
１，２，６，７，８金属電極
３，４，９絶縁層
５半導体基板
１０コンタクト
１１ガード電極
１００，１０１本発明の第１の実施形態における電極間容量
１０２，１０３本発明の第１の実施形態における寄生容量
１０４，１０５本発明の第１の実施形態における寄生素子
１０６本発明の第１の実施形態における第３の電極
２０１，２０２本発明の第２の実施形態における電極間容量
２０３，２０４本発明の第２の実施形態における寄生素子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a structure of a capacitor used for a coupling circuit in a semiconductor integrated circuit.
[0002]
[Prior art]
FIGS. 5 and 6 show a conventional structure diagram of an MIM capacitor made of a conventional semiconductor.
[0003]
In FIG. 5, a first electrode 1, a second electrode 2, and an insulator 3 are provided, and the first and second electrodes have a configuration in which the insulator 3 is interposed. It is formed separately from the body 4 (for example, see Patent Document 1).
[0004]
In FIG. 6, a first electrode 1, a second electrode 2, and an insulator 3 are provided, and the insulator 3 is sandwiched between the first and second electrodes. By providing a third electrode 8 separated between the semiconductor substrate 5 and the insulator 4 by an insulator 4 and an insulator 9 and grounded to the circuit ground, an electric shield is provided between the second electrode and the semiconductor substrate 5. It is configured to be.
[0005]
FIGS. 9 and 10 show equivalent circuits of the MIM capacitors shown in FIGS. 5 and 6 in the conventional structure, respectively.
[0006]
In FIG. 9, the capacitance C is the capacitance between the first electrode and the second electrode in FIG. 5, and the capacitance Cs and the resistance Rs are parasitic elements of the second electrode with respect to the semiconductor substrate 5.
[0007]
In FIG. 10, the capacitance C is the capacitance between the first electrode and the second electrode in FIG. 6, the capacitance C2 is the capacitance between the third electrode serving as the shield electrode and the second electrode, and the capacitance Cs And a resistor Rs are parasitic elements of the third electrode with respect to the semiconductor substrate 5, and a resistor RI is a wiring resistance of a wiring used to connect the third electrode to circuit ground.
[0008]
[Patent Document 1]
JP-A-7-326712 (page 1, FIG. 1)
[0009]
[Problems to be solved by the invention]
In the recent communication field, the use of circuits operating at a high frequency in the GHz band has increased, and it has become necessary to improve the performance of MIM capacitors. For example, when used in a matching circuit such as an input / output circuit, loss due to the resistance component of the parasitic element becomes a problem. When used in a voltage controlled oscillator, the resistance component of the parasitic element causes deterioration of the Q value, and the performance of the oscillator is deteriorated. Worsen. Also, when used for a signal line or the like, a problem occurs that the fluctuation of the time constant of the parasitic element fluctuates the amount of delay of the transmission signal and makes the system unstable.
[0010]
As shown in FIG. 6, by adding a grounded third electrode between the second electrode and the semiconductor substrate of FIG. 5, the second electrode is shielded from the semiconductor substrate to reduce the parasitic capacitance added to the second electrode. There is no loss resistance and it is possible to convert to a capacitance with little variation. This can improve the performance of the capacitor C of FIG. 10, but cannot be a complete measure due to the resistance component RI of the wiring that grounds the capacitor C2 of the equivalent circuit of FIG.
[0011]
In order to eliminate the influence of the parasitic element, the present invention provides a technique for preventing the deterioration of the circuit performance due to the influence of the parasitic capacitance when using the MIM capacitor.
[0012]
[Means for Solving the Problems]
In order to reduce the loss due to parasitic elements to the substrate when using the MIM capacitor, particularly when used in a differential line, the two pairs of electrodes between the electrode near the semiconductor substrate and the semiconductor substrate have two pairs of capacitors. From the two capacitances, are coupled by parasitic capacitances, and have an area large enough to block most of the electric flux from the two electrodes on the substrate side to the substrate and have no contact with other circuits. Another metal electrode is provided, and the non-contact electrode is charged and discharged with the same amount and opposite phase from the same amplitude and opposite phase signals applied to the two pairs of capacitors, thereby setting the AC ground state. In this AC ground state, parasitic elements to the substrate from the non-contact electrode can be ignored, and as a result, two pairs of capacitors inserted into the differential line are not affected by the parasitic elements to the substrate. .
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings.
[0014]
FIG. 1 shows a first embodiment of the present invention. In FIG. 1, 1 is a first electrode of a first capacitor, 2 is a second electrode of the first capacitor, 3, 4, and 9 are insulating layers, 5 is a semiconductor substrate, and 6 is a second electrode of a second capacitor. One electrode 7 is a second electrode of the second capacitor, and 8 is the first and second electrodes so as to simultaneously face both the second electrode surfaces of the first and second capacitors. Is a third electrode provided between both the second electrodes having the above-mentioned capacitance and the semiconductor substrate 5.
[0015]
FIG. 11 shows the equivalent circuit of FIG.
[0016]
In FIG. 11, 100 is the first capacitor, 101 is the second capacitor, and 102 is a second capacitor between the second electrode and the third electrode of the first capacitor which is added to the first capacitor as a parasitic element. , A capacitance 103 between the second electrode and the third electrode of the second capacitance added to the second capacitance as a parasitic element, and a capacitance 105 between the third electrode and the semiconductor substrate. A capacitance 104 is an internal loss resistance of the parasitic capacitance 105, and 106 is a portion corresponding to the third electrode.
[0017]
When the capacitance pair in the first embodiment of the present invention having the structure shown in FIG. 1 is used as a coupling capacitance for inputting a differential signal to a differential circuit as shown in FIG. The signals applied to the points c and d corresponding to the second electrodes of the first and second capacitors have the same amplitude and opposite phases, and the parasitic capacitances 102 and 102 of the first and second second electrodes respectively. The sum of the charges charged and discharged to the third electrode 106 through 103 cancels to zero. As a result, the potential of the third electrode 106 becomes an AC ground state, and is not affected by the parasitic elements 104 and 105 existing between the third electrode 106 and the semiconductor substrate in FIG. Loss and deterioration of the Q value of the capacitance are eliminated, problems such as a phase shift and a difference in amplitude between two signals as a differential signal do not occur, and a high-precision and high-quality circuit design becomes possible.
[0018]
FIG. 2 shows a second embodiment of the present invention.
[0019]
In FIG. 2, 1 is a first electrode of a first capacitor, 2 is a common second electrode of the first and second capacitors, which is also used as a second electrode of a second capacitor. 4 is an insulating layer and 5 is a semiconductor substrate.
[0020]
FIG. 13 shows the equivalent circuit of FIG.
[0021]
In FIG. 13, reference numeral 201 denotes a first capacitance, 202 denotes a second capacitance, 203 and 204 denote the first capacitance, and the parasitic capacitance between the common second electrode of the second capacitance and the substrate and the parasitic capacitance. A loss resistance 205 corresponds to a common second electrode of the first capacitance and the second capacitance.
[0022]
When the capacitance according to the first embodiment of the present invention having the structure shown in FIG. 2 is used under conditions such as the capacitance C inserted between the differential signals shown in FIG. 14, the equivalent circuit shown in FIG. In the second electrode 205 shown in the figure, the sum of the charges charged and discharged from the terminals e and f through the first capacitor 201 and the second capacitor 202 becomes zero, so that the potential of the second electrode 205 becomes AC ground. In this state, there is no influence of the parasitic capacitance 203 and the loss resistance 204 shown between the second electrode 2 and the semiconductor substrate 5 shown in FIG.
[0023]
FIG. 3 shows a third embodiment of the present invention.
[0024]
In the embodiment shown in FIG. 3, an extraction wiring for connecting the third electrode of the first embodiment to a circuit ground is provided, and the third electrode is connected to a circuit installation.
[0025]
In the case where the signal added to the first capacitance and the second capacitance in the first embodiment includes distortion or has a different amplitude, the third electrode of the first embodiment shown in FIG. Since a ripple voltage is generated at 106 and slightly affected by the parasitic elements 104 and 105 in FIG. 11, the third electrode is connected to circuit ground, and the shield effect of the third electrode is further enhanced. And a ground potential is applied to the third electrode in such a structure that each of the second electrodes of the first and second capacitors has the same impedance with respect to the circuit ground connected to the third electrode. , The balance between the two signals applied to the first and second capacitors can be maintained.
[0026]
FIG. 4 shows a fourth embodiment of the present invention.
[0027]
In the embodiment shown in FIG. 4, a lead-out wire for connecting the second electrode of the second embodiment to circuit ground is provided, and the second electrode is connected to a circuit installation.
[0028]
In the second embodiment, when a signal added to the first capacitor and the second capacitor includes distortion or a different amplitude, the second electrode of the second embodiment shown in FIG. Since a ripple voltage is generated at 205 and slightly affected by the parasitic elements 203 and 204 in FIG. 14, the second electrode is connected to circuit ground to eliminate the effect of the parasitic element. By connecting a ground potential to the second electrode in such a structure that each of the first electrodes of the first and second capacitors has the same impedance with respect to the circuit ground connected to the second electrode. , The balance between the two signals applied to the first and second capacitors can be maintained.
[0029]
Further, in the embodiments of the present invention 1 to 4, another electrode may be provided on the upper electrode to obtain a shield effect in the upper direction.
[0030]
Further, in the second embodiment shown in FIG. 2, as shown in FIG. 8, a structure may be adopted in which a guard connected to the second electrode is provided around the first electrode to increase the shielding effect. Similarly, similar guards may be provided for the first, third, and fourth embodiments.
[0031]
【The invention's effect】
As described above, the present invention makes it possible to use the MIM capacitor under conditions that are not affected by the parasitic element with respect to the substrate, enabling higher frequency and more precise design in a high-frequency semiconductor integrated circuit, It is an object of the present invention to provide a technique for realizing means capable of extremely improving the characteristics of a high-frequency semiconductor integrated circuit.
[Brief description of the drawings]
FIG. 1 is a structural diagram showing a first embodiment of a MIM capacitor according to the present invention; FIG. 2 is a structural diagram showing a second embodiment of a MIM capacitor according to the present invention; FIG. 3 is a third diagram showing a MIM capacitor according to the present invention; FIG. 4 is a structural diagram showing a fourth embodiment of an MIM capacitor according to the present invention; FIG. 5 is a structural diagram of a conventional MIM capacitor; FIG. 6 is an MIM for showing a conventional shielding method; FIG. 7 is a structural diagram of a capacitor. FIG. 8 is a structural diagram of a MIM capacitor for illustrating a method of using a conventional MIM capacitor. FIG. 8 is a structural diagram of a MIM capacitor for supplementary explanation of an embodiment of the present invention. FIG. 10 is an equivalent circuit diagram of the MIM capacitor when a conventional shielding method is used. FIG. 11 is an equivalent circuit diagram of the MIM capacitor according to the first embodiment of the present invention. No. FIG. 13 is a diagram showing an example of use of the second embodiment. FIG. 13 is an equivalent circuit diagram of a MIM capacitor according to the second embodiment of the present invention. FIG. 14 is a diagram showing an example of use of the second embodiment of the present invention. ]
1, 2, 6, 7, 8 Metal electrodes 3, 4, 9 Insulating layer 5 Semiconductor substrate 10 Contact 11 Guard electrode 100, 101 Capacitance between electrodes 102, 103 in the first embodiment of the present invention Parasitic capacitances 104, 105 in the embodiment Parasitic element 106 in the first embodiment of the present invention Third electrodes 201, 202 in the first embodiment of the present invention Inter-electrode capacitance 203, 202 in the second embodiment of the present invention 204 Parasitic Element in Second Embodiment of Present Invention

Claims

A first electrode (upper electrode), a second electrode (lower electrode closer to the substrate), and a first insulating film disposed between the first and second electrodes on a semiconductor substrate. A first capacitor and a second capacitor, and a third floating electrode between the substrate and the second electrode of both the first capacitor and the second capacitor, and the first capacitor and the second capacitor. The third electrode is formed so that the capacitors are arranged close to each other, and the areas of the second electrodes of both the first and second capacitors are almost simultaneously overlapped with the whole area, and are arranged in an electrically floating state. , Two pairs of MIM (Metal-Insulator-Metal) capacitors used as a capacitor between the first and second electrodes of the first capacitor and the second capacitor.

A first electrode (upper electrode) and a second electrode (lower electrode closer to the substrate) are provided on a semiconductor substrate, and a first insulating interlayer film is provided between the first electrode and the second electrode. , And a first capacitor and a second capacitor are provided, and the first capacitor and the second capacitor are arranged close to each other, and both the first and second capacitors have one second electrode. And the second electrode of each of the first and second capacitors is directly connected, and at the same time, the second electrode is configured as an electrically floating electrode. Two pairs of MIM (Metal-Insulator-Metal) capacitors using the first and second two capacitors as a combined capacitor between the first electrodes of the first and second capacitors.

The first and second positions as viewed through the parasitic capacitance between the second electrode and the third electrode from the position with respect to the position on the third electrode which is the electrically floating electrode according to claim 1 of the present invention. 2. The MIM capacitor according to claim 1, wherein the MIM capacitor is connected to circuit ground by using a position on the third electrode as a connection point such that the impedance of each of the second electrodes becomes substantially equal.

In the second aspect of the present invention, with respect to a position on the second electrode which is the electrically floating electrode, the first and second first and second first viewed from the position through the first and second capacitors, respectively. 3. The MIM capacitor according to claim 2, wherein the MIM capacitor is configured to be connected to a circuit ground by using a position on the second electrode such that an impedance to the electrode is substantially equal, as a connection point.