JP2010087303A - Thin film transistor substrate for display and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor substrate for an active matrix type display, which removes troubles which may be caused by connecting a semiconductor film of a source-drain region to a semiconductor film formed under a scanning line. <P>SOLUTION: The thin film transistor substrate 1 for the active matrix type display includes a TFT 20 in which at least a semiconductor film 13, a gate insulating film 14g and a gate electrode 15g are formed successively from the substrate 10 side. The thin film transistor substrate 1 is configured so as to have: conductive patterns 32 obtained by dividing a scanning line 31 including the gate electrode 15g as a part through a predetermined gap G; a semiconductor film 13 formed under the conductive patterns 32; and a wiring film 33 for connecting the divided conductive patterns 32. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor substrate for an active matrix display and a method for manufacturing the same.

  In an active matrix drive display device, a thin film transistor (hereinafter also referred to as TFT) is used as a switching element provided in each pixel, a circuit element constituting a peripheral circuit on a display substrate of the display device, or the like. . Liquid crystal display panels and organic EL display panels, which are display devices driven by an active matrix, are often used for mobile display applications such as mobile phones and PDAs, and TFT substrates having further weight reduction and impact resistance are desired. ing. Particularly in recent years, a TFT substrate using a plastic substrate instead of a glass substrate has been proposed.

  Among such TFT substrates, in a top gate type TFT substrate used for a polysilicon TFT substrate or the like, various so-called “self-alignment processes” using a patterned gate electrode as a mask for ion implantation into a silicon film have been proposed ( For example, see Patent Document 1). In the top gate stagger type TFT substrate, a self-alignment process is also proposed in which a patterned gate electrode is used when a silicon film is etched into a predetermined pattern. As described above, when the self-alignment process is applied to the top gate type TFT substrate and the silicon film pattern is not formed in advance before forming the gate electrode, the gate electrode is used as a mask pattern. Therefore, a silicon film always exists under the gate electrode. The reason for not patterning the silicon film in advance is that (a) the substrate is not heat resistant, so that the thermal activation method of heating the entire substrate cannot be used for activating the ion-implanted impurities. When the laser activation method of irradiating the entire surface with laser light is adopted (in the former case), the laser light damages the substrate in a portion where there is no silicon film, or (b) silicon with a gate electrode pattern A case where the purpose is to omit the photolithography process once by etching the film (in the latter case) can be considered.

  By the way, when a TFT substrate is applied as a switching element of a matrix display, the TFT gate electrode and a scanning line for supplying an external voltage to the gate electrode are usually shared for the purpose of reducing the number of processes. Has been. When the above-described self-alignment process is employed when manufacturing a TFT substrate of such a mode, a silicon film is always formed under the scanning line.

Japanese Patent Laying-Open No. 2004-342753 (paragraph 0025)

  In the above embodiment, when an on-voltage is applied to the scanning line, the silicon film under the scanning line is also in a conductive state, but the silicon film is also connected to the data line and the pixel electrode through the source-drain region. Has been. Therefore, when a current flows between the source and drain by applying an on / off voltage from the scanning line to the gate electrode, the current flows from the silicon film in the source-drain region to the silicon film under the scanning line. Inflow and leakage current may cause problems. In particular, since the scanning line is formed over many pixel areas, there is a possibility that an unnecessary current flows in the adjacent pixel area or a desired voltage is not supplied to the pixel electrode. There is.

  The present invention has been made to solve the above-described problems, and the object thereof is caused by the connection between the semiconductor film in the source-drain region and the semiconductor film under the scanning line. An object of the present invention is to provide an active matrix type thin film transistor substrate for a display which can eliminate problems. Another object of the present invention is to provide a method for manufacturing such a thin film transistor substrate for a display.

  The thin film transistor substrate for display of the present invention for solving the above problems is an active matrix display thin film transistor substrate having thin film transistors provided in this order from the substrate side in the order of a semiconductor film, a gate insulating film, and a gate electrode. A conductive pattern in which a scanning line including the gate electrode as a part thereof is divided at a predetermined gap, and a semiconductor film provided under the conductive pattern are connected to the divided conductive pattern. And a wiring film.

  According to the present invention, the scanning line including the gate electrode as a part thereof is divided by a predetermined gap, the conductive pattern, the semiconductor film provided under the conductive pattern, and the divided conductive pattern. Since the TFT substrate thus configured has a semiconductor film under the conductive pattern, the semiconductor substrate does not exist where there is no conductive pattern. That is, since the semiconductor film under the conductive pattern is divided in the same manner as the conductive pattern at the portion where the conductive pattern is divided, the semiconductor film under the conductive pattern is also divided. As a result, when a current flows between the source and drain by applying an on / off voltage from the scanning line to the gate electrode, the current is below the conductive pattern from the semiconductor film in the source-drain region. Even when the semiconductor film flows into the semiconductor film, an unnecessary current does not flow into the adjacent pixel region as a leakage current or a desired voltage is not supplied to the pixel electrode.

  As a preferable aspect of the thin film transistor substrate for display of the present invention, the substrate is configured to be a non-heat resistant substrate. An example of such a substrate is a plastic substrate.

  In the case of using a non-heat-resistant substrate such as a plastic substrate as the substrate, for example, when obtaining a thin film transistor substrate in a process of performing an activation process after patterning the semiconductor film, the non-heat-resistant substrate in the region where the semiconductor film is removed Therefore, it is desirable to pattern the semiconductor film after the activation process is performed on the solid semiconductor film. Therefore, when a non-heat-resistant substrate is used as the substrate constituting the top gate stagger type TFT substrate as in the present invention, the scanning line including the gate electrode as a part thereof is divided with a predetermined gap. It is particularly preferable to have a conductive pattern, a semiconductor film provided under the conductive pattern, and a wiring film that connects the divided conductive patterns.

  As a preferred embodiment of the thin film transistor substrate for display according to the present invention, the wiring film may be formed directly on the conductive pattern, or the wiring film may be formed on the conductive pattern. Alternatively, the insulating film may be formed through a contact hole.

  According to these inventions, the wiring film for connecting the conductive patterns separated by a predetermined gap may be provided directly on the conductive pattern, or via the contact hole formed in the insulating film on the conductive pattern. In particular, when an insulating film having a contact hole is formed, it is convenient because the insulating film can be shared with an interlayer insulating film formed so as to cover the gate electrode.

  As a preferable aspect of the thin film transistor substrate for display according to the present invention, the semiconductor film is configured such that a region other than a region located under the gate electrode is ion-implanted.

  According to the present invention, since the semiconductor film is ion-implanted by a so-called self-alignment process using the gate electrode as a mask pattern, ion implantation can be performed with high positional accuracy without performing accurate mask alignment.

  As a preferred embodiment of the thin film transistor substrate for display according to the present invention, an interlayer insulating film is formed so as to cover the gate electrode.

  According to the present invention, since the interlayer insulating film is formed so as to cover the gate electrode, the gate electrode can be insulated from the source electrode and the drain electrode, and further, the insulating film for forming the interlayer insulating film on the conductive pattern; It is convenient because it can be common.

  A method of manufacturing a thin film transistor substrate for a display according to the present invention for solving the above-described problem has a thin film transistor provided in the order of at least a semiconductor film, a gate insulating film, and a gate electrode from the substrate side. The scanning line included as a part has a conductive pattern divided by a predetermined gap, a semiconductor film provided under the conductive pattern, and a wiring film connecting the divided conductive pattern This is a method for manufacturing an active matrix thin film transistor substrate for display.

  The manufacturing method according to the first aspect includes a step of forming a semiconductor film on the entire surface of the substrate, a scan including forming a gate insulating film and a gate electrode on the semiconductor film, and including the gate electrode as a part thereof. A step of forming a line with a conductive pattern divided by a predetermined gap, and a region other than a region located under the gate electrode by performing ion implantation on the semiconductor film from above the gate electrode A step of activating the ion-implanted region by irradiating the entire surface with an energy beam, and a semiconductor film other than a portion of the activated region that becomes a source diffusion region and a drain diffusion region Removing a semiconductor film other than the semiconductor film under the conductive pattern, and disposing a predetermined pattern on the conductive pattern separated by the predetermined gap. Film is formed, and having a step of connecting the divided conductive patterns, at that order.

  The manufacturing method according to the second aspect includes a step of forming a semiconductor film on the entire surface of the substrate, a gate insulating film and a gate electrode on the semiconductor film, and the gate electrode as a part thereof. Forming a scanning line including a conductive pattern separated by a predetermined gap, and patterning the gate insulating film and the semiconductor film using the gate electrode forming the conductive pattern as a mask, Forming a wiring film of a predetermined pattern on the conductive pattern divided across the predetermined gap, and connecting the divided conductive pattern in that order.

  According to the invention according to the first and second aspects, the TFT substrate manufactured through the respective steps has a semiconductor film under the conductive pattern, but there is no semiconductor film in the place without the conductive pattern. Does not exist. That is, since the semiconductor film under the conductive pattern is divided in the same manner as the conductive pattern at the portion where the conductive pattern is divided, the semiconductor film under the conductive pattern is also divided. As a result, in the manufactured thin film transistor substrate for display, when a current flows between the source and the drain by applying an on / off voltage from the scanning line to the gate electrode, the current flows in the source-drain region. Even when the semiconductor film flows into the semiconductor film under the conductive pattern, an unnecessary current flows into the adjacent pixel region as a leakage current, or a desired voltage is not supplied to the pixel electrode. There is no problem.

  As a preferable aspect of the method for manufacturing a thin film transistor substrate for display according to the present invention, the substrate is configured to be a non-heat resistant substrate.

  According to the present invention, since the semiconductor film is patterned after the activation process, even if a non-heat resistant substrate is used as the substrate, the activation process greatly increases the non-heat resistant substrate. Does not cause thermal damage.

  As a preferred embodiment of the method for manufacturing a thin film transistor substrate for display according to the present invention, the wiring film may be formed directly on the conductive pattern, or the wiring film may be contacted on the conductive pattern. After forming the insulating film having holes, the insulating film may be formed on the insulating film.

  In these inventions, in particular, if an insulating film having a contact hole is formed on a conductive pattern and then formed on the insulating film, the insulating film is common with the interlayer insulating film formed on the gate electrode. This is convenient for manufacturing.

  As a preferable aspect of the method for manufacturing a thin film transistor substrate for display according to the present invention, the method includes a step of forming an interlayer insulating film so as to cover the gate electrode.

  According to the present invention, since the interlayer insulating film is formed so as to cover the gate electrode, the gate electrode can be insulated from the source electrode and the drain electrode, and the interlayer insulating film is formed in common with the insulating film formed on the conductive pattern. Since it can be used, it is convenient in manufacturing.

  According to the thin film transistor substrate for display of the present invention, the semiconductor film under the conductive pattern is divided in the same manner as the conductive pattern at the portion where the conductive pattern is divided, and the semiconductor film under the conductive pattern Therefore, when a current flows between the source and drain by applying an on / off voltage from the scanning line to the gate electrode, the current flows from the semiconductor film in the source-drain region to the conductive pattern. Even if it flows into the semiconductor film underneath, an unnecessary current may flow into the adjacent pixel region as a leakage current or a desired voltage may not be supplied to the pixel electrode. Absent. As a result, the thin film transistor substrate for display according to the present invention can reduce the occurrence of defects based on the above-mentioned defects.

  According to the method for manufacturing a thin film transistor substrate for a display of the present invention, as described above, an unnecessary current flows into the adjacent pixel region as a leakage current, or a desired voltage is not supplied to the pixel electrode. Since a thin film transistor substrate for display that is not generated can be manufactured, it is possible to reduce the occurrence of defects based on the above-mentioned defects, improve the manufacturing yield, and for example, a liquid crystal display (LCD), an organic light emitting device (OLED), etc. Combined flexible displays can be manufactured with good yield and low cost. Further, in the TFT substrate manufactured by the manufacturing method of the present invention, the semiconductor film is ion-implanted or patterned by a so-called self-alignment process using the gate electrode as a mask pattern, so that accurate mask alignment is not required. Ion implantation or patterning can be performed with high positional accuracy.

  Hereinafter, the thin film transistor substrate for display and the manufacturing method thereof according to the present invention will be described in detail. In addition, this invention is not limited to the form of drawing or the following embodiment.

[Thin film transistor substrate for display]
FIG. 1 is a schematic plan view showing an example of a thin film transistor substrate for display according to the present invention, FIG. 2 is a cross-sectional view taken along line AA ′ of the TFT substrate shown in FIG. 1, and FIG. 3 is a TFT shown in FIG. It is BB 'sectional drawing of a board | substrate. The display thin film transistor substrate 1 (hereinafter, also simply referred to as “TFT substrate 1”) of the present invention includes at least a semiconductor film 13, a gate insulating film 14g, a gate from the substrate 10 side, as shown in FIGS. This is an active matrix TFT substrate having a thin film transistor 20 (hereinafter also simply referred to as “TFT 20”) provided in the order of electrodes 15g. As shown in FIGS. 1 and 3, the present invention includes conductive patterns 32 and 32 in which a scanning line 31 including the gate electrode 15g as a part thereof is divided by a predetermined gap G, and the conductive pattern 32, 32. The semiconductor film 13 provided under the patterns 32 and 32 and the wiring film 33 connecting the divided conductive patterns 32 and 32 are provided.

  More specifically, the present invention is a TFT substrate 1 having a top gate / top contact structure as shown in FIGS. 1 to 3. The TFT 20 formed on the TFT substrate 1 includes a substrate 10 and a substrate 10. The undercoat film 11 provided as necessary, the semiconductor film 13 (source side diffusion film 13s, channel film 13c and drain side diffusion film 13d) provided on the undercoat film 11, and the semiconductor film 13 Specifically, the gate insulating film 14g formed on the channel film 13c, the gate electrode 15g provided on the gate insulating film 14g, and the interlayer provided so as to cover the gate electrode 15g and the gate insulating film 14g The contact film formed by the insulating film 16a and the insulating film 16b covering a part of each of the source side diffusion film 13s and the drain side diffusion film 13d. And Le 17, and a source electrode 15s and the drain electrode 15d that is provided through the contact hole 17, and a protective layer 18 provided so as to cover the TFT20 of further. One end of the drain electrode 15d is provided so as to be connected to the pixel electrode 19 formed in the pixel region (50A, 50B,...). In many cases, the scanning line 31 including the gate electrode 15g as a part thereof is usually divided for each pixel region (50A, 50B,...), But it is not always necessary for each pixel region. In the following, an example in which each pixel region is divided will be described for easy understanding.

  The formation part 30 of the scanning line 31 includes the gate electrode 15g as a part thereof, and is electrically conductive with a predetermined gap G between, for example, each pixel region (50A, 50B,...) Adjacent in the extending direction of the scanning line 30. The pattern 32 is divided. Although the semiconductor film 13 is provided under the conductive pattern 32, the semiconductor film 13 is similarly divided because the conductive pattern 32 is divided. A wiring film 33 is provided on the divided conductive pattern 32 so as to electrically connect the conductive pattern 32. The wiring portion 33 is provided directly or via a contact hole 34 formed in the insulating film 16c.

  In the TFT substrate 1 according to the present invention, although the semiconductor film 13 exists under the conductive pattern 32, the semiconductor film 13 does not exist where the conductive pattern 32 is absent. That is, since the semiconductor film 13 under the conductive pattern 32 is divided in the same manner as the conductive pattern 32 at the portion where the conductive pattern 32 is divided, the semiconductor film 13 under the conductive pattern 32 is divided. Is also divided. As a result, when a current flows between the source and the drain by applying an on / off voltage from the scanning line 31 to the gate electrode 15g, the current flows into the semiconductor film (source side diffusion film 13s in the source-drain region). , The drain side diffusion film 13d) flows into the semiconductor film 13 below the conductive pattern 32, and an unnecessary current flows into the adjacent pixel region as a leakage current, or a desired voltage is applied to the pixel electrode 19. Does not cause problems such as not being supplied.

  Furthermore, in the TFT substrate 1 of the present invention, when a non-heat-resistant substrate such as a plastic substrate is used as the substrate 10, the semiconductor film 13 is patterned and then subjected to an activation process by energy beam irradiation 25 on the entire surface. When the TFT substrate 1 is manufactured, a large thermal damage occurs in the non-heat-resistant substrate in the region where the semiconductor film 13 is removed. Therefore, after the entire surface of the solid semiconductor film 13 is irradiated with the energy beam. It is desirable to manufacture the TFT substrate 1 through the process of patterning the semiconductor film 13 (manufacturing method according to the first aspect of the present invention). Therefore, when a non-heat-resistant substrate is used as the substrate 10 constituting the top gate stagger type TFT substrate 1 as in the present invention, the scanning line 31 including the gate electrode 15g as a part thereof has a predetermined gap G. It is configured to have a conductive pattern 32 separated by a distance, a semiconductor film 13 provided under the conductive pattern 32, and a wiring film 33 connecting the divided conductive pattern 32. Particularly preferred.

  In the present invention, since the interlayer insulating film 16a is formed so as to cover the gate electrode 15g and the gate insulating film 14g, the gate electrode 15g can be insulated from the source electrode 15s and the drain electrode 15d, and the interlayer insulation is further provided. This is convenient because the film 16a can be made common to the insulating film 16c formed on the conductive pattern 32.

[Production method]
The manufacturing method of the TFT substrate of the present invention is a method of manufacturing the TFT substrate 1 of the present invention. The manufacturing method according to the first aspect of the present invention includes a step of forming a semiconductor film 13 (for example, an amorphous silicon film 21a) on the entire surface of the substrate 10, and the semiconductor film 13 (for example, an amorphous silicon film 21a). Forming a gate insulating film 14g and a gate electrode 15g thereon, and forming a scanning line 31 including the gate electrode 15g as a part thereof with a conductive turn 32 separated by a predetermined gap G; An ion implantation process is performed on the semiconductor film 13 from above the electrode 15g, and ion implantation is performed on the semiconductor film 13 in a region other than the region located below the gate electrode 15g. The step of activating the ion-implanted region, and the semiconductor film 1 other than the portion of the activated region that becomes the source-side diffusion film 14s and the drain-side diffusion film 14d And a step of removing the semiconductor film 13 other than the semiconductor film under the conductive pattern 32, and a wiring film 32 having a predetermined pattern is formed on the conductive pattern 32 separated by a predetermined gap G. And connecting the divided conductive patterns 32 in that order.

  Further, in the manufacturing method according to the second aspect of the present invention, the step of forming the semiconductor film 13 on the entire surface of the substrate 10, the formation of the gate insulating film 14g and the gate electrode 15g on the semiconductor film 13, and the gate electrode 15g A scanning line 31 including a part of the gate insulating film 14g as a mask, and a step of forming the scanning line 31 with a conductive pattern 32 separated by a predetermined gap G, and the gate electrode 15g forming the conductive pattern 32 as a mask. A step of patterning the film 13, and a step of forming a wiring film 32 having a predetermined pattern on the conductive pattern 32 separated by a predetermined gap G, and connecting the divided conductive pattern 32. Have in that order.

  These manufacturing methods according to the first and second embodiments are cases where the semiconductor film pattern is not formed in advance before forming the gate electrode, but the TFT substrate 1 manufactured through the respective steps has a conductive pattern. Although the semiconductor film 13 exists under 32, the semiconductor film 13 does not exist where the conductive pattern 32 is absent. That is, since the semiconductor film 13 under the conductive pattern 32 is divided in the same manner as the conductive pattern 32 at the portion where the conductive pattern 32 is divided, the semiconductor film 13 under the conductive pattern 32 is divided. Is also divided. As a result, in the manufactured TFT substrate 1 for display, when a current flows between the source and the drain by applying the on / off voltage from the scanning line 31 to the gate electrode 15g, the current is Even when the semiconductor film 13 in the drain region flows into the semiconductor film 13 below the conductive pattern 32, an unnecessary current flows into the adjacent pixel region as a leakage current, or a desired voltage is supplied to the pixel electrode. There is an advantage that it does not cause problems such as being not performed.

  In particular, according to the manufacturing method according to the first aspect, an ion implantation process is performed on the semiconductor film 13 from above the gate electrode 15g, and ions are implanted into a region other than the region located below the gate electrode 15g; In the TFT substrate 1 manufactured through these steps, the semiconductor film 13 is a so-called self-alignment using the gate electrode 15g as a mask pattern. Ion implantation is performed by the process, and as a result, ion implantation can be performed with high positional accuracy without performing accurate mask alignment. In addition, since the substrate 10 is not heat resistant, the thermal activation method of heating the entire substrate cannot be used to activate the impurities implanted by ion implantation. For this purpose, a laser activation method of irradiating the entire surface with laser light is used. When employed, the laser light does not damage the substrate 10 where there is no semiconductor film 13, so the invention according to the first aspect is preferably applied.

  In addition, according to the manufacturing method according to the second aspect, since the gate insulating film 14g and the semiconductor film 31 are patterned using the gate electrode 15g forming the conductive pattern 32 as a mask, the number of photolithography processes is increased. It can be omitted as compared with the case of one embodiment.

  In the present invention, the semiconductor film 13 under the conductive pattern 32 is divided in the same manner as the conductive pattern 32 by such a manufacturing process.

  Hereinafter, taking the TFT substrate 1 shown in FIGS. 1 to 3 as an example, the structure and manufacturing method of the TFT substrate 1 will be described by the manufacturing method according to the first embodiment shown in FIGS. 4 to 6. In the TFT substrate and the manufacturing method thereof according to the present invention, the planar form is not particularly limited to the illustrated example, and the planar arrangement may be changed within the range having the characteristics of the present invention.

  First, the substrate 10 is prepared. The substrate 10 forms a support substrate for the TFT substrate 1 and may be an organic substrate or an inorganic substrate. Examples of organic substrates include polyethersulfone (PES), polyethylene naphthalate (PEN), polyamide, polybutylene terephthalate, polyethylene terephthalate, polyphenylene sulfide, polyether ether ketone, liquid crystal polymer, fluororesin, polycarbonate, and polynorbornene. An organic substrate made of resin, polysulfone, polyarylate, polyamideimide, polyetherimide, thermoplastic polyimide, or the like, or a composite substrate thereof can be given. Such an organic substrate may be rigid or may be a thin flexible film having a thickness of about 5 μm to 300 μm. Use of a flexible organic substrate (also referred to as a plastic substrate) can be applied to a film display or the like because the TFT substrate 1 can be a flexible substrate.

  Moreover, as an inorganic substrate, a glass substrate, a silicon substrate, a ceramic substrate etc. can be mentioned, for example. The glass substrate may be a glass substrate for liquid crystal displays having a thickness of about 0.05 mm to 3.0 mm.

  As will be described later, the present invention is particularly effective when the substrate 10 is a non-heat resistant substrate that is damaged by the activation process (energy beam irradiation 25) on the semiconductor film 13. As the non-heat-resistant substrate, an organic substrate (plastic substrate or the like) is usually used, but even an inorganic substrate is non-heat-resistant as long as it is damaged by a thermal load such as activation treatment (energy beam irradiation 25). It can be called a substrate.

  Next, as shown in FIG. 4A, an undercoat film 11 is formed on the prepared substrate 10 as necessary. The undercoat film 11 is not an essential film. For example, the undercoat film 11 is (i) an adhesive film for improving the adhesion between the semiconductor film 13 and the substrate 10 or (ii) a stress possessed by a film formed in a subsequent process. As a stress buffer film that relaxes, or (iii) as a barrier film that prevents impurities in the substrate 10 from entering the TFT, or (iv) against heat applied in a later step when a non-heat-resistant substrate is used It can be provided as a thermal buffer film. Therefore, it is not necessary to provide it when the adhesiveness is good, there is no influence of stress, the barrier property need not be considered, or the non-heat resistant substrate is not used.

  For example, when the undercoat film 11 is provided as an adhesion film, the undercoat film 11 needs to be formed at least in a portion where the TFT 20 is formed and a portion where the scanning line 31 is formed, but in other regions. May or may not be formed, and may be formed on the entire surface of the substrate 10. In the example shown in FIG. 4A, the undercoat film 11 is formed on the entire surface.

  The undercoat film 11 is selected from the group of chromium, titanium, aluminum, silicon, chromium oxide, titanium oxide, aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride according to the purposes (i) to (iv) above. Formed of any material. For example, when used as an adhesion film, a metal-based inorganic film made of chromium, titanium, aluminum, silicon, or the like is preferably used. When used as a stress relaxation film or a thermal buffer film, chromium oxide, titanium oxide, oxide A compound film made of aluminum, silicon oxide, silicon nitride, silicon oxynitride, or the like is preferably used. When used as a barrier film, a compound film made of silicon oxide, silicon oxynitride, or the like is preferably used. These films may be provided as a single layer or two or more layers may be laminated depending on the purpose.

  The thickness when the undercoat film 11 is provided as an adhesion film varies slightly depending on the material constituting the film, but it is usually preferably in the range of 1 nm to 200 nm, preferably in the range of 3 nm to 50 nm. More preferably. In addition, when forming the metal type inorganic film which consists of chromium, titanium, aluminum, or silicon as the undercoat film | membrane 11, it is more preferable that it exists in the range of 3 nm or more and 10 nm or less, and chromium oxide, titanium oxide, oxidation In the case where a compound-based inorganic film made of aluminum, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride is formed as the undercoat film 11, it is in the range of 5 nm to 50 nm. It is more preferable. On the other hand, the thickness in the case where the undercoat film 11 is provided as a compound film made of stress, a barrier film, or a thermal buffer film is slightly different depending on the material of the actually formed film, but the thickness is usually 100 nm or more. It is preferably in the range of 1000 nm or less, and more preferably in the range of 100 nm or more and 500 nm or less from the viewpoint of film formation time.

  The undercoat film 11 can be formed by various methods such as a DC sputtering method, an RF magnetron sputtering method, and a plasma CVD method. In practice, a preferred method according to the material constituting the film is employed. Usually, a DC sputtering method, an RF magnetron sputtering method, or the like is preferably used.

  Next, as shown in FIG. 4B, a semiconductor film 13 is formed on the substrate 10 (if an undercoat film 11 is provided). Examples of the semiconductor film 13 include various semiconductor films such as silicon, zinc oxide, and InGaZnO. In the following description, a silicon film will be described as an example of the representative semiconductor film 13. However, since an amorphous silicon film 21a is usually provided, the following description will be given as “amorphous silicon film 21a” unless otherwise specified. explain. In the case where the amorphous silicon film 21a and the polycrystalline silicon film 21p are both specified without being specified, they will be described as “semiconductor film 13”.

The thickness of the amorphous silicon film 21a is not particularly limited, and is usually in the range of 20 nm to 200 nm. The amorphous silicon film 21a can be formed by various methods such as an RF magnetron sputtering method and a CVD method. For example, when the amorphous silicon film 21a is formed by the RF magnetron sputtering method, for example, the film thickness is 50 nm under the film forming conditions of film forming temperature: room temperature, film forming pressure: 0.2 Pa, and gas: argon. The film can be formed. In addition, even when the amorphous silicon film 21a is formed by the CVD method, the film can be formed at a film formation temperature of about 25 ° C. However, since SiH ₄ is used as the source gas, the film is formed at about 450 ° C. after the film formation. Dehydrogenation treatment (about 1 hour in vacuum) is required.

  Next, as shown in FIGS. 4C and 4D, the gate insulating film 14g and the insulating film 14 provided under the conductive pattern 32 are formed on the entire surface of the amorphous silicon film 21a. The insulating film 14 (FIG. 4C) and the metal film 15 (FIG. 4D) for forming the gate electrode 15g and the conductive pattern 32 are formed in this order.

As the insulating film 14, a silicon oxide film is usually used, and the thickness is usually in the range of 15 nm to 300 nm. The insulating film 14 is formed by, for example, RF magnetron sputtering. As a method for forming the insulating film 14, for example, using an RF magnetron sputtering apparatus, an 8-inch SiO ₂ target is charged with power: 1.0 kW (= 3 W / cm ² ), pressure: 1.0 Pa, gas: argon + O ₂ ( A silicon oxide film having a thickness of about 100 nm is formed under the deposition conditions of 50%.

  In addition, as the metal film 15 formed on the insulating film 14, aluminum (Al), copper (Cu), and other conductive materials are usually used, and the thickness is usually in the range of 30 nm to 300 nm. is there. The metal film 15 is formed by a film deposition process such as vacuum deposition or sputtering.

As a sub-step of this step, (1) before forming the insulating film 14 on the entire surface of the amorphous silicon film 21a or (2) after forming the insulating film 14 until the metal film 15 is formed. At any one of the timings, the laser irradiation 22 is performed from above the insulating film 14 to polycrystallize the amorphous silicon film 21a, and a crystallization process for changing to a low resistance polycrystalline silicon film 21p is added. Good. The laser irradiation 22 at this time is a crystallization means for polycrystallizing the amorphous silicon film 21a into the polycrystalline silicon film 21p, and various lasers such as an XeCl excimer laser and a CW (Continuous Wave) laser are used. Can be done. For example, when crystallization is performed using a XeCl excimer laser with a wavelength of 308 nm, as an example, pulse width: 30 nsec (FWHM (full width at half maximum)), energy density: 200 to 300 mJ / cm ² Can be carried out at room temperature. Note that this sub-step may be omitted.

  In the sub-step A of (1) above, the laser irradiation 22 is performed before the insulating film 14 is formed. However, since the amorphous silicon film 21a is formed on the entire surface of the substrate 10, the amorphous silicon film 21a becomes a laser absorption film, and there is an advantage that heat damage based on laser irradiation 22 is not given to the substrate 10. The laser irradiation 22 with the amorphous silicon film 21a formed on the entire surface is particularly preferable when the substrate 10 is a non-heat resistant substrate such as a plastic substrate.

  Further, in the sub-step B of (2) above, as shown in FIG. 4C, laser irradiation 22 is performed after forming the insulating film 14 and before forming the metal film 15. Since the amorphous silicon film 21a and the insulating film 14 are formed on the entire surface, the amorphous silicon film 21a serves as a laser absorption film and does not cause thermal damage to the substrate 10 due to the laser irradiation 22. There is. Such laser irradiation 22 with the amorphous silicon film 21a and the insulating film 14 formed on the entire surface is particularly preferable when the substrate 10 is a non-heat resistant substrate such as a plastic substrate. Further, in this sub-process B, since the insulating film 14 is continuously formed after the amorphous silicon film 21a is formed, the surface of the amorphous silicon film 21a may be exposed to the air atmosphere during laser irradiation. As a result, the generation of oxidation and defects at the interface between the amorphous silicon film 21a and the insulating film 14 can be suppressed, and after the gate insulating film 14g is formed thereafter, the TFT has excellent electrical characteristics. It becomes.

  In the following process, what passed through sub process B which is a crystallization process is explained.

  Next, as shown in FIG. 5E, the scanning line 31 including the gate electrode 15g as a part thereof is formed by the conductive turn 32 divided by a predetermined gap G.

  In this step, first, the insulating film 14 and the metal film 15 are patterned. The patterning is performed by ordinary photolithography using a resist film made of a photosensitive polymer or the like. Specifically, after forming a resist film to be a mask layer on the metal film 15, a mask layer having a predetermined pattern is formed by exposure and development by photolithography using a photomask, and then covered with the mask layer. The unexposed exposed metal film 15 is removed by etching with, for example, a phosphoric acid solution to form the gate electrode 15g and the conductive pattern 32. Subsequently, after the mask layer is removed by etching with, for example, an organic solution, the exposed insulating film 14 is removed with, for example, a hydrofluoric acid solution by a so-called self-alignment process using the gate electrode 15g formed in a predetermined pattern and the conductive pattern 32 as a mask. Then, the gate insulating film 14g is formed by etching and the insulating film 14 provided under the conductive pattern 32 is formed. By such a self-alignment process, there are the gate insulating film 14g and the insulating film 14 patterned in the same shape under the gate electrode 15g and the conductive pattern 32, respectively.

  The pattern of the mask layer formed on the metal film 15 is the same pattern as the plan view pattern (see FIG. 1) of the scanning line 31 including the gate electrode 15g as a part thereof. The scanning line 31 including the gate electrode 15g as a part thereof by photolithography using the pattern as a mask is, for example, divided by a predetermined gap G for each pixel region (50A, 50B,...). A turn 32 can be formed. The scanning line 31 is generally formed continuously so as to cross each pixel region with the same width as that of the gate electrode 15g. However, in the present invention, the conductive pattern 32 is shown in FIG. As shown in FIG. 3, the gap is divided by a predetermined gap G. The length of the gap G is not particularly limited, and can be set, for example, in the range of 0.2 μm to 1000 μm. The shape of the conductive pattern 32 is not particularly limited, and can be, for example, a quadrilateral (see FIG. 1) larger than the line width of the scanning line 31 or a round pattern.

Next, as shown in FIG. 5 (F), when the semiconductor film 13 (amorphous silicon film 21a or the laser shown in FIG. 4 (C) is irradiated from above the gate electrode 15g, polycrystalline silicon is used. An ion implantation process is performed on the film 21p) to perform ion implantation 24 in a region other than the region located under the gate electrode 15g. In the ion implantation 24, for example, phosphorus (P) is implanted at an implantation voltage of 10 keV at room temperature so as to have a dose of 5 × 10 ¹⁴ ions / cm ² to 2 × 10 ¹⁵ ions / cm ² . As the implantation element, in addition to phosphorus, a known element that can be ion-implanted into the semiconductor film, such as boron, antimony, and arsenic, may be arbitrarily selected and implanted.

  In the present invention, the ion implantation 24 is performed as a so-called self-alignment process using the gate electrode 15g as a mask. Therefore, by this step, regions other than the region that is located under the gate electrode 15g and becomes the channel film 13c (the region that becomes the source-side diffusion film 13s and the region that becomes the drain-side diffusion film 13d) are ion-implanted. When the semiconductor film to be ion-implanted is the amorphous silicon film 21a, the amorphous silicon film 21a maintains an amorphous phase as it is even by ion implantation, but the semiconductor film to be ion-implanted is irradiated by laser irradiation. In the case of the polycrystalline silicon film 21p, the polycrystalline silicon film 21p is changed to an amorphous silicon film 21a by ion implantation. In either case, the ion-implanted portion is an amorphous silicon film 21a. Therefore, in this step, ions are implanted into the semiconductor film (channel film 13c) other than the region located under the gate electrode 15g by a so-called self-alignment process using the gate electrode 15g as a mask pattern. Ion implantation can be performed with high positional accuracy without performing proper alignment.

  Next, as shown in FIG. 5G, energy beam irradiation 25 is performed on the entire surface to activate the ion-implanted region. In this step, the ion-implanted region (that is, the region other than the region to be the channel film 13c located under the gate electrode 15g) is activated by the energy beam irradiation 25 to activate the source-side diffusion film 13s. And a region to be the drain side diffusion film 13d are formed. In this activation step, the ion-implanted amorphous silicon film 21a is recrystallized to be changed into the polycrystalline silicon film 21p, and the channel film 13c is formed without being ion-implanted under the gate electrode 15g. The amorphous silicon film 21a is also recrystallized and changed to a polycrystalline silicon film 21p. Here, the energy beam irradiation 25 is a process of recrystallizing by irradiating an energy beam such as a laser, and does not necessarily use a laser.

As the energy beam irradiation 25, various lasers such as a XeCl excimer laser and a CW (Continuous Wave) laser can be used. For example, when crystallization is performed using a XeCl excimer laser having a wavelength of 308 nm, as an example, pulse width: 30 nsec (FWHM (full width at half-maximum)), energy density: 150 to 250 mJ / cm ² Can be carried out at room temperature. At this time, the entire surface of the TFT substrate can be efficiently activated by performing the energy beam irradiation 25 with a linear laser irradiation.

Next, as shown in FIG. 5H, in the activated region, the polycrystalline silicon film 21p other than the portion that becomes the source-side diffusion film 14s and the drain-side diffusion film 14d is removed to form an island. The silicon semiconductor films (13s, 13c, 13d) are formed, and unnecessary polycrystalline silicon film 21p other than the semiconductor film under the conductive pattern 32 is removed. The formation of the polycrystalline silicon semiconductor films (13s, 13c, 13d) by the island formation and the unnecessary removal of the polycrystalline silicon film 21p are performed by etching away by photolithography. Usually, a mask layer is formed only on the remaining portion. After the formation, dry etching is performed. As the etching gas at this time, SF ₆ or the like can be used.

  After the formation of the polycrystalline silicon semiconductor film and the polycrystalline silicon semiconductor film (13s, 13c, 13d) by the island formation and the removal of the unnecessary polycrystalline silicon film 21p, the polycrystalline silicon semiconductor film (13s) is usually used. , 13c, 13d) is subjected to defect processing using oxygen plasma for reducing the defects. For example, the oxygen plasma treatment is performed under conditions of RF 100 W, 1 Torr (133 Pa), and 150 ° C., and thereafter, a drying treatment is performed under the condition of 120 ° C.

  In the present invention, the semiconductor film is patterned to form an island after the energy film irradiation 25 is performed on the entire surface of the semiconductor film. Therefore, even when a non-heat resistant substrate is used as the substrate 10, The non-heat resistant substrate is not greatly damaged by the beam irradiation 25.

  Next, as shown in FIG. 6I, after the insulating film 16 is formed on the entire surface including the gate electrode 15g and the polycrystalline silicon semiconductor films (13s, 13d), the insulating film 16 is patterned to form the gate electrode. An interlayer insulating film 16a is formed so as to cover 15g. Note that the contact hole 17 shown in FIG. 6I may be formed at the same time as the formation of the interlayer insulating film 16a, or after the insulating film is formed in a separate process after the formation of the interlayer insulating film 16a. The insulating film may be formed by selective patterning. Such patterning can be performed, for example, by forming a mask layer such as a resist and then exposing and developing by a resist process using a photomask. The insulating film 16b for forming the contact hole 17 can be patterned by wet etching using, for example, a 2% HF solution, and then the mask layer is removed by resist stripping or plasma ashing. In this step, the gate electrode 15g can be insulated from the source electrode 15s and the drain electrode 15d by the interlayer insulating film 16a.

  Note that the contact hole 34 in the formation portion 30 of the scanning line 31 in FIG. 6I may be formed simultaneously with the interlayer insulating film 16a, or the insulating film 16b for forming the contact hole 17 The insulating film 16c may be formed at the same time, or may be formed by selectively patterning the insulating film 16c after forming the insulating film 16c in a separate process after forming the interlayer insulating film 16a and the insulating film 16b. Also good. Similarly to the above, the insulating film 16c for forming the contact hole 34 can also be patterned by wet etching using, for example, a 2% HF solution, and then the mask layer can be removed by resist stripping or plasma ashing. .

  Next, as shown in FIG. 6 (J), treatment with high-pressure steam 28 is performed to terminate defects and interface defects in the semiconductor film of the polycrystalline silicon semiconductor film 13 (13s, 13c, 13d). For example, dangling bonds on the semiconductor surface are terminated by high-pressure steam treatment at about 0.5 MPa · 150 ° C., and the leakage path at the interface between the polycrystalline silicon semiconductor film 13 (13s, 13c, 13d) and the gate insulating film 14g is eliminated. The method is taken.

  Next, as shown in FIG. 6K, an aluminum (Al) film having a thickness of, for example, 50 nm or more is deposited on the entire surface, and then patterned by wet etching to form the source electrode 15s and the drain electrode 15d. In addition to aluminum, the electrode material may be copper (Cu), other conductive materials, or may be formed by other film forming processes such as sputtering. At this time, the drain electrode 15d is formed so as to be connected to the pixel electrode 19 as shown in FIGS.

  In this step, simultaneously, a wiring film 33 having a predetermined pattern can be formed on the conductive pattern 32 separated by a predetermined gap G, and the divided conductive pattern 32 can be connected. . That is, the wiring film 33 may be formed directly on the conductive pattern 32 at the same time as the source electrode 15s and the drain electrode 15d are formed in this step. In the case where the insulating film 16 c having the contact hole 34 is formed on the conductive pattern 32, the wiring film 33 may be formed through the contact hole 34. The wiring film 33 formed in this way connects the conductive patterns 32 separated by a predetermined gap G.

  Note that the pixel electrode 19 may be formed in any of the steps shown in FIGS. 4 to 6, but as an example, the source electrode 15s and the drain electrode 15d are formed in the step shown in FIG. You may form before forming, and may form before forming the protective layer 18 in the process shown in FIG.6 (L) mentioned later. Examples of the material for forming the pixel electrode 19 include ITO, IZO, and the like. Examples of the formation method include RF magnetron sputtering.

  Next, as shown in FIG. 6L, a protective film 18 that covers the TFT 20 and the formation portion 30 of the scanning line 31 is formed. A preferable example of the protective film 18 is a silicon oxide film. The protective film 18 is preferably formed with a thickness of about 20 nm by, for example, RF magnetron sputtering. Note that the protective film 19 is not formed on the pixel electrode 19. Thus, the TFT substrate 1 according to the embodiment shown in FIGS. 2 and 3 is manufactured.

  The process illustrated in FIGS. 4 to 6 is a manufacturing example to which the manufacturing method according to the first embodiment of the TFT substrate 1 shown in FIGS. 1 to 3 is applied, but the TFT substrate 1 of the present invention is an example of the illustrated process. It is not limited to, It can manufacture in a various deformation | transformation aspect, The manufacturing method which concerns on a 2nd aspect can also be applied.

  Here, the manufacturing method according to the second aspect of the present invention will be described only with respect to differences from the manufacturing method according to the first aspect described above. In the manufacturing method according to the second aspect, as described above, the step of forming the semiconductor film 13 on the entire surface of the substrate 10, the gate insulating film 14 g and the gate electrode 15 g on the semiconductor film 13, and the gate electrode 15 g A scanning line 31 including a part of the gate insulating film 14g as a mask, and a step of forming the scanning line 31 with a conductive pattern 32 separated by a predetermined gap G, and the gate electrode 15g forming the conductive pattern 32 as a mask. A step of patterning the film 13, and a step of forming a wiring film 32 having a predetermined pattern on the conductive pattern 32 separated by a predetermined gap G, and connecting the divided conductive pattern 32. Have in that order.

  The manufacturing method according to the second aspect is the same as the manufacturing method according to the first aspect described above, after the step of FIG. 4D (that is, after forming the metal film 15), the metal film 15 is obtained by photolithography. Through the process of forming the scanning line 31 including the gate electrode 15g as a part thereof with the conductive pattern 32 separated by a predetermined gap G, the gate electrode 15g forming the conductive pattern 32 is then used as a mask. The insulating film 14g is patterned, and the semiconductor film 13 is also patterned to obtain the form shown in FIG. The patterning itself here is a method often used as self-alignment using the gate electrode 15g.

  That is, it differs from the manufacturing method according to the first embodiment in that it does not go through the ion implantation step (FIG. 5 (F)) and the activation step (FIG. 5 (G)), but the step shown in FIG. 5 (H). It will take on the same form again. According to the manufacturing method according to the second aspect, since the gate insulating film 14g and the semiconductor film 31 are patterned using the gate electrode 15g forming the conductive pattern 32 as a mask, the number of photolithography processes is set to the first number. It can be omitted as compared with the case of the embodiment.

  As described above, in the TFT substrate 1 manufactured by the TFT substrate manufacturing method of the present invention, the semiconductor film 13 exists under the conductive pattern 32, but there is no semiconductor film where there is no conductive pattern. do not do. That is, since the semiconductor film 13 under the conductive pattern 32 is divided in the same manner as the conductive pattern at the portion where the conductive pattern is divided, the semiconductor film 13 under the conductive pattern 32 is also divided. Has been. As a result, in the manufactured TFT substrate 1 for display, when a current flows between the source and the drain by applying the on / off voltage from the scanning line 31 to the gate electrode 15g, the current is Even when the semiconductor film 13 under the conductive pattern 32 flows from the semiconductor films 13 s and 13 d in the drain region, an unnecessary current flows into the adjacent pixel area as a leakage current, or a desired current flows into the pixel electrode 19. It does not cause problems such as voltage not being supplied.

  Specifically, a polyether sulfone (PES) having a thickness of 0.2 mm and a thickness of 100 mm × 100 mm is used as the substrate 10, and a chromium film is formed on the substrate 10 as an undercoat film 11 by a DC sputtering method (deposition pressure 0 After forming a thickness of 8 nm by 3 Pa (argon), input power 0.5 kW, film formation time 20 seconds, an amorphous silicon film 21a is formed by RF magnetron sputtering (film formation temperature: room temperature, film formation pressure: 0. 2 Pa (argon)) was formed to a thickness of 50 nm. Thereafter, the TFT substrate 1 was produced based on the specific conditions exemplified in the description column of the steps of FIGS.

In this manufacturing process, (1) crystallization by laser irradiation 22 is performed using a XeCl excimer laser with a wavelength of 308 nm, pulse width: 30 nsec, energy density: 200 to 300 mJ / cm ² , and room temperature conditions. (2) Recrystallization by energy beam irradiation 25 was performed using a XeCl excimer laser with a wavelength of 308 nm under conditions of pulse width: 30 nsec, energy density: 150 to 250 mJ / cm ² , and room temperature. The obtained TFT substrate 1 had no thermal damage such as bending on the PES substrate even by such heat application.

  Further, even when an on / off voltage is applied to the gate electrode 15g from the scanning line of the obtained TFT substrate 1 and a current flows between the source and the drain, an unnecessary current is generated in the adjacent pixel region as a leakage current. Does not flow in, or a desired voltage is not supplied to the pixel electrode 19.

It is a schematic plan view which shows an example of the thin-film transistor substrate for a display of this invention. It is A-A 'sectional drawing of the thin-film transistor substrate shown in FIG. FIG. 2 is a B-B ′ sectional view of the thin film transistor substrate shown in FIG. 1. It is explanatory drawing which shows a part of manufacturing process of the thin-film transistor substrate of this invention. FIG. 5 is an explanatory diagram showing a manufacturing process continued from FIG. 4. FIG. 6 is an explanatory diagram showing a manufacturing process continued from FIG. 5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 TFT substrate 10 Substrate 11 Undercoat film 13 Semiconductor film 13s Source side diffusion film 13c Channel film 13d Drain side diffusion film 14 Insulating film 14g Gate insulating film 15 Metal film 15s Source electrode 15g Gate electrode 15d Drain electrode 16a Interlayer insulating film 16b, 16c Insulating film 17 Contact hole 18 Protective film 19 Pixel electrode 20 TFT
21a Amorphous silicon film 21p Polycrystalline silicon film 22 Laser irradiation 24 Ion implantation 25 Energy beam irradiation 28 High-pressure steam 30 Scan line portion 31 Scan line 32 Conductive pattern 33 Wiring film 34 Contact hole 50A, 50B Pixel region G Gap

Claims (12)

From the substrate side, at least in the thin film transistor substrate for an active matrix type display having a thin film transistor provided in the order of a semiconductor film, a gate insulating film, and a gate electrode,
A conductive pattern in which a scanning line including the gate electrode as a part thereof is divided at a predetermined gap, and a semiconductor film provided under the conductive pattern are connected to the divided conductive pattern. A thin film transistor substrate for display, comprising a wiring film.   The thin film transistor substrate for display according to claim 1, wherein the substrate is a non-heat resistant substrate.   The display thin film transistor substrate according to claim 1, wherein the wiring film is directly formed on the conductive pattern.   The thin film transistor substrate for display according to claim 1, wherein the wiring film is connected through a contact hole of an insulating film formed on the conductive pattern.   5. The display thin film transistor substrate according to claim 1, wherein a region other than a region located under the gate electrode is ion-implanted in the semiconductor film.   The thin film transistor substrate for display according to claim 1, wherein an interlayer insulating film is formed so as to cover the gate electrode. A conductive film having a thin film transistor provided in order of a semiconductor film, a gate insulating film, and a gate electrode from the substrate side, and a scanning line including the gate electrode as a part thereof is separated by a predetermined gap. A manufacturing method of an active matrix type thin film transistor substrate for a display, comprising: a pattern; a semiconductor film provided under the conductive pattern; and a wiring film connecting the divided conductive patterns.
Forming a semiconductor film on the entire surface of the substrate;
Forming a gate insulating film and a gate electrode on the semiconductor film, and forming a scanning line including the gate electrode as a part thereof in a conductive pattern separated by a predetermined gap;
Performing an ion implantation process on the semiconductor film from above the gate electrode, and implanting ions into a region other than a region located under the gate electrode;
Irradiating the entire surface with an energy beam to activate the ion-implanted region;
Removing the semiconductor film other than the portion that becomes the source diffusion region and the drain diffusion region in the activated region, and the semiconductor film other than the semiconductor film under the conductive pattern;
Forming a wiring film of a predetermined pattern on the conductive pattern divided across the predetermined gap, and connecting the divided conductive pattern;
In that order. A method of manufacturing a thin film transistor substrate for a display. A conductive film having a thin film transistor provided in order of a semiconductor film, a gate insulating film, and a gate electrode from the substrate side, and a scanning line including the gate electrode as a part thereof is separated by a predetermined gap. A manufacturing method of an active matrix type thin film transistor substrate for a display, comprising: a pattern; a semiconductor film provided under the conductive pattern; and a wiring film connecting the divided conductive patterns.
Forming a semiconductor film on the entire surface of the substrate;
Forming a gate insulating film and a gate electrode on the semiconductor film, and forming a scanning line including the gate electrode as a part thereof in a conductive pattern separated by a predetermined gap;
Patterning the gate insulating film and the semiconductor film using the gate electrode forming the conductive pattern as a mask;
Forming a wiring film of a predetermined pattern on the conductive pattern divided across the predetermined gap, and connecting the divided conductive pattern;
In that order. A method of manufacturing a thin film transistor substrate for a display.   The method for manufacturing a thin film transistor substrate for a display according to claim 7 or 8, wherein the substrate is a non-heat resistant substrate.   The method for manufacturing a thin film transistor substrate for a display according to claim 7, wherein the wiring film is directly formed on the conductive pattern.   10. The method of manufacturing a thin film transistor substrate for display according to claim 7, wherein the wiring film is formed on the insulating film after an insulating film having a contact hole is formed on the conductive pattern. 11.   The method for manufacturing a thin film transistor substrate for a display according to claim 7, further comprising a step of forming an interlayer insulating film so as to cover the gate electrode.

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