US20150162364A1 - Method of forming semiconductor device - Google Patents

Method of forming semiconductor device Download PDF

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Publication number
US20150162364A1
US20150162364A1 US14/614,414 US201514614414A US2015162364A1 US 20150162364 A1 US20150162364 A1 US 20150162364A1 US 201514614414 A US201514614414 A US 201514614414A US 2015162364 A1 US2015162364 A1 US 2015162364A1
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layer
forming
region
doped
doped layers
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Shou-Peng Weng
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AU Optronics Corp
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AU Optronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a semiconductor device and method of making the same, and more particularly, to a method of forming semiconductor device that uses a non-implant process to form a semiconductor device with low resistant doped layers.
  • polycrystalline silicon thin film transistor device Compared with amorphous silicon thin film transistor device, polycrystalline silicon thin film transistor device exhibits superior electrical property due to its high electrical mobility.
  • LTPS low temp polycrystalline silicon
  • some major issue e.g. poor uniformity of large-size film
  • the conventional LTPS process normally uses an ion implant process to form doped layers for reducing the contact resistance in the thin film transistor device.
  • To introduce the ion implant apparatus into large-size display panel fabrication would result in many technique problems and high cost. Therefore, to seek an alternative method for forming low resistant doped layers has become one of the developing goals.
  • LTPS thin film transistor device may be N type thin film transistor device or P type thin film transistor device when different conductive types of doped layers are used.
  • N type thin film transistor device and P type thin film transistor device are required, a patterned N type doped semiconductor layer and a patterned P type doped semiconductor layer are formed respectively on the same substrate, which would cause damages to the polycrystalline layer.
  • the N type doped semiconductor layer is formed subsequent to the P type doped semiconductor layer, the polycrystalline silicon layer of the N type thin film transistor device will be damaged twice by two etching processes. Accordingly, the device characteristic of the N type thin film transistor device will be deteriorated.
  • a method of forming semiconductor device includes the following steps.
  • a substrate having a first region and a second region is provided.
  • a semiconductor layer is formed on the substrate.
  • a doped layer is formed on the semiconductor layer, and the doped layer is patterned to form two first doped layers in the first region.
  • a patterned dielectric layer is formed on the substrate, wherein the patterned dielectric layer includes a first dielectric layer disposed on the semiconductor layer of the first region and the first doped layers, and an etching stop layer disposed on the semiconductor layer of the second region.
  • Another doped layer is formed on the semiconductor layer and the patterned dielectric layer.
  • the another doped layer is patterned to form two second doped layers in the second region, and the semiconductor layer is patterned to form a first semiconductor layer in the first region and a second semiconductor layer in the second region.
  • a gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the second doped layers, the first dielectric layer and the etching stop layer.
  • a first patterned conductive layer is formed on the gate insulating layer, wherein the first patterned conductive layer includes a first gate electrode disposed on the gate insulating layer of the first region, and a second gate electrode disposed on the gate insulating layer of the second region.
  • a first source electrode and a first drain electrode electrically connected to the first doped layers respectively are formed in the first region, and a second source electrode and a second drain electrode electrically connected to the second doped layers respectively are formed in the second region.
  • the method of forming semiconductor device of the present invention uses a first dielectric layer to protect the semiconductor layer of the first region from being damaged, and uses an etching stop layer to protect the semiconductor layer of the second region from being damaged when patterning the second doped layers.
  • the first dielectric layer and the etching stop layer are defined by the same patterned dielectric layer, and therefore no extra process is required. In addition, fabrication cost can be reduced, and yield can be improved.
  • FIGS. 1-8 are schematic diagrams illustrating a method of forming semiconductor device according to a first preferred embodiment of the present invention.
  • FIG. 9 is a schematic diagram illustrating a method of forming semiconductor device according to a second preferred embodiment of the present invention.
  • FIGS. 10-11 are schematic diagrams illustrating a method of forming semiconductor device according to a third preferred embodiment of the present invention.
  • FIGS. 1-8 are schematic diagrams illustrating a method of forming semiconductor device according to a first preferred embodiment of the present invention.
  • a substrate 10 is provided.
  • the substrate 10 may be a glass substrate, a plastic substrate or a quartz substrate, but not limited thereto.
  • the substrate 10 has a first region 101 and a second region 102 .
  • a semiconductor layer 12 is formed on the substrate 10 .
  • a doped layer 16 is formed on the semiconductor layer 12 .
  • the semiconductor layer 12 maybe an amorphous silicon layer, and an annealing process 14 may be carried out to convert the amorphous silicon layer into a polycrystalline silicon layer.
  • the annealing process may be a laser annealing process, but not limited thereto.
  • the annealing process 14 may also be a thermal process.
  • the doped layer 16 is a P type doped semiconductor layer, but not limited thereto.
  • the doped layer 16 can be formed by performing a non-implant process e.g. a chemical vapor deposition process, a physical vapor deposition process, a spin-on coating process, etc., along with introducing P type doped semiconductor material e.g. boron or boron compound during the non-implant process, but not limited thereto.
  • an annealing process 14 e.g.
  • a laser annealing process can be performed to reduce the resistance of the doped layer 16 .
  • the annealing process 14 for converting the amorphous silicon layer into a polycrystalline silicon layer and the annealing process 14 for reducing the resistance of the doped layer 16 can be integrated. In other words, after the doped layer 16 is formed, one annealing process 14 can be performed to convert the amorphous silicon layer into a polycrystalline silicon layer, as well as reduce the resistance of the doped layer 16 .
  • the material of the semiconductor layer 12 is not limited to amorphous silicon, and may be other semiconductor material.
  • the doped layer 16 is then patterned, for example by performing a lithography and etching process to form two first doped layers 161 in the first region 101 .
  • the first doped layers 161 are P type doped semiconductor layers.
  • a patterned dielectric layer 18 is formed on the substrate 10 and the first doped layers 161 .
  • the patterned dielectric layer 18 includes a first dielectric layer 181 disposed on the semiconductor layer 12 and the first doped layers 161 in the first region 101 , and an etching stop layer 182 disposed on the semiconductor layer 12 in the second region 102 .
  • the first dielectric layer 181 and a first gate insulating layer (not shown) to be formed subsequently are used as a gate insulating layer for protecting the semiconductor layer 12 in the first region 101 from being damaged in the successive process.
  • the etching stop layer 182 is used as an etching stop layer for protecting the semiconductor layer 12 in the second region 102 from being damaged when patterning second doped layers in the successive process.
  • the first dielectric layer 181 and the etching stop layer 182 are made of the same patterned dielectric layer 18 , and thus no extra process is required.
  • the material of the patterned dielectric layer 18 maybe various types of dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto.
  • the patterned dielectric layer 18 may be a single-layered dielectric structure or a composite-layered dielectric structure.
  • the doped layer 20 is an N type doped semiconductor layer, but not limited thereto.
  • the doped layer 20 can be formed by performing a non-implant process e.g. a chemical vapor deposition process, a physical vapor deposition process, a spin-on coating process, etc., along with introducing N type doped semiconductor material e.g. phosphorus or phosphorus compound during the non-implant process, but not limited thereto.
  • an annealing process 14 e.g. a laser annealing process can be performed to reduce the resistance of the doped layer 20 .
  • the annealing process 14 for converting the amorphous silicon layer into a polycrystalline silicon layer and the annealing process 14 for reducing the resistance of the doped layer 16 can be integrated with the annealing process 14 for reducing the resistance of the doped layer 20 .
  • one annealing process 14 can be performed to convert the amorphous silicon layer into a polycrystalline silicon layer, as well as reduce the resistance of the doped layer 16 and the doped layer 20 . As shown in FIG.
  • a lithography and etching process for example, is performed to form a photo resist pattern (not shown) on the doped layer 20 , and the doped layer 20 is etched to form two second doped layers 201 in the second region 102 .
  • the etching stop layer 182 is disposed between the second doped layers 201 , and the second doped layers 201 may partially cover the etching stop layer 182 , but not limited.
  • the second doped layers 201 may be disposed on two opposite sides of the etching stop layer 182 without covering the etching stop layer 182 .
  • the second doped layers 201 are N type doped semiconductor layers.
  • the etching stop layer 182 are disposed on the semiconductor layer 12 in the second region 102 , and thus the semiconductor layer 12 in the second region 102 would not be damaged when patterning the doped layer 20 . Subsequently, the photo resist pattern is removed.
  • the second doped layers 201 , the etching stop layer 182 and the first dielectric layer 181 are used as an etching mask to pattern the semiconductor layer 12 , thereby forming a first semiconductor layer 121 in the first region 101 , and a second semiconductor layer 122 in the second region 102 .
  • the method of patterning the semiconductor layer 12 is not limited by the aforementioned method.
  • the photo resist pattern for defining the doped layer 20 may be reserved until the semiconductor layer 12 is patterned, such that the second doped layers 201 can be protected from being damaged when etching the semiconductor layer 12 . As shown in FIG.
  • a gate insulating layer 22 is formed on the substrate 10 to cover the second doped layers 201 , the first dielectric layer 181 and the etching stop layer 182 .
  • the material of the gate insulating layer 22 maybe various types of dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto.
  • the gate insulating layer 22 may be a single-layered dielectric structure or a composite-layered dielectric structure.
  • a first patterned conductive layer 24 is formed on the gate insulating layer 22 .
  • the first patterned conductive layer 24 includes a first gate electrode 241 disposed on the gate insulating layer 22 in the first region 101 , and a second gate electrode 242 disposed on the gate insulating layer 22 in the second region 102 .
  • the material of the first patterned conductive layer 24 maybe metal or other conductive materials.
  • inter-layered dielectric (ILD) 26 is formed on the gate insulating layer 22 , the first gate electrode 241 and the second gate electrode 242 .
  • the material of the ILD 26 may be various types of dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto.
  • a plurality of first contact holes 281 are formed in the ILD 26 , the gate insulating layer 22 and the first dielectric layer 181 in the first region 101 to partially expose each of the first doped layers 161 respectively, and a plurality of second contact holes 282 are formed in the ILD 26 and the gate insulating layer 22 in the second region 102 to partially expose each of the second doped layers 201 respectively.
  • the second patterned conductive layer 30 includes a first source electrode 301 S and a first drain electrode 301 D disposed on the ILD 26 in the first region 101 and electrically connected to each of the first doped layers 161 respectively, and a second source electrode 302 S and a second drain electrode 302 D disposed on the ILD 26 in the second region 102 and electrically connected to each of the second doped layers 201 respectively.
  • the material of the first source electrode 301 S, the first drain electrode 301 D, the second source electrode 302 S and the second drain electrode 302 D may be metal or other conductive materials.
  • the first semiconductor layer 121 , the first doped layers 161 , the first dielectric layer 181 , the gate insulating layer 22 , the first gate electrode 241 , the ILD 26 , the first source electrode 301 S and the first drain electrode 301 D form a first thin film transistor device 401 .
  • the second semiconductor layer 122 , the etching stop layer 182 , the second doped layers 201 , the gate insulating layer 22 , the second gate electrode 242 , the ILD 26 , the second source electrode 302 S and the second drain electrode 302 D form a second thin film transistor device 402 .
  • the semiconductor device and method of making the same are not limited by the aforementioned embodiment, and may have other different preferred embodiments.
  • the identical components in each of the following embodiments are marked with identical symbols.
  • the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
  • FIG. 9 is a schematic diagram illustrating a method of forming semiconductor device according to a second preferred embodiment of the present invention.
  • the first gate electrode 241 of the first thin film transistor device 501 is electrically connected to the second gate electrode 242 of the second thin film transistor device 502 , and the first source electrode 301 S and the second drain electrode 302 D are electrically connected.
  • the semiconductor device 50 of this embodiment may be a CMOS device, but not limited thereto.
  • the first gate electrode 241 and the second gate electrode 242 may be electrically connected directly, or with another bridging structure.
  • the first source electrode 301 S and the second drain electrode 302 D may be electrically connected directly, or with another bridging structure.
  • the semiconductor device 50 may be applied in the peripheral circuit of electroluminescent display panel, but not limited thereto.
  • FIGS. 10-11 are schematic diagrams illustrating a method of forming semiconductor device according to a third preferred embodiment of the present invention.
  • the first gate electrode 241 is electrically connected to the second drain electrode 302 D.
  • the second drain electrode 302 D is electrically connected to the first gate electrode 241 through the contact hole 261 of the ILD 26 .
  • a first passivation layer 61 is formed on the ILD 26 , the first source electrode 301 S, the first drain electrode 301 D, the second source electrode 302 S and the second drain electrode 302 D.
  • the first passivation layer 61 at least partially exposes the first drain electrode 301 D.
  • a first electrode 62 is formed on the first passivation layer 61 to electrically connect with the exposed first drain electrode 301 D.
  • a second passivation layer 63 is formed on the first passivation layer 61 and the first electrode 62 .
  • the second passivation layer 63 at least partially exposes the first electrode 62 .
  • a light-emitting layer 64 and a second electrode 65 are then formed on the first electrode 62 exposed by the second passivation layer 63 to accomplish a semiconductor device 70 of this embodiment.
  • the semiconductor device 70 may be applied in the pixel structure of electroluminescent display panel.
  • the first thin film transistor device 701 may serve as a driving thin film transistor device
  • the second thin film transistor device 702 may serve as a switching thin film transistor device
  • the first electrode 62 , the light-emitting layer 64 and the second electrode 65 form a light-emitting device 72 , but not limited thereto.
  • the first electrode 62 is an anode
  • the second electrode is a cathode, but not limited thereto.
  • the method of forming semiconductor device of the present invention uses a non-implant process to form the doped layers, which is applicable in large-size display panel fabrication.
  • the resistance of the doped layers is reduced by an annealing process, and thus the electrical characteristic of the semiconductor device is improved.
  • the first dielectric layer of the semiconductor device is able to protect the semiconductor layer in the first region from being damaged, and the etching stop layer is able to protect the semiconductor layer from being damaged when defining the second doped layer.
  • the first dielectric layer and the etching stop layer are defined by the same patterned dielectric layer. Accordingly, no extra process is required, fabrication cost is reduced, and yield is improved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of application Ser. No. 13/447,295 filed Apr. 16, 2012, now allowed, which is incorporated by reference herein in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device and method of making the same, and more particularly, to a method of forming semiconductor device that uses a non-implant process to form a semiconductor device with low resistant doped layers.
  • 2. Description of the Prior Art
  • Compared with amorphous silicon thin film transistor device, polycrystalline silicon thin film transistor device exhibits superior electrical property due to its high electrical mobility. As low temp polycrystalline silicon (LTPS) process advances, some major issue, e.g. poor uniformity of large-size film, has been improved. Thus, LTPS process has been expected to be applied in large-size display panel fabrication. The conventional LTPS process, nevertheless, normally uses an ion implant process to form doped layers for reducing the contact resistance in the thin film transistor device. To introduce the ion implant apparatus into large-size display panel fabrication would result in many technique problems and high cost. Therefore, to seek an alternative method for forming low resistant doped layers has become one of the developing goals.
  • In addition, LTPS thin film transistor device may be N type thin film transistor device or P type thin film transistor device when different conductive types of doped layers are used. In the conventional LTPS process, when both N type thin film transistor device and P type thin film transistor device are required, a patterned N type doped semiconductor layer and a patterned P type doped semiconductor layer are formed respectively on the same substrate, which would cause damages to the polycrystalline layer. For example, if the N type doped semiconductor layer is formed subsequent to the P type doped semiconductor layer, the polycrystalline silicon layer of the N type thin film transistor device will be damaged twice by two etching processes. Accordingly, the device characteristic of the N type thin film transistor device will be deteriorated.
    • SUMMARY OF THE INVENTION
  • It is therefore one of the objectives of the present invention to provide a semiconductor device and method of making the same to avoid damage of the semiconductor layer, and to improve the electrical performance and yield of the semiconductor device.
  • According to a preferred embodiment of the present invention, a method of forming semiconductor device is provided. The method of forming semiconductor device includes the following steps. A substrate having a first region and a second region is provided. A semiconductor layer is formed on the substrate. A doped layer is formed on the semiconductor layer, and the doped layer is patterned to form two first doped layers in the first region. A patterned dielectric layer is formed on the substrate, wherein the patterned dielectric layer includes a first dielectric layer disposed on the semiconductor layer of the first region and the first doped layers, and an etching stop layer disposed on the semiconductor layer of the second region. Another doped layer is formed on the semiconductor layer and the patterned dielectric layer. The another doped layer is patterned to form two second doped layers in the second region, and the semiconductor layer is patterned to form a first semiconductor layer in the first region and a second semiconductor layer in the second region. A gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the second doped layers, the first dielectric layer and the etching stop layer. A first patterned conductive layer is formed on the gate insulating layer, wherein the first patterned conductive layer includes a first gate electrode disposed on the gate insulating layer of the first region, and a second gate electrode disposed on the gate insulating layer of the second region. A first source electrode and a first drain electrode electrically connected to the first doped layers respectively are formed in the first region, and a second source electrode and a second drain electrode electrically connected to the second doped layers respectively are formed in the second region.
  • The method of forming semiconductor device of the present invention uses a first dielectric layer to protect the semiconductor layer of the first region from being damaged, and uses an etching stop layer to protect the semiconductor layer of the second region from being damaged when patterning the second doped layers. The first dielectric layer and the etching stop layer are defined by the same patterned dielectric layer, and therefore no extra process is required. In addition, fabrication cost can be reduced, and yield can be improved.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-8 are schematic diagrams illustrating a method of forming semiconductor device according to a first preferred embodiment of the present invention.
  • FIG. 9 is a schematic diagram illustrating a method of forming semiconductor device according to a second preferred embodiment of the present invention.
  • FIGS. 10-11 are schematic diagrams illustrating a method of forming semiconductor device according to a third preferred embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • To provide a better understanding of the present invention to the skilled users in the technology of the present invention, preferred embodiments will be detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to elaborate the contents and effects to be achieved.
  • Please refer to FIGS. 1-8. FIGS. 1-8 are schematic diagrams illustrating a method of forming semiconductor device according to a first preferred embodiment of the present invention. As shown in FIG. 1, a substrate 10 is provided. The substrate 10 may be a glass substrate, a plastic substrate or a quartz substrate, but not limited thereto. The substrate 10 has a first region 101 and a second region 102. Then, a semiconductor layer 12 is formed on the substrate 10. Subsequently, a doped layer 16 is formed on the semiconductor layer 12. In this embodiment, the semiconductor layer 12 maybe an amorphous silicon layer, and an annealing process 14 may be carried out to convert the amorphous silicon layer into a polycrystalline silicon layer. The annealing process may be a laser annealing process, but not limited thereto. For example, the annealing process 14 may also be a thermal process. In this embodiment, the doped layer 16 is a P type doped semiconductor layer, but not limited thereto. The doped layer 16 can be formed by performing a non-implant process e.g. a chemical vapor deposition process, a physical vapor deposition process, a spin-on coating process, etc., along with introducing P type doped semiconductor material e.g. boron or boron compound during the non-implant process, but not limited thereto. After the doped layer 16 is formed, an annealing process 14 e.g. a laser annealing process can be performed to reduce the resistance of the doped layer 16. The annealing process 14 for converting the amorphous silicon layer into a polycrystalline silicon layer and the annealing process 14 for reducing the resistance of the doped layer 16 can be integrated. In other words, after the doped layer 16 is formed, one annealing process 14 can be performed to convert the amorphous silicon layer into a polycrystalline silicon layer, as well as reduce the resistance of the doped layer 16. The material of the semiconductor layer 12 is not limited to amorphous silicon, and may be other semiconductor material.
  • As shown in FIG. 2, the doped layer 16 is then patterned, for example by performing a lithography and etching process to form two first doped layers 161 in the first region 101. In this embodiment, the first doped layers 161 are P type doped semiconductor layers. As shown in FIG. 3, a patterned dielectric layer 18 is formed on the substrate 10 and the first doped layers 161. The patterned dielectric layer 18 includes a first dielectric layer 181 disposed on the semiconductor layer 12 and the first doped layers 161 in the first region 101, and an etching stop layer 182 disposed on the semiconductor layer 12 in the second region 102. The first dielectric layer 181 and a first gate insulating layer (not shown) to be formed subsequently are used as a gate insulating layer for protecting the semiconductor layer 12 in the first region 101 from being damaged in the successive process. The etching stop layer 182 is used as an etching stop layer for protecting the semiconductor layer 12 in the second region 102 from being damaged when patterning second doped layers in the successive process. The first dielectric layer 181 and the etching stop layer 182 are made of the same patterned dielectric layer 18, and thus no extra process is required. The material of the patterned dielectric layer 18 maybe various types of dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. In addition, the patterned dielectric layer 18 may be a single-layered dielectric structure or a composite-layered dielectric structure.
  • As shown in FIG. 4, another doped layer 20 is formed on the semiconductor layer 12 and the patterned dielectric layer 18. In this embodiment, the doped layer 20 is an N type doped semiconductor layer, but not limited thereto. The doped layer 20 can be formed by performing a non-implant process e.g. a chemical vapor deposition process, a physical vapor deposition process, a spin-on coating process, etc., along with introducing N type doped semiconductor material e.g. phosphorus or phosphorus compound during the non-implant process, but not limited thereto. After the doped layer 20 is formed, an annealing process 14 e.g. a laser annealing process can be performed to reduce the resistance of the doped layer 20. The annealing process 14 for converting the amorphous silicon layer into a polycrystalline silicon layer and the annealing process 14 for reducing the resistance of the doped layer 16 can be integrated with the annealing process 14 for reducing the resistance of the doped layer 20. In other words, after the doped layer 20 is formed, one annealing process 14 can be performed to convert the amorphous silicon layer into a polycrystalline silicon layer, as well as reduce the resistance of the doped layer 16 and the doped layer 20. As shown in FIG. 5, a lithography and etching process, for example, is performed to form a photo resist pattern (not shown) on the doped layer 20, and the doped layer 20 is etched to form two second doped layers 201 in the second region 102. In this embodiment, the etching stop layer 182 is disposed between the second doped layers 201, and the second doped layers 201 may partially cover the etching stop layer 182, but not limited. For example, the second doped layers 201 may be disposed on two opposite sides of the etching stop layer 182 without covering the etching stop layer 182. The second doped layers 201 are N type doped semiconductor layers. The etching stop layer 182 are disposed on the semiconductor layer 12 in the second region 102, and thus the semiconductor layer 12 in the second region 102 would not be damaged when patterning the doped layer 20. Subsequently, the photo resist pattern is removed.
  • As shown in FIG. 6, the second doped layers 201, the etching stop layer 182 and the first dielectric layer 181 are used as an etching mask to pattern the semiconductor layer 12, thereby forming a first semiconductor layer 121 in the first region 101, and a second semiconductor layer 122 in the second region 102. The method of patterning the semiconductor layer 12 is not limited by the aforementioned method. In an alternative embodiment, for instance, the photo resist pattern for defining the doped layer 20 may be reserved until the semiconductor layer 12 is patterned, such that the second doped layers 201 can be protected from being damaged when etching the semiconductor layer 12. As shown in FIG. 7, a gate insulating layer 22 is formed on the substrate 10 to cover the second doped layers 201, the first dielectric layer 181 and the etching stop layer 182. The material of the gate insulating layer 22 maybe various types of dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. The gate insulating layer 22 may be a single-layered dielectric structure or a composite-layered dielectric structure. Subsequently, a first patterned conductive layer 24 is formed on the gate insulating layer 22. The first patterned conductive layer 24 includes a first gate electrode 241 disposed on the gate insulating layer 22 in the first region 101, and a second gate electrode 242 disposed on the gate insulating layer 22 in the second region 102. The material of the first patterned conductive layer 24 maybe metal or other conductive materials.
  • As shown in FIG. 8, at least one inter-layered dielectric (ILD) 26 is formed on the gate insulating layer 22, the first gate electrode 241 and the second gate electrode 242. The material of the ILD 26 may be various types of dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. Then, a plurality of first contact holes 281 are formed in the ILD 26, the gate insulating layer 22 and the first dielectric layer 181 in the first region 101 to partially expose each of the first doped layers 161 respectively, and a plurality of second contact holes 282 are formed in the ILD 26 and the gate insulating layer 22 in the second region 102 to partially expose each of the second doped layers 201 respectively. Subsequently, a second patterned conductive layer 30 is formed on the ILD 26. The second patterned conductive layer 30 includes a first source electrode 301S and a first drain electrode 301D disposed on the ILD 26 in the first region 101 and electrically connected to each of the first doped layers 161 respectively, and a second source electrode 302S and a second drain electrode 302D disposed on the ILD 26 in the second region 102 and electrically connected to each of the second doped layers 201 respectively. The material of the first source electrode 301S, the first drain electrode 301D, the second source electrode 302S and the second drain electrode 302D may be metal or other conductive materials. By virtue of the aforementioned method, a semiconductor device 40 of this embodiment is accomplished. In the first region 101, the first semiconductor layer 121, the first doped layers 161, the first dielectric layer 181, the gate insulating layer 22, the first gate electrode 241, the ILD 26, the first source electrode 301S and the first drain electrode 301D form a first thin film transistor device 401. In the second region 102, the second semiconductor layer 122, the etching stop layer 182, the second doped layers 201, the gate insulating layer 22, the second gate electrode 242, the ILD 26, the second source electrode 302S and the second drain electrode 302D form a second thin film transistor device 402.
  • The semiconductor device and method of making the same are not limited by the aforementioned embodiment, and may have other different preferred embodiments. To simplify the description, the identical components in each of the following embodiments are marked with identical symbols. For making it easier to compare the difference between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
  • Please refer to FIG. 9, as well as FIGS. 1-8. FIG. 9 is a schematic diagram illustrating a method of forming semiconductor device according to a second preferred embodiment of the present invention. As shown in FIG. 9, different from the aforementioned embodiment, in this embodiment, the first gate electrode 241 of the first thin film transistor device 501 is electrically connected to the second gate electrode 242 of the second thin film transistor device 502, and the first source electrode 301S and the second drain electrode 302D are electrically connected. The semiconductor device 50 of this embodiment may be a CMOS device, but not limited thereto. The first gate electrode 241 and the second gate electrode 242 may be electrically connected directly, or with another bridging structure. The first source electrode 301S and the second drain electrode 302D may be electrically connected directly, or with another bridging structure. The semiconductor device 50 may be applied in the peripheral circuit of electroluminescent display panel, but not limited thereto.
  • Please refer to FIGS. 10-11, as well as FIGS. 1-8. FIGS. 10-11 are schematic diagrams illustrating a method of forming semiconductor device according to a third preferred embodiment of the present invention. As shown in FIG. 10, in this embodiment, the first gate electrode 241 is electrically connected to the second drain electrode 302D. For instance, the second drain electrode 302D is electrically connected to the first gate electrode 241 through the contact hole 261 of the ILD 26. Then, a first passivation layer 61 is formed on the ILD 26, the first source electrode 301S, the first drain electrode 301D, the second source electrode 302S and the second drain electrode 302D. The first passivation layer 61 at least partially exposes the first drain electrode 301D. Subsequently, a first electrode 62 is formed on the first passivation layer 61 to electrically connect with the exposed first drain electrode 301D.
  • As shown in FIG. 11, a second passivation layer 63 is formed on the first passivation layer 61 and the first electrode 62. The second passivation layer 63 at least partially exposes the first electrode 62. A light-emitting layer 64 and a second electrode 65 are then formed on the first electrode 62 exposed by the second passivation layer 63 to accomplish a semiconductor device 70 of this embodiment. The semiconductor device 70 may be applied in the pixel structure of electroluminescent display panel. The first thin film transistor device 701 may serve as a driving thin film transistor device, the second thin film transistor device 702 may serve as a switching thin film transistor device, and the first electrode 62, the light-emitting layer 64 and the second electrode 65 form a light-emitting device 72, but not limited thereto. Also, in this embodiment, the first electrode 62 is an anode, and the second electrode is a cathode, but not limited thereto.
  • In conclusion, the method of forming semiconductor device of the present invention uses a non-implant process to form the doped layers, which is applicable in large-size display panel fabrication. The resistance of the doped layers is reduced by an annealing process, and thus the electrical characteristic of the semiconductor device is improved. In addition, the first dielectric layer of the semiconductor device is able to protect the semiconductor layer in the first region from being damaged, and the etching stop layer is able to protect the semiconductor layer from being damaged when defining the second doped layer. The first dielectric layer and the etching stop layer are defined by the same patterned dielectric layer. Accordingly, no extra process is required, fabrication cost is reduced, and yield is improved.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (9)

What is claimed is:
1. A method of forming semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming a semiconductor layer on the substrate;
forming a doped layer on the semiconductor layer, and patterning the doped layer to form two first doped layers in the first region;
forming a patterned dielectric layer on the substrate, wherein the patterned dielectric layer comprises a first dielectric layer disposed on the semiconductor layer of the first region and the first doped layers, and an etching stop layer disposed on the semiconductor layer of the second region;
forming another doped layer on the semiconductor layer and the patterned dielectric layer;
patterning the another doped layer to form two second doped layers in the second region, and patterning the semiconductor layer to form a first semiconductor layer in the first region and a second semiconductor layer in the second region;
forming a gate insulating layer on the substrate, the gate insulating layer covering the second doped layers, the first dielectric layer and the etching stop layer;
forming a first patterned conductive layer on the gate insulating layer, wherein the first patterned conductive layer comprises a first gate electrode disposed on the gate insulating layer of the first region, and a second gate electrode disposed on the gate insulating layer of the second region; and
forming a first source electrode and a first drain electrode electrically connected to the first doped layers respectively in the first region, and a second source electrode and a second drain electrode electrically connected to the second doped layers respectively in the second region.
2. The method of forming semiconductor device of claim 1, wherein the first doped layers and the second doped layers are formed by a non-implant process.
3. The method of forming semiconductor device of claim 2, further comprising performing at least one annealing process on the first doped layers, the second doped layers and the semiconductor layer.
4. The method of forming semiconductor device of claim 3, wherein the annealing process converts the semiconductor layer from an amorphous silicon layer to a polycrystalline silicon layer.
5. The method of forming semiconductor device of claim 1, wherein the first doped layers comprise P type doped semiconductor layers, and the second doped layers comprise N type doped semiconductor layers.
6. The method of forming semiconductor device of claim 1, further comprising:
forming at least one inter-layered dielectric (ILD) on the gate insulating layer, the first gate electrode and the second gate electrode prior to forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode;
forming a plurality of first contact holes in the ILD, the gate insulating layer and the first dielectric layer of the first region to partially expose each of the first doped layers, respectively; and
forming a plurality of second contact holes in the ILD and the gate insulating layer of the second region to partially expose each of the second doped layers, respectively;
wherein the first source electrode and the first drain electrode are electrically connected to the first doped layers through the first contact holes respectively, and the second source electrode and the second drain electrode are electrically connected to the second doped layers through the second contact holes respectively.
7. The method of forming semiconductor device of claim 6, further comprising forming a light-emitting device, wherein the light-emitting device comprises a first electrode, a light-emitting layer and a second electrode, and the first electrode is electrically connected to the first drain electrode.
8. The method of forming semiconductor device of claim 1, further comprising electrically connecting the first source electrode with the second drain electrode, and electrically connecting the first gate electrode with the second gate electrode.
9. The method of forming semiconductor device of claim 1, further comprising electrically connecting the first gate electrode with the second drain electrode.
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