TWI712080B - Semiconductor structure and the manufacturing method of the same - Google Patents

Abstract

A method for manufacturing a semiconductor structure includes providing a substrate. The substrate is divided into an operating area and a sensing area. The method also includes forming a semiconductor element in the operating area and forming a sensing element in the sensing area. The method further includes forming a dielectric layer on the substrate. The method includes forming a pad on the dielectric layer. The pad is electrically connected to the semiconductor element. The method also includes forming a supporting layer on the pad and the dielectric layer. The method further includes forming at least one conductive layer on the supporting layer. The conductive layer includes a first portion and a second portion. The first portion is electrically connected to the semiconductor element, and the second portion has at least one hole and is disposed on the sensing element. The method incudes patterning the supporting layer, the dielectric layer and the sensing element through the hole to form an etching trench. The method also includes removing the second portion.

Description

Semiconductor structure and its manufacturing method

The embodiment of the disclosure relates to a manufacturing method of a semiconductor structure, and more particularly to a manufacturing method of a semiconductor structure using a conductive layer as a mask for a patterning process.

The cantilever structure is often used in devices that require isolation, such as sensing devices such as mass sensors, thermal sensors, and voiceprint sensors. In this type of device, the cantilever structure is often used as a supporting layer or a supporting film, so that it can be used as a support for a floating structure.

If the support layer or the support film is excessively stretched or compressed, the sensing device will not operate normally. Therefore, the thickness of the support layer or the support film, the size of the aperture formed by patterning the support layer or the support film, etc., are key factors that affect the performance of the sensing device.

Although current semiconductor structures used to form sensing devices generally meet the requirements, they are not satisfactory in every respect.

The embodiment of the disclosure relates to a manufacturing method of a semiconductor structure using a conductive layer as a mask to perform a patterning process. Through the manufacturing method of the disclosed embodiment, the thickness of the support layer can be precisely adjusted, and the size of the aperture formed by patterning the support layer can be further reduced. Through the manufacturing method of the disclosed embodiment, the complexity of the manufacturing process can be reduced, thereby reducing the time and cost of the manufacturing process.

The disclosed embodiments include a method for manufacturing a semiconductor structure. The manufacturing method includes providing a substrate. The substrate is divided into an operation area and a sensing area. The manufacturing method also includes forming a semiconductor element in the operation area and forming a sensing element in the sensing area. The manufacturing method further includes forming a dielectric layer on the substrate. The manufacturing method also includes forming a contact on the dielectric layer. The contact is electrically connected to the semiconductor element. The manufacturing method further includes forming a support layer on the contact and the dielectric layer. The manufacturing method includes forming at least one conductive layer on the support layer. The conductive layer includes a first part and a second part. The first part is electrically connected to the semiconductor element, and the second part has at least one through hole and is disposed on the sensing element. The manufacturing method also includes patterning the support layer, the dielectric layer and the sensing element through at least one through hole to form an etching trench. This manufacturing method further includes removing the second part.

The disclosed embodiment includes a semiconductor structure. The semiconductor structure includes a substrate, and the substrate may have an operation area and a sensing area. The semiconductor structure includes a semiconductor element, and the semiconductor element is disposed in the operation area. The semiconductor structure includes a sensing element, and the sensing element is disposed in the sensing area. The semiconductor structure includes a dielectric layer, which is disposed on the substrate. The semiconductor structure includes a contact, which is arranged on the dielectric layer and electrically connected to the semiconductor element. The semiconductor structure includes a support layer disposed on the contact and the dielectric layer. The semiconductor structure includes at least one conductive layer, and the conductive layer is disposed on the support layer. The conductive layer includes a dummy part, which is located in the sensing area and disposed on the sensing element.

The following disclosure provides many different embodiments or examples to implement different features of this case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not meant to be limiting. For example, if the embodiment of the present disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact. It may include an embodiment in which an additional characteristic part is formed between the first characteristic part and the second characteristic part, and the first characteristic part and the second characteristic part may not be in direct contact.

It should be understood that additional operation steps may be implemented before, during or after the method, and in other embodiments of the method, part of the operation steps may be replaced or omitted.

In addition, terms related to space may be used, such as "below", "below", "lower", "above", "above", "higher" and similar terms. These space-related terms are used to facilitate the description of the relationship between one element(s) or characteristic part and another (some) elements or characteristic parts in the illustration. These space-related terms include the difference between devices in use or operation. Position, and the position described in the diagram. When the device is turned in different directions (rotated by 90 degrees or other directions), the space-related adjectives used therein will also be interpreted according to the turned position.

In the manual, the terms "about", "approximately" and "approximately" usually mean within 20%, or within 10%, or within 5%, or within 3% of a given value or range. Or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, the meaning of "about", "approximately" and "approximately" can still be implied without specifying "about", "approximately" or "approximately".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings commonly understood by the general artisans to whom the disclosure belongs. It is understandable that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meaning consistent with the relevant technology and the background or context of this disclosure, and should not be used in an idealized or overly formal way. Interpretation, unless there is a special definition in the embodiment of the present disclosure.

The different embodiments disclosed below may use the same reference symbols and/or marks repeatedly. These repetitions are for the purpose of simplification and clarity, and are not used to limit the specific relationship between the different embodiments and/or structures discussed.

In the embodiment of the present disclosure, since the method used to remove the conductive layer and the dielectric layer is different (for example, using different etching liquids for etching), a higher selectivity can be generated, so that the conductive layer serves as The mask is used for the patterning process to accurately adjust the thickness of the support layer, and further reduce the size of the aperture formed by patterning the support layer. In addition, through the manufacturing method of the embodiment of the disclosure, the number of uses of the patterned photoresist can be reduced, the complexity of the manufacturing process is reduced, and the manufacturing process time and cost can be reduced.

FIG. 1 to FIG. 8 are partial schematic diagrams illustrating the formation of the semiconductor structure 100 shown in FIG. 8 in various process stages according to some embodiments of the present disclosure. It should be noted that, in order to facilitate the display of the features of the embodiment of the present disclosure, FIGS. 1 to 8 illustrate the semiconductor structure 100 in cross-section, but they do not represent the cross-section of the semiconductor structure 100 at a specific location. In addition, some elements may be omitted in FIGS. 1 to 8.

Referring to Figure 1, a substrate 10 is provided. In some embodiments, the substrate 10 may include elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. Etc.; alloy semiconductors, such as: silicon germanium (silicon germanium), gallium arsenide phosphide (gallium arsenide phosphide), aluminum indium phosphide (aluminum indium phosphide), aluminum gallium arsenide (aluminum gallium arsenide), gallium indium arsenide (gallium Indium arsenide), gallium indium phosphide (gallium indium phosphide), gallium indium arsenide phosphide (gallium indium arsenide phosphide), etc. or a combination of the foregoing, but the embodiments of the disclosure are not limited thereto. In some embodiments, the substrate 10 may be a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate on the insulating layer may include a bottom plate, a buried oxide layer disposed on the bottom plate, and a semiconductor layer disposed on the buried oxide layer. In some embodiments, the substrate 10 may be a semiconductor wafer (for example, a silicon wafer or other suitable semiconductor wafer).

In some embodiments, the substrate 10 may include various p-type doped regions and/or n-type doped regions formed by processes such as ion implantation and/or diffusion. For example, the aforementioned doped regions can be configured to form transistors, photodiodes and/or light-emitting diodes, but the embodiments of the disclosure are not limited thereto.

In some embodiments, the substrate 10 may include various isolation features to separate different device regions in the substrate 10. For example, the isolation features may include shallow trench isolation (STI) features, but the embodiments of the disclosure are not limited thereto. In some embodiments, the step of forming shallow trench isolation may include etching a trench in the substrate 10 and filling the trench with an insulating material (for example, silicon oxide, silicon nitride, or silicon oxynitride) . The filled trench may have a multilayer structure (for example, a thermal oxide liner and silicon nitride filled in the trench). A chemical mechanical polishing (CMP) process can be performed to polish excess insulating material and planarize the upper surface of the isolation feature.

In some embodiments, the substrate 10 may include various conductive features (for example, conductive lines or vias). For example, the aforementioned conductive features can be formed of aluminum (Al), copper (Cu), tungsten (W), their respective alloys, other suitable conductive materials, or a combination of the foregoing.

For example, the substrate 10 may be, for example, a P-type substrate, and as shown in FIG. 1, the substrate 10 is divided into an operation area 10C and a sensing area 10S, but the embodiment of the disclosure is not based on This is limited. Next, a semiconductor element 20 is formed in the operation area 10C, and a sensing element 30 is formed in the sensing area 10S.

As shown in Figure 1, in some embodiments, the semiconductor device 20 is, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), which may include a well region 21, such as P The well region may include dopants such as boron, aluminum, gallium, indium, and thallium, but the embodiment of the disclosure is not limited thereto. In some embodiments, the implantation area may be formed by ion implantation, and a thermal process (for example, an annealing process) may be performed on the implantation area to form the aforementioned well region 21, but the embodiment of the disclosure is not limited thereto.

In some embodiments, the semiconductor device 20 also includes a heavily doped region 23 and a heavily doped region 25. The heavily doped region 23 and the heavily doped region 25 are, for example, N-type doped regions, which may include nitrogen, phosphorus, and arsenic. , Antimony, and bismuth doping, but the embodiment of the disclosure is not limited to this. Similarly, in some embodiments, the implanted region may be formed by ion implantation, and a thermal process (for example, an annealing process) may be performed on the implanted region to form the aforementioned heavily doped region 23 and heavily doped region 25, but The embodiment of the disclosure is not limited to this. In some embodiments, the average doping concentration of the heavily doped region 23 and the heavily doped region 25 are both greater than the average doping concentration of the well region 21. In some embodiments, the heavily doped region 23 and the heavily doped region 25 can be, for example, the source/drain regions of the semiconductor device 20.

In some embodiments, the semiconductor device 20 further includes a gate structure 27. The gate structure 27 can be disposed between the heavily doped region 23 and the heavily doped region 25, and is located above the well region 21, but the present disclosure is implemented The examples are not limited to this. In some embodiments, the gate structure 27 may include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. In some embodiments, a layer of dielectric material and a layer of conductive material on it can be sequentially blanket deposited on the substrate 10, and then the dielectric material layer and the conductive material layer are lithographically and The etching process is patterned to form a gate dielectric layer and a gate electrode respectively.

For example, the aforementioned dielectric material layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, any other suitable dielectric material, or a combination of the above, but the present disclosure The embodiment is not limited to this. In some embodiments, the aforementioned high-k dielectric material may include LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO ₃ (BST), Al ₂ O ₃ , other suitable high-k dielectric materials Or a combination.

In some embodiments, the dielectric material layer may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating, but the disclosed embodiments Not limited to this. For example, the aforementioned chemical vapor deposition method may be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), and rapid temperature chemical vapor deposition. Method (rapid thermal chemical vapor deposition, RTCVD) or plasma enhanced chemical vapor deposition (PECVD).

In some embodiments, the aforementioned conductive material layer may be formed of polysilicon, but the embodiment of the disclosure is not limited thereto. In some embodiments, the aforementioned conductive material layer may be made of metal (for example, tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, similar metal materials or a combination of the foregoing), metal alloys, metal nitrides (for example, nitride Tungsten, molybdenum nitride, titanium nitride, tantalum nitride, similar metal nitrides or combinations of the foregoing), metal silicides (for example, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, similar Or a combination of the foregoing), a metal oxide (for example, ruthenium oxide, indium tin oxide, similar metal oxides or a combination of the foregoing), other suitable conductive materials, or a combination of the foregoing.

In some embodiments, the conductive material layer may be formed by a chemical vapor deposition process, a physical vapor deposition process (for example, a vacuum evaporation process or a sputtering process), other appropriate processes or The aforementioned combination is formed, but the embodiment of the disclosure is not limited thereto.

In some embodiments, the semiconductor device 20 includes an isolation structure 29. The isolation structure 29 can be disposed outside the heavily doped region 23 and the heavily doped region 25, but the embodiment of the disclosure is not limited thereto. In some embodiments, the material of the isolation structure 29 may include dielectric materials, such as silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), nitride Aluminum (AlN), Magnesium Oxide (MgO), Magnesium Nitride (Mg ₃ N ₂ ), Zinc Oxide (ZnO), Titanium Oxide (TiO ₂ ), other suitable materials or a combination of the foregoing, but the embodiments of this disclosure are not This is limited.

In some embodiments, the isolation structure 29 can be formed through a deposition process, a photolithography process, other appropriate processes, or a combination of the foregoing, but the embodiment of the disclosure is not limited thereto. For example, the photolithography process may include photoresist coating (for example, spin-on coating), soft baking, mask aligning, exposure, Post-exposure baking (PEB), developing (developing), washing (rinsing), drying (such as hard baking), other suitable processes or a combination of the foregoing, but the embodiments of the present disclosure are not limited to this .

As shown in FIG. 1, in some embodiments, the sensing element 30 is, for example, a thermal sensing element. For example, the sensing device 30 may include a semiconductor layer 33, an oxide layer 31, and a thermopile (Thermopile) 35, 37.

In some embodiments, the material of the semiconductor layer 33 may be polysilicon, for example, but the embodiment of the disclosure is not limited thereto. In some embodiments, the material of the oxide layer 31 may include silicon oxide (SiO ₂ ), other suitable materials, or a combination thereof, but the embodiment of the disclosure is not limited thereto. Specifically, as shown in FIG. 1, the oxide layer 31 can be divided into a first oxide layer 311 and a second oxide layer 313. The first oxide layer 311 may surround the semiconductor layer 33, and the second oxide layer 313 may be disposed on the top surface of the semiconductor layer 33, but the embodiment of the disclosure is not limited thereto.

In some embodiments, the thermopile 35 and 37 may be disposed on the oxide layer 31. More specifically, the thermopile 35, 37 may be disposed on the second oxide layer 313. In some embodiments, the materials of the thermopile 35 and 37 may include P-type heavily doped polysilicon and N-type heavily doped polysilicon, respectively. P-type heavily doped polysilicon may include doped materials such as boron, aluminum, gallium, indium, and thallium. Impurities, and the N-type heavily doped polysilicon may include nitrogen, phosphorus, arsenic, antimony, and bismuth dopants, but the embodiment of the disclosure is not limited to this.

As shown in Figure 1, in this embodiment, the thermopile 35 may have a through hole 35T, the thermopile 37 may have a through hole 37T, and the through holes 35T and 37T may expose part of the oxide layer 31 (second oxide layer 313) The top surface. It should be noted that, although in the embodiment shown in FIG. 1, the thermopile 35 has two through holes 35T and the thermopile 37 has two through holes 37T, the embodiment of the disclosure is not limited thereto.

Referring to FIG. 2, a dielectric layer 41 is formed on the substrate 10. Specifically, the dielectric layer 41 can be formed on the semiconductor device 20 (the heavily doped region 23, the heavily doped region 25, the gate structure 27, the isolation structure 29) and the sensing device 30 (the oxide layer 31, the semiconductor layer 33, The thermopile 35, 37) is filled in the through holes 35T, 37T, but the embodiment of the disclosure is not limited to this.

In some embodiments, the material of the dielectric layer 41 may include tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass (for example, boron phosphate glass). silicate glass (BPSG)), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and other doped silicon dioxide (doped silicon dioxide) oxide) and/or other appropriate dielectric materials, but the embodiments of the disclosure are not limited thereto.

In some embodiments, the dielectric layer 41 may be formed by plasma-assisted chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), or other appropriate methods, but the original The disclosed embodiments are not limited to this.

Next, a contact 45 is formed on the dielectric layer 41. In this embodiment, the contact 45 can be electrically connected to the semiconductor device 20. For example, as shown in FIG. 2, the contact 45 is located in the operation area 10C of the substrate 10, and it can be electrically connected to the heavily doped area 23 and the heavily doped area 25 through the conductive plug 43, but the disclosed embodiment Not limited to this.

In some embodiments, the material of the conductive plug 43 and the contact 45 may include polysilicon and/or metal. For example, the metal may include titanium aluminum nitride (TiAlN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), titanium (Ti), aluminum (Al), cobalt (Co), tantalum carbide (TaC), tantalum carbide (TaCN), tantalum silicon nitride (TaSiN), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN) ), other suitable materials or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto.

In some embodiments, the conductive plug 43 and the contact 45 can be formed by chemical vapor deposition, physical vapor deposition, plating, and/or other suitable processes, but the disclosed embodiment is not limit. In some embodiments, the contact 45 can be further formed through a photolithography process, but the embodiment of the disclosure is not limited thereto. The example of the photolithography process is as described above, so I won't repeat it here.

As shown in FIG. 2, in some embodiments, the dielectric layer 41 may include a hole 47. The hole 47 may expose a portion of the sensing element 30, but does not expose the portion of the sensing element 30 corresponding to the through holes 35T and 37T. Specifically, the hole 47 may expose part of the thermopile 35, 37, but the embodiment of the disclosure is not limited to this.

Referring to FIG. 3, a support layer 48 is formed on the contact 45 and the dielectric layer 41. The material and forming method of the support layer 48 can be the same as or similar to those of the dielectric layer 41, which will not be repeated here, but the embodiment of the disclosure is not limited thereto. In addition, as shown in FIG. 3, the support layer 48 can fill the holes 47 of the dielectric layer 41. Therefore, the support layer 48 can serve as a support for the sensing element 30 to form a suspension structure in the subsequent manufacturing process.

Then, a conductive layer is formed on the supporting layer 48. As shown in Figure 3, in this embodiment, the conductive layer may include a first portion 51C and a second portion 51S. The first portion 51C is electrically connected to the semiconductor element 20, and the second portion 51S has a plurality of through holes 51T and Set on the sensing element 30. Specifically, the first portion 51C of the conductive layer is located in the operation area 10C of the substrate 10 and can be electrically connected to the contact 45 through the conductive plug 49, but the embodiment of the disclosure is not limited thereto.

In some embodiments, the second portion 51S of the conductive layer is a patterned conductive layer, which has a plurality of through holes 51T, and the maximum width of the cross section of each through hole 51T is at least less than or equal to 0.5 μm. However, the disclosed embodiment Not limited to this. Specifically, the second portion 51S of the conductive layer is located in the sensing area 10S of the substrate 10 and is correspondingly disposed on the sensing element 30. In addition, as shown in FIG. 3, the through hole 51T may be provided corresponding to the through hole 35T of the thermopile 35 and the through hole 37T of the thermopile 37. The second portion 51S of the conductive layer can be used as a patterned mask in the subsequent manufacturing process, which will be described in detail later.

In addition, in some embodiments, the materials and forming methods of the first portion 51C and the second portion 51S of the conductive layer may be the same as or similar to the conductive plug 43 and the contact 45, and will not be repeated here, but the disclosed embodiment is not Limit this.

Referring to FIG. 4, an interlayer dielectric layer 53 is formed on the conductive layer (the first portion 51C and the second portion 51S) and the supporting layer 48. The material and forming method of the interlayer dielectric layer 53 can be the same as or similar to the dielectric layer 41, which will not be described here, but the embodiment of the disclosure is not limited thereto. Next, a conductive layer 57 is formed on the interlayer dielectric layer 53. The material and forming method of the conductive layer 57 can be the same as or similar to the conductive plug 43 and the contact 45, which will not be repeated here, but the embodiment of the disclosure is not limited thereto. In addition, the conductive layer 57 can be electrically connected to the first portion 51C of the conductive layer through the conductive plug 55, but the embodiment of the disclosure is not limited thereto.

Referring to FIG. 5, an interlayer dielectric layer 59 is formed on the conductive layer 57 and the interlayer dielectric layer 53. The material and forming method of the interlayer dielectric layer 59 can be the same as or similar to those of the dielectric layer 41, which will not be repeated here, but the embodiment of the disclosure is not limited thereto. As shown in FIG. 5, in some embodiments, the interlayer dielectric layer 59 may include a hole 59T, and the hole 59T may expose a part of the conductive layer 57, but the embodiment of the disclosure is not limited thereto.

It should be noted that the number of dielectric layers (including interlayer dielectric layers) and conductive layers (including contacts) of the semiconductor structure 100 is not limited to that shown in FIG. 5. That is, the semiconductor structure 100 may include a plurality of conductive layers and a plurality of (interlayer) dielectric layers, and the (interlayer) dielectric layers may be disposed between the plurality of conductive layers. The number of dielectric layers and conductive layers can be adjusted according to actual needs, and will not be repeated here.

Referring to FIG. 6, a patterned photoresist layer 61 is formed on the interlayer dielectric layer 59. As shown in FIG. 6, the patterned photoresist layer 61 may have a hole 61T, and the hole 61T is located in the sensing area 10S. In more detail, the holes 61T of the patterned photoresist layer 61 may be provided corresponding to the second portion 51S of the conductive layer. In this embodiment, the maximum width W1 of the cross section of the hole 61T is smaller than the maximum width W of the second portion 51S of the conductive layer (marked in FIG. 3), but the embodiment of the disclosure is not limited thereto.

In some embodiments, the patterned photoresist layer 61 may be a positive photoresist or a negative photoresist, for example. In some embodiments, the patterned photoresist layer 61 can be a single-layer or multi-layer structure, and the patterned photoresist layer 61 can be formed through, for example, a deposition process, a photolithography process, other appropriate processes, or a combination of the foregoing, but the present disclosure The embodiment is not limited to this.

Referring to FIG. 7, an etching process is performed and the interlayer dielectric layer 59 and the interlayer dielectric layer 53 are etched through the holes 61T of the patterned photoresist layer 61 to expose the top surface 51ST of the second portion 51S of the conductive layer. In some embodiments, the etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, the dry etching process can use fluorine-containing gas (for example: CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and/or C ₂ F ₆ ), other suitable gases and/or plasma, and/or A combination of the above. For example, the wet etching process may include etching in the following solutions: diluted hydrofluoric acid (DHF), including hydrofluoric acid (HF), nitric acid (HNO ₃ ) and/or acetic acid (CH ₃ COOH) solution or other appropriate wet etchant. However, the embodiments of the present disclosure are not limited to this.

Next, perform an etching process and pattern the support layer 48 and the dielectric layer 41 through the through holes 51T of the second portion 51S of the conductive layer (for example, including removing the dielectric layer 41 filled in the holes 35T and 37T), To form an etching trench 63. In this embodiment, the etching trench 63 may be connected to the semiconductor layer 33, for example. The example of the etching process is as described above, and will not be repeated here, but the embodiment of the disclosure is not limited thereto.

Referring to FIG. 8, the second portion 51S of the conductive layer and the patterned photoresist layer 61 are removed to form the semiconductor structure 100. In this embodiment, the second portion 51S of the conductive layer is removed to expose a portion of the support layer 48. In some embodiments, another etching process may be performed to remove the second portion 51S of the conductive layer. In some embodiments, the other etching process may include dry etching, wet etching, reactive ion etching, and/or other suitable processes. For example, the dry etching process may use chlorine-containing gas (eg, Cl ₂ , CHCl ₃ , CCl ₄ and/or BCl ₃ ), other suitable gases and/or plasma, and/or a combination of the foregoing. For example, the wet etching process may include etching in a chlorine-containing solution, but the embodiment of the disclosure is not limited thereto.

Since the material of the second part 51S of the conductive layer is different from that of the support layer 48, the liquid or gas used to etch the second part 51S of the conductive layer is not easy to etch the support layer 48 (that is, it is highly selective). The thickness T of the support layer 48 is precisely adjusted to reduce the possibility that the support layer 48 is excessively stretched or compressed, so that the sensing element 30 can operate normally. In some embodiments, the support layer 48 may be further etched, but the embodiment of the disclosure is not limited thereto.

As shown in Figure 8, in some embodiments, the maximum width of the interlayer dielectric layer 59 and the interlayer dielectric layer 53 through the hole 61T of the patterned photoresist layer 61 is approximately equal to the maximum width W1 of the cross section of the hole 61T. . Under this condition, compared with the semiconductor structure that generally does not have the second portion 51S as a mask, the embodiment of the disclosure can penetrate the etching trench formed by the patterned conductive layer (ie, the second portion 51S) 63 to remove the semiconductor layer 33, so that the etching trench 63 can be further reduced. For example, the maximum width W2 of the cross-section of the etching trench 63 can be reduced to less than or equal to 0.5 μm to further improve the isolation of the sensing element 30 effect.

Finally, another etching process is performed to remove the semiconductor layer 33 of the sensing device 30 through the etching trench 63 to form a cavity 39 in the area originally occupied by the semiconductor layer 33. For example, the semiconductor layer 33 can be plasma-etched by passing gas through the etching trench 63 to form the cavity 39, so that the sensing element 30 forms a suspension structure, but the embodiment of the disclosure is not limited thereto.

Furthermore, through the manufacturing method of the embodiment of the present disclosure, the number of uses of the patterned photoresist can be reduced (for example, the patterned photoresist 61 is used only once in this embodiment, but the embodiment of the present disclosure is not limited to this). It can reduce the complexity of the process, thereby reducing the process time and cost.

It should be noted that although in the foregoing embodiments, the second portion 51S of the conductive layer and the first portion 51C of the conductive layer are simultaneously formed as an example for description, the disclosure is not limited to this. In other embodiments, the second portion 51S of the conductive layer can also be formed at the same time as the conductive layer 57, and can be adjusted according to the (predetermined) thickness T of the support layer 48.

In some embodiments, since the maximum width W1 of the cross section of the hole 61T of the patterned photoresist 61 is smaller than the maximum width W of the second portion 51S of the conductive layer, a portion may remain when the second portion 51S of the conductive layer is removed The dummy conductive layer 51SD is on the interlayer dielectric layer 53, but the embodiment of the disclosure is not limited to this. That is, as shown in FIG. 8, the semiconductor structure 100 of the present disclosure may include a substrate 10, and the substrate 10 may have an operation area 10C and a sensing area 10S. The semiconductor structure 100 may include a semiconductor element 20 disposed in the operation area 10C. The semiconductor structure 100 may include a sensing element 30 disposed in the sensing area 10S. The semiconductor structure 100 may include a dielectric layer 41 disposed on the substrate 10. The semiconductor structure 100 may include a contact 45, and the contact 45 is disposed on the dielectric layer 41 and electrically connected to the semiconductor device 20. The semiconductor structure 100 may include a supporting layer 48 disposed on the contact 45 and the dielectric layer 41. The semiconductor structure 100 may include at least one conductive layer, and the conductive layer is disposed on the support layer 48. The conductive layer includes a dummy part (not shown), and the dummy part is located in the sensing area 10S and disposed on the sensing element 30.

The components of the several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present disclosure can better understand the viewpoints of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field of the present disclosure should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can do everything without departing from the spirit and scope of this disclosure. Various changes, substitutions and replacements. Therefore, the protection scope of this disclosure shall be subject to the scope of the attached patent application. In addition, although the present disclosure has been disclosed in several preferred embodiments as described above, it is not intended to limit the present disclosure.

Reference to features, advantages, or similar language throughout this specification does not mean that all the features and advantages that can be achieved with the present disclosure should be or be in any single embodiment of the present disclosure. In contrast, language related to features and advantages is understood as meaning that a particular feature, advantage, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, the discussion of features and advantages and similar language throughout the specification may but does not necessarily represent the same embodiment.

Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner. Based on the description herein, those skilled in the relevant art will realize that the present disclosure can be implemented without one or more specific features or advantages of a specific embodiment. In other cases, additional features and advantages can be recognized in certain embodiments, and these features and advantages may not exist in all embodiments of the present disclosure.

100: semiconductor structure

10: substrate

10C: Operating area

10S: Sensing area

20: Semiconductor components

21: Well area

23, 25: heavily doped area

27: Gate structure

29: isolation structure

30: sensing element

31: Oxide layer

311: first oxide layer

313: second oxide layer

33: Semiconductor layer

35, 37: thermopile

35T, 37T: through hole

39: Cavity

41: Dielectric layer

43: conductive plug

45: Contact

47: Hole

48: support layer

49: conductive plug

51C: The first part of the conductive layer

51S: The second part of the conductive layer

51SD: Virtual conductive layer

51ST: Top surface

51T: Through hole

53: Interlayer dielectric layer

55: conductive plug

57: conductive layer

59: Interlayer dielectric layer

59T: Hole

61: Patterned photoresist layer

61T: Hole

63: Etching groove

T: thickness

W: width

W1: width

W2: width

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the element may be enlarged or reduced to clearly show the technical features of the embodiment of the disclosure. FIG. 1 to FIG. 8 are partial schematic diagrams illustrating the formation of the semiconductor structure shown in FIG. 8 in different process stages according to some embodiments of the present disclosure.

100: semiconductor structure

10: substrate

10C: Operating area

10S: Sensing area

20: Semiconductor components

21: Well area

23, 25: heavily doped area

27: Gate structure

29: isolation structure

30: sensing element

31: Oxide layer

311: first oxide layer

313: second oxide layer

33: Semiconductor layer

35, 37: thermopile

41: Dielectric layer

43, 49: conductive plug

45: Contact

48: support layer

51C: Part One

51S: Part Two

51T: Through hole

W: width

Claims (10)

A method for manufacturing a semiconductor structure includes: Provide a substrate, wherein the substrate is divided into an operation area and a sensing area; Forming a semiconductor element in the operation area and forming a sensing element in the sensing area; Forming a dielectric layer on the substrate; Forming a contact on the dielectric layer, wherein the contact is electrically connected to the semiconductor element; Forming a support layer on the contact and the dielectric layer; At least one conductive layer is formed on the support layer, wherein the conductive layer includes a first part and a second part, the first part is electrically connected to the semiconductor element, and the second part has at least one through hole and is disposed on the sensing Component Pattern the support layer, the dielectric layer, and the sensing element through the at least one through hole to form an etching trench; and Remove the second part. According to the manufacturing method of the semiconductor structure described in the first item of the scope of patent application, the sensing element includes: A semiconductor layer; An oxide layer surrounding the semiconductor layer; and A thermopile arranged on the oxide layer; The etching trench is connected to the semiconductor layer. The manufacturing method of the semiconductor structure as described in item 2 of the scope of patent application further includes: The semiconductor layer is removed through the etching trench. The manufacturing method of the semiconductor structure as described in item 1 of the scope of patent application further includes: Forming a plurality of conductive layers on the supporting layer, wherein one of the conductive layers includes the first part and the second part; and At least one inter-dielectric layer is formed between the conductive layers. The manufacturing method of the semiconductor structure as described in item 4 of the scope of patent application further includes: A patterned photoresist layer is formed on the interlayer dielectric layer, wherein the patterned photoresist layer has a hole, and the hole is located in the sensing area. According to the manufacturing method of the semiconductor structure described in item 5 of the scope of patent application, the hole is provided corresponding to the second part. According to the manufacturing method of the semiconductor structure described in the scope of patent application, the maximum width of the cross section of the hole is smaller than the maximum width of the second part. The manufacturing method of semiconductor structure as described in item 5 of the scope of patent application further includes: The interlayer dielectric layer is etched through the hole to expose the top surface of the second part. According to the manufacturing method of the semiconductor structure described in the first item of the patent application, the maximum width of the cross section of the etching trench is less than or equal to 0.5 μm. A semiconductor structure including: A substrate with an operation area and a sensing area; A semiconductor element arranged in the operation area; A sensing element arranged in the sensing area; A dielectric layer disposed on the substrate; A contact, arranged on the dielectric layer and electrically connected to the semiconductor element; A supporting layer disposed on the contact and the dielectric layer; At least one conductive layer is disposed on the support layer, wherein the conductive layer includes a dummy part located in the sensing area and disposed on the sensing element.

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