TWI524530B - Semiconductor device and method of manufacturing the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an upright tunneling field effect transistor semiconductor device and a method of fabricating the same.

The semiconductor integrated circuit industry has experienced rapid growth over the past few decades. Advances in semiconductor materials and design techniques have made circuits smaller and more complex. Advances in the above materials and design have been achieved due to advances in related process technologies. In the course of semiconductor development, the number of components that can be interconnected per unit area is increasing due to the smaller and smaller size of the smallest components that can be reliably fabricated.

However, as the size of the smallest components shrinks, many challenges arise. As the components get closer, the leakage current becomes more pronounced; the signal becomes easier to cross; and the use of power becomes more important. The semiconductor integrated circuit industry has made many developments in an effort to reduce the size of components. One of the potential developments is to replace or supplement the traditional gold oxide half field effect transistor with a tunneling field effect transistor.

The tunneling field effect transistor is considered to be a potential device that can further reduce the power supply voltage and does not significantly increase the off-state leakage current due to the sub-resistance swing of the sub-60mv/dec sub-reshold swing. Set. However, current tunneling field effect transistors are not satisfactory in all respects.

The present invention provides embodiments of many different field effect transistor devices. The field effect transistor of the present invention provides one or more improvements over other prior methods. In one embodiment, the field effect transistor device includes: a precursor, the precursor includes: a substrate; a frustoconical protruding structure disposed on the substrate and protruding from the plane of the substrate; the gate stack is disposed on the substrate The gate stack has a flat portion parallel to the surface of the substrate and a gate surface encased in an intermediate portion of the frustoconical projecting structure; an isolation dielectric layer disposed on the flat portion and the substrate of the gate stack between. The field effect transistor device also includes a source region disposed at the top of the frustoconical bulging structure, the top portion of the frustoconical bulging structure including a portion overlapping the top of the gate surface of the gate stack a sidewall spacer disposed along a sidewall of the source region and disposed on the surface of the gate and connected to the isolation dielectric layer; a dielectric layer disposed on the source region; and a source contact, the source contact A critical dimension having a width substantially greater than the source region and formed on the source region and extending to the sidewall spacer.

In another embodiment, the vertical tunneling field effect transistor comprises: a semiconductor substrate; a frustoconical convex structure, a plane disposed on the substrate and protruding from the semiconductor substrate; and a source region having a first width a top portion of the frustoconical embossed structure; a high dielectric constant/metal gate disposed on the semiconductor substrate, the high dielectric constant/metal gate having a flat portion parallel to the surface of the semiconductor substrate and cladding The gate surface of the intermediate portion of the conical convex structure, the intermediate portion of the frustoconical projection structure includes a portion overlapping the source region. The field effect transistor device also includes: a sidewall spacer disposed along the source region and disposed on the gate surface; and a drain region disposed on the semiconductor substrate adjacent to the frustoconical protruding structure and extending Extending to the bottom of the frustoconical bulging structure becomes a raised bungee region; the isolation dielectric layer is disposed between the flat portion of the high dielectric constant/metal gate and the drain region, and is disposed in the source region and And a source contact having a second width disposed at the source region and the sidewall spacer, wherein the second width is substantially greater than the first width.

In another embodiment, a method of fabricating a semiconductor device includes: providing a precursor, the precursor comprising: a substrate; a frustoconical bulging structure disposed on the substrate and projecting a plane of the substrate; and a drain region disposed at a base and a frustoconical protruding structure, and extending to the bottom of the frustoconical protruding structure to form a raised bungee region; an isolating element disposed between each of the drain regions; and a gate stack disposed on the substrate Wherein the gate stack has a flat portion parallel to the surface of the substrate and a gate surface encased in the intermediate portion of the frustoconical projecting structure, the intermediate portion of the frustoconical projecting structure including the bungee region The overlapping portions; and the isolation dielectric layer are disposed between the flat portion of the gate stack and the drain region. The method also includes forming a sidewall spacer disposed along a top sidewall of the frustoconical bulge structure and disposed on a gate surface of the frustoconical bulge structure and connecting the isolation dielectric layer; Forming a source region on top of the protruding structure, wherein the doping profile of the source region is different from the drain region; depositing a dielectric layer on the source region, the gate stack, and the drain region; The dielectric layer and the isolation dielectric layer are selectively etched to form a source contact between the source region and the sidewall spacer, the gate contact is at a flat portion of the gate stack and the drain contact is at the drain region The key dimension of the formed source contact is substantially larger than the width of the source region.

100‧‧‧Methods for manufacturing semiconductor devices

102~110‧‧‧Processing steps for manufacturing semiconductor devices

200‧‧‧Precursors

210‧‧‧Base

215‧‧‧ Hard mask layer

220‧‧‧Frustum-conical protruding structure

230‧‧‧Isolation components

240‧‧‧Bungee Area

250‧‧‧gate stacking

255‧‧‧gate dielectric layer

256‧‧‧Metal gate

260‧‧‧Isolated dielectric layer

310‧‧‧ sidewall spacers

410‧‧‧ source area

505‧‧‧ dielectric layer

510‧‧‧ source contact

520‧‧‧gate contacts

530‧‧‧汲pole contacts

600‧‧‧ Tunneling field effect transistor device

W1, w2, w3, w4, w5, w6, w7‧‧‧ width

H1, h2, h3‧‧‧ height

1 is a flow chart of a method of fabricating a semiconductor device according to the present invention; Fig. 2 is a cross-sectional view of a precursor in a manufacturing step according to the method of Fig. 1; and Figs. 3 to 5 are cross-sectional views of the semiconductor device in each process step according to the method of Fig. 1.

It will be appreciated that many embodiments or examples are provided below to implement different features of the invention. Examples of specific elements and their arrangement are described below to clarify the invention. Of course, these are only examples and should not limit the scope of the invention. Furthermore, the first and second steps described in the description may include: the second step is followed by the first step of the embodiment and the first and second steps. Example. Different components may be drawn at different scales for concise purposes. Furthermore, when the first element is referred to in the description as being formed on the second element, it may include an embodiment in which the first element is in direct contact with the second element, and may include other elements formed in the first An embodiment between the second elements, wherein the first element is not in direct contact with the second element.

1 is a flow diagram of an embodiment of a method 100 for fabricating one or more tunneling field effect transistor devices in accordance with features disclosed herein. The method 100 will be discussed in detail below, and reference can be made to the tunneling field effect transistor device precursor 200 and the tunneling field effect transistor device 600 in FIGS. 2-5 as an example.

Referring to Figures 1 and 2, method 100 begins at step 102, which provides precursor 200 of field effect transistor device 600. The precursor 200 includes a substrate 210. This substrate 210 includes ruthenium. In another embodiment, the substrate 210 may include tantalum, niobium, gallium arsenide, tantalum carbide, indium arsenide, indium phosphide, gallium arsenide, gallium indium hydride. Or other suitable semiconductor materials. In some embodiments, substrate 210 can have an epitaxial layer overlying the bulk semiconductor. In addition, strain can be applied to the substrate 210 to enhance its performance. For example, the epitaxial layer can include a semiconductor material that is different from the bulk semiconductor. For example, the bismuth layer covers the main body 矽 or the 矽 layer covers the main body 锗. The epitaxial layer is formed by a process including selective epitaxial growth (SEG). Additionally, substrate 210 can include an insulating layer overlying cerium (SOI) structure, such as a buried dielectric layer. In addition, the substrate 210 may include a buried dielectric layer, such as a buried oxide layer (BOX), which is formed by oxygen implantation separation techniques, wafer bonding, selective epitaxial growth, or other suitable methods. . In fact, embodiments may include any form of substrate structure and materials. Substrate 210 may also include various P-type doped regions and/or N-type doped regions that are implemented by ion implantation and/or diffusion processes. These doped regions include the N and P wells.

The precursor 200 also includes a frustoconical bulging structure 220 having a first width (w1) that protrudes from the plane of the substrate 210 and has a first height (h1). The frustoconical bulging structure 220 is referred to as a core structure. This core structure 220 can be formed using a lithography and etching process. In one embodiment, the first step is to place the hard mask layer 215 on the substrate 210. Hard mask layer 215 includes hafnium oxide, tantalum nitride, hafnium oxynitride or other suitable dielectric materials. The hard mask layer 215 can be patterned and defined by a lithography and etching process to define a core structure 220 having a first width (w1). Next, during the etching process, the patterned hard mask layer 215 is treated as an etch mask while the substrate 210 is etched and forms the core structure 220. This etching process can include wet etching, dry etching, or a combination thereof. The core structure 220 has a side wall having an angle a with the plane of the substrate 210, the angle a being from about 45 degrees to about 90 degrees.

In an embodiment, the core structure 220 is cylindrical. In addition, the core structure 220 may also be a square columnar structure, an elliptical cylindrical structure, a rectangular columnar structure, a hexagonal columnar structure or other polygonal columnar structures.

The precursor 200 also includes a spacer element 230 formed on the substrate 210 between the core structures 220. Isolation element 230 includes different structures formed using different process technologies. In an embodiment, the isolation element 230 is a shallow trench isolation element (STI). The process of forming the shallow trench isolation features can include etching the trenches in the substrate 210 and filling the isolation material in the trenches. The insulating material includes cerium oxide, cerium nitride or cerium oxynitride. The filled trench can have a multilayer structure, such as a thermal oxide liner with a tantalum nitride filled trench.

The precursor 200 also includes a drain region 240 having a second width (w2) on the substrate 210, the second width (w2) being substantially greater than the first width (w1). In an embodiment, the drain region 240 and the core structure 220 have a common center. The drain region 240 can be formed using a doping and annealing process. In the present embodiment, the drain region 240 is adjacent to the core structure 220 and extends to the bottom of the core structure 220 and has a second height (h2) to become the raised bungee region 240. For P-type tunneling field effect transistors, the drain region 240 can be doped with a P-type dopant, such as boron or boron fluoride. For N-type tunneling field effect transistors, the drain region 240 can be doped with an N-type dopant, such as phosphorus, arsenic, or a combination thereof. After implantation, one or more annealing processes are performed to activate the dopant.

The precursor 200 also includes a gate stack 250. The gate stack 250 includes a flat portion parallel to the surface of the substrate 210 and a gate surface overlying the intermediate portion of the core structure 220. This flat portion can be asymmetrical to the core structure 220. In the present embodiment, the top of the core structure 220 having the third height (h3) is not covered by the gate surface. In an embodiment, the gate of the raised plane gate stack 250 The surface overlaps with a portion of the raised bungee region 240. The gate surface has a third width (w3) and the gate stack 250 has a total width which is a fourth width (w4). This fourth width (w4) is substantially greater than the first width (w1) of the core structure 220, and the fourth width is substantially smaller than the second width (w2) of the drain region 240.

The gate stack 250 can be formed by a process including deposition, photolithographic patterning, and etching. The deposition process includes chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), organometallic chemical vapor deposition (MOCVD), other suitable methods, and/or combinations thereof. The photolithography patterning process includes photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as hard baking), Other suitable processes and/or combinations thereof. The etching process includes dry etching, wet etching, or a combination thereof.

In one embodiment, the gate stack 250 is a high dielectric constant (HK) / metal gate (MG). The high dielectric constant/metal gate includes a gate dielectric layer 255 and a metal gate 256. The gate dielectric layer 255 can include an interfacial layer (IL) and a high-k dielectric layer. The interfacial layer (IL) includes oxides, HfSiO, and nitrogen oxides. The high-k dielectric layer may include LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO. , HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , Si ₃ N ₄ , cerium oxynitride (SiON) and other suitable materials. The metal gate 256 may comprise a single layer or a multilayer structure such as a metal layer, a liner layer, a wetting layer, and an adhesion layer. Metal gate 256 may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, and other suitable materials.

In another embodiment, the gate stack 250 is a polysilicon gate stack Stack. The polysilicon gate stack can include a gate dielectric layer and a polysilicon layer disposed on the gate dielectric layer. The gate dielectric layer includes tantalum oxide, tantalum nitride or any other suitable material.

The precursor 200 also includes an isolation dielectric layer 260 disposed on the substrate 210 including the flat portion of the gate stack 250 and the drain region 240. The isolating dielectric layer 260 includes tantalum oxide, tantalum nitride, tantalum carbide, niobium oxynitride or other suitable materials. The isolation dielectric layer 260 includes a multilayer structure. The isolation dielectric layer 260 can be formed using a deposition and etch process.

Referring to Figures 1 and 3, after the precursor 200 is obtained, the method 100 proceeds to step 104 to form a sidewall spacer 310 having a fifth width (w5) disposed along the top sidewall of the core structure 220. The top of the structure 220 includes a gate surface of the core structure 220 and a portion above the isolation dielectric layer 260. In an embodiment, the fifth width is substantially greater than the third width. The sidewall spacers 310 can include a dielectric material such as tantalum nitride. Additionally, the sidewall spacers 310 may include hafnium oxide, tantalum carbide, niobium oxynitride, or a combination thereof. In one embodiment, the material of the sidewall spacers 310 is selected to have substantially etch selective material with respect to the isolation dielectric layer 260 in subsequent contact etches, which will be described in detail later. The sidewall spacers 310 can be formed using deposition and etching processes. For example, an anisotropic dry etch is performed after the deposition process to form sidewall spacers 310.

Referring to FIGS. 1 and 4, the method 100 proceeds to step 106 to form a source region 410 having a sixth width (w6) at the top of the core structure, the top portion of the core structure including the gate surface overlapping the gate stack 250. Part. The doping profile of the source region 410 is different from the drain region 240. In an embodiment, the hard mask is removed Thereafter, the source region 410 is formed by photolithography patterning, implantation, and annealing processes. In this embodiment, the sixth width is approximately equal to the first width. In another embodiment, after the hard mask 215 is removed, the core structure 220 is etched, and then the source region 410 is formed by the photolithography patterning, implantation, and annealing process on the etched core structure 220. top. In another embodiment, the semiconductor material is epitaxially grown on the etched core structure 220. In this embodiment, the sixth width may be different from the first width. The semiconductor material layer includes an elemental semiconductor material such as germanium (Ge) or germanium (Si); or a compound semiconductor material such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs); or a semiconductor alloy such as germanium telluride (SiGe), phosphorus gallium arsenide (GaAsP). The epitaxial process includes chemical vapor deposition techniques (eg, vapor phase epitaxy (VPE) and/or ultra high vacuum vapor phase epitaxy (UHV-VPE)), molecular beam epitaxy, and/or other suitable processes. The source region 410 can be field doped during the epitaxial process. In an embodiment, the source region 410 is not doped in the field, but is doped with a source process region (eg, a bonding process).

Referring to FIGS. 1 and 5, method 100 proceeds to step 108 to form source contact 510, gate contact 520, and drain contact 530. The dielectric layer 505 is disposed on the isolation dielectric layer 260, including a portion above the source region 410. Dielectric layer 505 is similar in many respects to isolation dielectric layer 260 of Figure 2 above. In the present embodiment, the dielectric layer 505 is selected to have an etch selectivity with respect to the sidewall spacers 310 in the contact etch. Further, the upper surface of the dielectric layer 505 is smoothed by a chemical mechanical polishing process.

Contacts 510, 520, and 530 can be formed using a lithography patterning and etching process. The photolithography patterning process includes photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as hard baking), Other suitable processes and/or combinations thereof. In this embodiment, Source contact 510 is patterned and has an enlarged critical dimension that is a seventh width (w7). This seventh width (w7) is substantially greater than the sixth width (w6) of the source region 410. For example, the seventh width is designed to be the sixth width plus a multiple of the overlap limit of the contact photo lithography. The enlarged source contact critical dimensions not only relax the limitations of the contact lithography technology, but also provide a misalignment-immune-like source contact.

The etching process includes dry etching, wet etching, or a combination thereof. The dry etching process may use a fluorine-containing gas (for example, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF _{3 ,} and/or C ₂ F ₆ ), a chlorine-containing gas (for example, Cl ₂ , CHCl ₃ , CCl _{4 ,} and/or BCl _{3 ).} ), a bromine containing gas (eg, HBr and/or CHBr ₃ ), an iodine containing gas, other suitable gases and/or plasmas, and/or combinations thereof. The etch process can include a multi-step process to achieve etch selectivity, flexibility, and to achieve the desired etch profile. In this embodiment, the contact etch has a suitable selectivity for sidewall spacers 310 in connection with the selection of the isolation dielectric layer 260, sidewall spacers 310, and dielectric layer 505 materials. Therefore, in the contact etch, the source contact 510 has a characteristic similar to the auto-alignment etch, which can improve the process capability of preventing the source-gate short circuit caused by over-etching. In an embodiment, the gate contact 520 is formed on a flat portion of the gate stack 250.

The tunneling field effect transistor device 600 can be formed into various known components and regions by further complementary MOS or MOS technology. For example, subsequent processes may form various vias/lines and multilayer interconnect elements (eg, metal layers and interlayer dielectric layers) on substrate 210 to bond the various components or structures of tunneling field effect transistor device 600. For example, multilayer interconnects include vertical interconnects such as conventional vias and contacts; horizontal interconnects such as metal lines. Different interconnecting elements can use various conductive materials including copper, tungsten, and/or metal telluride.

Additional processes may be added before, during or after method 100. Some of the above described processes may be replaced, omitted, or moved to accommodate embodiments of other methods 100.

In light of the above, the present invention provides an upright tunneling field effect transistor device having a source contact that is amplified and similar to self-alignment and a method of fabricating the same. Amplified and similarly self-aligned source contacts provide an elastic contact photolithography process, misalignment-immune-like source contact resistance, and improved source-gate Short circuit process margin.

The foregoing text sets forth the features of the various embodiments of the invention, and the various aspects of the invention may be better understood by those of ordinary skill in the art. It should be understood by those of ordinary skill in the art that they can readily design or modify other processes and structures based on the present invention and achieve the same objectives and/or achieve the same embodiments as the presently described embodiments. The advantages. For example, source and drain regions are often interchanged depending on the actual application and circuit design of the transistor, and modified or interchanged by appropriate process steps. Therefore, under the above conditions, the terms of source and drain are considered interchangeable. Those of ordinary skill in the art should also understand that such equivalent structures do not depart from the spirit and scope of the invention. The invention may be varied, substituted, and modified without departing from the spirit and scope of the invention.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

210‧‧‧Base

220‧‧‧Frustum-conical protruding structure

230‧‧‧Isolation components

240‧‧‧Bungee Area

250‧‧‧gate stacking

255‧‧‧gate dielectric layer

256‧‧‧Metal gate

260‧‧‧Isolated dielectric layer

310‧‧‧ sidewall spacers

410‧‧‧ source area

505‧‧‧ dielectric layer

510‧‧‧ source contact

520‧‧‧gate contacts

530‧‧‧汲pole contacts

600‧‧‧ Tunneling field effect transistor device

W1, w2, w3, w4, w5, w6, w7‧‧‧ width

H1, h2‧‧‧ height

Claims (10)

A semiconductor device comprising: a precursor, the precursor comprising: a substrate; a frustoconical protruding structure disposed on the substrate and protruding from a plane of the substrate; a gate stack disposed on the substrate The gate stack has a flat portion parallel to the surface of the substrate and a gate surface encased in an intermediate portion of the frustoconical projecting structure; and an isolation dielectric layer disposed on the gate Between the flat portion of the stack and the substrate; a source region disposed on top of the frustoconical projecting structure, the top portion of the frustoconical projecting structure including the gate surface stacked with the gate electrode a portion of the sidewall portion is disposed along the sidewall of the source region and is disposed on the surface of the gate and connected to the isolation dielectric layer; a dielectric layer is disposed on the source region; a source contact having a critical dimension substantially larger than a width of the source region and formed on the source region and extending to the sidewall spacer; and a gate contact disposed at the gate contact a flat portion of the gate stack, wherein the gate contact passes through the isolation interface Layer and directly contacts the gate stack. The semiconductor device of claim 1, wherein the material of the sidewall spacer has a suitable anti-etching when the source contact is formed. And wherein the sidewall spacer comprises tantalum nitride, and the dielectric layer and the isolation dielectric layer comprise tantalum oxide. The semiconductor device of claim 1, wherein the critical dimension of the source contact is equivalent to the width of the source region plus the overlap limit of a contact lithography. The semiconductor device of claim 1, wherein the precursor further comprises: a drain region disposed on the substrate adjacent to the frustoconical projecting structure and extending to the frustoconical projection The bottom of the structure becomes a raised bungee region; and an isolation element is disposed between the respective drain regions. The semiconductor device of claim 4, wherein the gate surface of the gate stack overlaps the bumped drain region. The semiconductor device of claim 1, wherein the gate stack comprises a polysilicon gate or a high dielectric constant/metal gate. The semiconductor device according to claim 1, wherein the frustoconical convex structure comprises: a cylindrical structure; a square columnar structure; an elliptical cylindrical structure; or a hexagonal columnar structure. The semiconductor device of claim 1, further comprising: a drain contact disposed in the drain region. A method of fabricating a semiconductor device, comprising: Providing a precursor, the precursor comprising: a substrate; a frustoconical protruding structure disposed on the substrate and protruding from a plane of the substrate; a drain region disposed on the substrate and adjacent to the truncation a conical protruding structure extending to the bottom of the frustoconical protruding structure to form a raised bungee region; an isolating member disposed between each of the drain regions; and a gate stack disposed on the substrate Wherein the gate stack has a flat portion parallel to the surface of the substrate and a gate surface encased in an intermediate portion of the frustoconical projecting structure, the intermediate portion of the frustoconical projecting structure including a portion of the drain region overlapping; and an isolation dielectric layer disposed between the flat portion of the gate stack and the drain region; forming a sidewall spacer along the frustoconical a top sidewall of the protruding structure is disposed on the gate surface of the gate stack and connected to the isolation dielectric layer; forming a source region on top of the protruding structure, wherein the source region is doped The type is different from the drain region; depositing a dielectric layer in the source region The gate stack and the drain region; and selectively etching the dielectric layer and the isolation dielectric layer to form a source contact in the source region and the sidewall spacer, a gate a pole contact is formed on the flat portion of the gate stack and a drain contact is in the drain region, wherein The critical dimension of the source contact is substantially greater than the width of the source region, wherein the gate contact passes through the isolation dielectric layer and directly contacts the gate stack. The method of fabricating a semiconductor device according to claim 9, wherein the material of the sidewall spacer has a suitable etch resistance when the contact is etched.