JP2010085232A - Testing system and testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a testing system and a testing method, capable of testing a plurality of semiconductor devices stably in parallel, without causing the circuit size of the semiconductor devices to increase. <P>SOLUTION: The testing system 101 includes a reference potential measuring circuit 41 for measuring the reference potential level of one or plural reference semiconductor devices 1, each being a portion of the plurality of the semiconductor devices 1; a power source voltage supply circuit 42 for supplying a common power source voltage to the plurality of the semiconductor devices 1, based on the measured level; and a plurality of reference potential control circuits which are disposed so as to correspond to the semiconductor devices 1, detect the reference potential levels of the corresponding semiconductor devices 1, and control the reference potential levels to be a common prescribed value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a test apparatus and a test method, and more particularly to a test apparatus and a test method for testing a plurality of devices to be tested.

2. Description of the Related Art A test apparatus has been developed in which a plurality of test target semiconductor devices (DUT: Device Under Test) are detachably mounted via sockets and the like and a test is performed in parallel. For example, Patent Document 1 discloses a semiconductor device that can appropriately perform a defect detection test such as a burn-in test.
JP 2007-213706 A

  By the way, in the test apparatus as described above, the common power supply voltage is applied from the test apparatus to each DUT, thereby testing the electrical characteristics of each DUT in parallel. Here, when there is a deviation in the reference potential of each DUT mounted on the test apparatus, the power supply voltage at each DUT is different even though a common power supply voltage is applied from the test apparatus. End up. As a result, a normal DUT may be erroneously determined to be defective.

  In order to solve such problems, for example, a configuration in which a circuit for controlling the ground potential is provided inside the semiconductor device is conceivable. However, in such a configuration, when a common power supply voltage is applied to each DUT from one test apparatus, when the electrical characteristics of each DUT are tested in parallel, variations in the power supply voltage in each DUT can be avoided. It is difficult to reduce.

  Furthermore, with such a configuration, the circuit scale of the semiconductor device increases. Further, the range in which the ground potential can be corrected is limited due to the limitation of the internal circuit of the semiconductor device.

  Therefore, an object of the present invention is to provide a test apparatus and a test method capable of stably testing a plurality of semiconductor devices in parallel without increasing the circuit scale of the semiconductor device.

  In summary, the test apparatus according to the embodiment of the present invention measures the reference potential level of the reference semiconductor device. The power supply voltage supply circuit supplies a common power supply voltage to the plurality of semiconductor devices based on the measured reference potential level. The reference potential control circuit is provided corresponding to each semiconductor device, detects the reference potential level of the corresponding semiconductor device, and controls the reference potential level to a common predetermined value.

  In summary, a test method according to an embodiment of the present invention includes a step of detecting a reference potential level of each semiconductor device and controlling the reference potential level of each semiconductor device to a common predetermined value, and a plurality of semiconductor devices Measuring a reference potential level of one or a plurality of reference semiconductor devices that are a part of the reference semiconductor device, and supplying a common power supply voltage to the plurality of semiconductor devices based on the measured level.

  According to the embodiment of the present invention, the reference potential level of each semiconductor device is controlled to be a common predetermined value. Therefore, a plurality of semiconductor devices can be stably tested in parallel without increasing the circuit scale of the semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

FIG. 1 is an external view showing an overall schematic configuration of a test apparatus according to an embodiment of the present invention.
With reference to FIG. 1, a test apparatus 101 includes a tester body 51, a test head 52, and cables 8 to 10. The test head 52 includes a plurality of interface boards 3 and a plurality of pin cards 6 and 7.

  The pin cards 6 and 7 have an interface function between the tester main body 51 and the DUT 1 mounted on the interface board 3. For example, the pin cards 6 and 7 include a relay that switches between conduction and non-conduction of a signal path between the tester main body 51 and the interface board 3.

  2 is a diagram schematically showing a II-II cross section in FIG. 1 of the test apparatus according to the embodiment of the present invention. FIG. 2 shows a schematic cross section of the test apparatus according to the embodiment of the present invention viewed from the direction A shown in FIG.

  Referring to FIG. 2, tester body 51 includes a reference potential measurement circuit 41 and a power supply voltage supply circuit 42. The test head 52 includes sockets 2A, 2B, 2C, 2D, interface boards 3A, 3B, 3C, 3D, ground plates 4A, 4B, 4C, 4D, screws 5A, 5B, 5C, 5D, and a pin card 6A. , 6B, 6C, 6D, 7A, 7B, 7C, 7D, motherboard 11, cables 12A, 12B, 12D, and module boards 53A, 53B, 53C, 53D.

  In the embodiment of the present invention, each of the DUTs 1A, 1B, 1C, and 1D may be referred to as DUT1. Moreover, each of socket 2A, 2B, 2C, 2D may be called the socket 2. Each of the interface boards 3A, 3B, 3C, 3D may be referred to as an interface board 3. In addition, each of the ground plates 4A, 4B, 4C, and 4D may be referred to as a ground plate 4. Each of the screws 5A, 5B, 5C, and 5D may be referred to as a screw 5. In addition, each of the pin cards 6A, 6B, 6C, 6D may be referred to as a pin card 6. In addition, each of the pin cards 7A, 7B, 7C, and 7D may be referred to as a pin card 7. Each of the cables 12A, 12B, and 12D may be referred to as a cable 12. Each of the module boards 53A, 53B, 53C, and 53D may be referred to as a module board 53.

  In the test apparatus according to the embodiment of the present invention, at least one of the DUTs 1A, 1B, 1C, and 1D is set as the reference DUT. Here, description will be made assuming that DUT 1C is the reference DUT.

  The socket 2 is provided corresponding to the interface board 3 and mounted on the corresponding interface board 3. A corresponding DUT 1 is detachably attached to the interface board 3 by a socket 2.

  The cables 12A, 12B, and 12D electrically connect the reference potential node of the reference DUT 1C and the reference potential control circuit 61 corresponding to the DUTs 1A, 1B, and 1D other than the reference DUT 1C, that is, the module substrates 53A, 53B, and 53D.

  The cable 9 electrically connects the interface board 3C corresponding to the reference DUT 1C and the reference potential measurement circuit 41 in the tester body 51.

  The reference potential measurement circuit 41 measures the level of the reference potential HGND of the reference DUT 1C via the cable 9.

  The power supply voltage supply circuit 42 supplies a common power supply voltage to the DUTs 1A, 1B, 1C, and 1D via the cables 8A, 8B, 8C, and 8D based on the level of the reference potential HGND measured by the reference potential measurement circuit 41. . Thereby, the power supply voltage supplied to each DUT 1 is made uniform. Each of the cables 8A, 8B, 8C, and 8D includes a power supply voltage line and a ground line that is paired with the power supply voltage line.

  The ground plates 4A, 4B, 4C and 4D are provided independently, and the ground layers of the interface boards 3A, 3B, 3C and 3D are connected to the ground plate 4A via corresponding screws 5A, 5B, 5C and 5D. , 4B, 4C, 4D.

  FIG. 3 is a diagram showing a configuration of the module substrate in the test apparatus according to the embodiment of the present invention.

  With reference to FIG. 3, the module substrate 53 includes a substrate 31, a connector 32, and an electronic component 33. The board 31 is attached to the interface board 3 via the connector 32. A reference potential control circuit 61 is formed by the substrate 31 and the electronic component 33.

  FIG. 4 is a circuit diagram of the reference potential control circuit of the module substrate in the test apparatus according to the embodiment of the present invention.

  Referring to FIG. 4, reference potential control circuit 61 includes resistors R1 to R3, detection circuit SN1, comparison circuit CMP1, and D / A converter DAC1.

  The reference potential control circuit 61 detects the reference potential level of the corresponding DUT 1 and controls the reference potential level to a common predetermined value.

  For example, the reference potential control circuit 61 corresponding to the reference DUT1C controls the level of the reference potential HGND of the reference DUT1C so as to be a predetermined level. Then, the reference potential control circuits 61 corresponding to the DUTs 1A, 1B, and 1D other than the reference DUT 1C correspond to the DUTs 1A, 1B, and 1D corresponding to the reference potential HGND level of the reference DUT 1C transmitted by the cables 12A, 12B, and 12D. To control the reference potential level.

  The reference potential control circuit 61 detects and controls the reference potential level of the corresponding DUT 1 via the connector 32, the interface board 3, and the socket 2.

  More specifically, the detection circuit SN1 detects the reference potential level of the corresponding DUT1. For example, the reference potential level immediately below the socket 2 to which the DUT 1 is attached is detected.

  The correction voltage output circuit DAC1 outputs a level correction voltage to one input terminal of the comparison circuit CMP1.

  The comparison circuit CMP1 detects the difference between the level correction voltage at one input terminal and the level of the reference potential HGND at the other input terminal and changes the value of the output voltage so that this difference becomes zero. A feedback loop is formed by feeding back the output voltage of the comparison circuit CMP1 to the detection circuit SN1, and the reference potential level of the corresponding DUT1 is controlled to approach the level of the reference potential HGND of the reference DUT1C.

  FIG. 5 is a flowchart defining an operation procedure when the test apparatus according to the embodiment of the present invention tests a semiconductor device.

  Referring to FIG. 5, first, reference potential control circuit 61 detects the reference potential level of corresponding DUT 1 (step S1), and controls this reference potential level to a common predetermined value (step S2).

  Next, the reference potential measurement circuit 41 measures the level of the reference potential HGND of the reference DUT 1C via the cable 9 (step S3).

  Next, the power supply voltage supply circuit 42 uses the power supply voltage common to the DUTs 1A, 1B, 1C, and 1D via the cables 8A, 8B, 8C, and 8D based on the level of the reference potential HGND measured by the reference potential measurement circuit 41. Is supplied (step S4).

  FIG. 6 is a diagram showing a schematic cross section of the test apparatus according to the embodiment of the present invention viewed from the B direction shown in FIG.

  Referring to FIG. 6, in test head 52, a plurality of ground plates 24 are provided below pin cards 6 and 7, and these are connected to each other by cables or the like. At least one of the ground plates 24 is connected to the ground of the tester body 51 via the cable 10.

  Thus, in the test head 52, since each ground plate is connected by a cable or the like, the cable or the like has a high resistance, and a potential difference occurs between the ground plates. As a result, the potentials of the ground layers of the interface boards 3A, 3B, 3C, 3D vary.

  Furthermore, even if the ground plate 24 is formed of a common plate, the ground layers of the interface boards 3A, 3B, 3C, 3D are connected to the ground plates 4A, 4B, 4D via the corresponding screws 5A, 5B, 5C, 5D. Since it is only connected to 4C and 4D, a potential difference is generated between the ground plates 4, and the potentials of the ground layers of the interface boards 3A, 3B, 3C, and 3D vary.

  FIG. 7 shows that the ground potential (reference potential) varies between the tester body 51 and each DUT 1 when it is assumed that the test apparatus according to the embodiment of the present invention has a configuration without the reference potential control circuit. FIG. FIG. 7 shows a case where DUTB is a reference DUT among eight DUTA, DUTB, DUTC, DUTD, DUTE, DUTF, DUTG, and DUTH.

  Referring to FIG. 7, when the test apparatus 101 does not include the reference potential control circuit 61, the ground potential varies among the DUTs for the reasons described above. That is, the reference potentials of DUTA, DUTB, DUTC, DUTD, DUTE, DUTF, DUTG, and DUTH are −0.12 mV, 0.00 mV, 0.49 mV, 1.40 mV, 14.17 mV, 13.95 mV, respectively. 13.61 mV and 13.05 mV.

  For this reason, even if the power supply voltage supply circuit 42 supplies, for example, a power supply voltage of 2.50 V to each DUT in common, a power supply voltage of 2.5 V is supplied to the DUTB, but 2 to each DUT other than the DUTB. A power supply voltage different from .5V is supplied. In the example shown in FIG. 7, the power supply voltages of DUTE, DUTF, DUTG, and DUTH are particularly far from 2.5V.

  However, the test apparatus according to the embodiment of the present invention includes the reference potential control circuit 61. That is, the reference potential control circuit 61 corresponding to the DUTs 1A, 1B, and 1D other than the reference DUT 1C is set to the level of the reference potential HGND of the reference DUT 1C transmitted by the cables 12A, 12B, and 12D. To control the reference potential level. Then, the reference potential measurement circuit 41 measures the level of the reference potential HGND of the reference DUT 1C via the cable 9. The power supply voltage supply circuit 42 supplies a common power supply voltage to the DUTs 1A, 1B, 1C, and 1D via the cables 8A, 8B, 8C, and 8D based on the level of the reference potential HGND measured by the reference potential measurement circuit 41. .

  With such a configuration, an error from the set value of the voltage applied to the DUT can be reduced, so that the DUT can be tested under correct conditions. Further, even when the applied potential is different among the plurality of DUTs, the difference between the DUTs can be controlled to be smaller than that in the conventional case. Further, since the test can be performed with a more correct applied voltage, the yield is improved.

  Therefore, the test apparatus according to the embodiment of the present invention can stably test a plurality of semiconductor devices in parallel without increasing the circuit scale of the semiconductor device.

  The test apparatus according to the embodiment of the present invention is packaged by a test (wafer test) performed in a state where a semiconductor chip is mounted on a silicon wafer, a semiconductor chip on the silicon wafer being diced, or the like. The present invention can be applied to a test performed in a state (final test), a high-temperature operation test (burn-in test) in which a higher external power supply voltage is supplied to the device than during normal operation, and the like.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is an external view which shows the whole schematic structure of the test apparatus which concerns on embodiment of this invention. It is a figure which shows schematically the II-II cross section in FIG. 1 of the test apparatus which concerns on embodiment of this invention. It is a figure which shows the structure of the module board | substrate in the test apparatus which concerns on embodiment of this invention. It is a circuit diagram of the reference potential control circuit of the module substrate in the test apparatus according to the embodiment of the present invention. 6 is a flowchart defining an operation procedure when the test apparatus according to the embodiment of the present invention tests a semiconductor device. It is a figure which shows the schematic cross section of the test apparatus which concerns on embodiment of this invention seen from the B direction shown in FIG. An example in which the ground potential (reference potential) varies between the tester body 51 and each DUT 1 on the assumption that the test apparatus according to the embodiment of the present invention has a configuration not including the reference potential control circuit is shown. FIG.

Explanation of symbols

  2A, 2B, 2C, 2D socket, 3, 3A, 3B, 3C, 3D interface board, 4A, 4B, 4C, 4D ground plate, 5A, 5B, 5C, 5D screw, 6, 7, 6A, 6B, 6C, 6D, 7A, 7B, 7C, 7D pin card, 8-10 cable, 11 motherboard, 12A, 12B, 12D cable, 24 ground plate, 31 board, 32 connector, 33 electronic component, 41 reference potential measurement circuit, 42 power supply voltage Supply circuit, 51 tester main body, 52 test head, 53A, 53B, 53C, 53D module substrate, 61 reference potential control circuit, 101 test device, R1 to R3 resistors, SN1 detection circuit, CMP1 comparison circuit, DAC1 D / A converter.

Claims (4)

A test apparatus for testing a plurality of semiconductor devices,
A reference potential measuring circuit for measuring a reference potential level of one or more reference semiconductor devices that are part of the plurality of semiconductor devices;
A power supply voltage supply circuit for supplying a common power supply voltage to the plurality of semiconductor devices based on the measured level;
A test apparatus comprising a plurality of reference potential control circuits provided corresponding to the semiconductor device, detecting a reference potential level of the corresponding semiconductor device, and controlling the reference potential level to a common predetermined value. The test device comprises:
A cable for electrically connecting a reference potential node of the reference semiconductor device and the reference potential control circuit corresponding to the semiconductor device other than the reference semiconductor device;
The reference potential control circuit corresponding to the semiconductor device other than the reference semiconductor device controls a reference potential level of the corresponding semiconductor device so as to be a reference potential level of the reference semiconductor device transmitted by the cable. Item 2. The test apparatus according to Item 1. The test apparatus further includes:
A plurality of interface boards provided corresponding to the semiconductor device, to which the corresponding semiconductor device is detachably mounted;
Each of the reference potential control circuits is mounted on the corresponding interface board, and detects and controls the reference potential level of the corresponding semiconductor device via the interface board.
The test apparatus further includes:
A cable for electrically connecting the interface board corresponding to the reference semiconductor device and the reference potential measurement circuit;
The test apparatus according to claim 1, wherein the reference potential measurement circuit measures a reference potential level of the reference semiconductor device via the cable. A test method for testing a plurality of semiconductor devices,
Detecting a reference potential level of each of the semiconductor devices and controlling the reference potential level of each of the semiconductor devices to a common predetermined value;
Measuring a reference potential level of one or more reference semiconductor devices that are part of the plurality of semiconductor devices;
Supplying a common power supply voltage to the plurality of semiconductor devices based on the measured level.

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