JP2010081202A - Gain control circuit and class d power amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gain control circuit and a class D power amplifier circuit, which are stably applied for gain control and wide-range voltage sources. <P>SOLUTION: The gain control circuit 100 includes a signal input terminal 102 in which an analog input signal is input, a calculation amplifier 108 which amplifies analog signal to be supplied with a voltage source E1, and a first T-type resistance circuit T123 which is connected between an inversion input terminal 108a of the calculation amplifier 108 and an output terminal 108c. A first variable resistor RV1 for gain control is connected between the signal input terminal 102 and the inversion input terminal 108a. A DC bias voltage is supplied to a non-inversion input terminal 108b of the calculation amplifier 108 from a bias voltage supply circuit 130. The bias voltage supply circuit 130 includes a first voltage generation circuit 132 and a second bias voltage generation circuit 138. The first bias voltage generation circuit 132 includes a second voltage source E2 and a second T-type resistance circuit T123a. The second bias voltage generation circuit 138 includes a third voltage source E3 and a second variable resistor RV2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a gain adjustment circuit and a class D power amplifier. The gain adjustment circuit adjusts a voltage gain using a variable resistor on the input side of an operational amplifier, and the class D power amplifier includes the gain adjustment circuit. The present invention relates to a TV device, a personal computer, an AV receiver, a car audio, and the like.

An operational amplifier is often used for a gain adjustment circuit. It is well known to use a negative feedback circuit for an operational amplifier. Among the power amplifiers, the class D power amplifier converts an analog signal into a pulse signal whose pulse width changes with time (this is called PWM: Pulse Modulation Width), and the power transistor is turned on / off by the pulse signal. Then, the signal output from the power transistor is integrated by a low-pass filter to drive the speaker. Since the class D power amplifier has a relatively high efficiency, it is often used for a relatively low power type driven by a battery or the like. The negative feedback circuit is also used in the class D power amplifier to reduce the distortion of the entire circuit.

Patent Document 1 (FIGS. 2 and 7) shows a power amplifier using a negative feedback circuit formed of a so-called T-type resistor circuit. Patent Document 1 discloses that if a T-type resistor circuit is used in a negative feedback circuit of an operational amplifier, a high voltage gain can be obtained compared to a circuit configuration not using the operational amplifier, and a negative feedback circuit for obtaining the same voltage gain. It is taught that the total resistance value required for the circuit can be reduced, and is therefore suitable for integration. Further, if a resistor of the same order is formed in the T-type resistor circuit by integrated circuit technology, the variation in voltage gain can be suppressed to be small, which is suitable for mass production.

Patent document 2 shows what used the operational amplifier as a variable amplifier circuit. When the operational amplifier is used in a gain adjustment circuit, for example, the voltage gain is controlled, the resistance value on the input side of the operational amplifier or the resistance value of the negative feedback circuit is generally adjusted. When the electronic volume is connected to the inverting input terminal or the non-inverting input terminal of the operational amplifier and the voltage gain is adjusted by changing the resistance value of the electronic volume, as described in Patent Document 2 and Paragraph 2 As a result, not only the AC signal but also the DC offset voltage changes depending on the voltage gain. However, the output of the variable amplifier circuit using the volume needs to be held at, for example, a voltage half that of the power supply voltage VDD, that is, VDD / 2, without changing the DC offset voltage. Patent Document 2 proposes a variable amplifier circuit that eliminates fluctuations of the DC offset voltage in order to maintain the offset voltage at a constant voltage, that is, ½ of the power supply voltage.

Referring to Patent Document 2 and FIG. 1, an output [G of a first electronic volume EV1 that outputs a voltage gain G voltage using a signal (Vi = v + V) in which a DC offset voltage V is superimposed on an AC signal v as an input signal. (V + V)] and the output signal (Vo = −Gv + V) of the output signal (Vo = −Gv + V) by adding and subtracting only the DC offset voltage V as an input signal and the output GV of the second electronic volume EV2 that outputs the same voltage gain G voltage. A variable amplifying circuit including an addition / subtraction circuit that cancels a change in the offset voltage V is shown. The first electronic volume EV1 and the second electronic volume EV2 are interlocked so that even if the voltage gain G changes, the DC offset voltage V also changes accordingly and the DC offset voltage V remains at the constant voltage VDD / 2. Hold.

Patent Document 3 discloses a gain adjustment circuit composed of a so-called switched capacitor. For example, referring to FIG. 1, the input signal Ein is input to the inverting input terminal of the operational amplifier 5 via the equivalent resistor 3, and the equivalent resistance R2 is provided between the output terminal Eout and the inverting input terminal of the operational amplifier 5. Are connected, and the equivalent resistors R1 and R2 are driven by the divided clock signals φ1, φ2 and φ3, φ4 from the frequency dividing circuit 2, respectively. The frequency divider 2 operates according to the oscillator 1 and the constant (M, N) input device 7. That is, the gain adjustment circuit disclosed in Patent Document 3 uses equivalent resistances R1 and R2 by switched capacitors without using a resistance which is a passive element.

Patent Document 4 discloses a pulse width modulation amplifier circuit used for an audio signal reproducing device or the like. Patent Document 4 suggests not only a narrow-sense pulse width modulation amplifier circuit but also a broad-sense pulse width modulation amplifier circuit, that is, a class D power amplifier. Referring to Patent Document 4 and FIG. 1, the pulse width modulation amplifier has a preamplifier (so-called preamplifier) and a modulation circuit, and an operational amplifier is used for the preamplifier provided in the previous stage of the modulation circuit, and the input side of the operational amplifier is The voltage gain is adjusted by changing the resistance value. That is, Patent Document 4 shows a gain adjustment circuit provided on the input side of an operational amplifier.

Patent Document 5 shows a class D power amplifier. Referring to Patent Document 5 and FIG. 1, binary state modulation means for converting an analog signal into a digital signal, pulse power amplification means for power amplification of the output of the binary state modulation means, and low pass for band limiting the output of the power amplification means Feedback means for feeding back the output of the filter and pulse power amplification means to the binary state modulation means is shown.

Patent Document 6 discloses a so-called self-excited oscillation type PWM modulation system. The self-oscillation type PWM modulation method is a method for outputting a PWM signal that automatically oscillates without using a triangular wave signal. With reference to Patent Document 6 and FIG. 1, the self-excited oscillation type PWM modulation method includes an operational amplifier that automatically generates an oscillation signal. The comparator 11 having hysteresis characteristics generates an oscillation signal.

Patent Document 7 discloses a delta-sigma modulation amplifier. The delta sigma modulation amplifier shown in FIG. 1 includes an input terminal 1, a differential amplifier 2, a 1-bit quantizer 3, a delay device 4, a clock oscillator 5, a pulse amplifier 6, a low-pass filter 7, and an output terminal 8.

JP-A-51-77159 JP-A-5-55848 JP 2000-1114896 A JP-A-4-43706 Japanese Unexamined Patent Publication No. 7-231226 JP 2003-115730 A JP-A-5-63457

However, when the operational amplifier is used in a variable amplification circuit, that is, a gain adjustment circuit, there arises a problem that the DC offset voltage changes as taught in Patent Document 2. For this reason, as shown in Patent Document 4, when the gain adjustment circuit is configured by an operational amplifier, for example, at the front stage of the modulation circuit of the class D power amplifier, the offset voltage of the operational amplifier changes according to the gain adjustment. This causes a problem in the circuit operation of the modulation circuit and power amplifier connected to the subsequent stage of the operational amplifier.

An object of the present invention is to provide a gain adjustment circuit that can easily adjust the offset voltage of the operational amplifier and the operating voltage on the input side of the gain adjustment circuit even if the voltage gain and the voltage source are changed in view of the technical idea of each of the above prior arts. provide.

Another object of the present invention is to provide a gain adjustment circuit suitable for integration into an integrated circuit.

Another object of the present invention is to provide a class D power amplifier capable of simplifying the circuit configuration.

Another object of the present invention is to provide a class D power amplifier having a stable circuit operating point regardless of gain adjustment. Another object of the present invention is to provide a voltage source, that is, a class D power amplifier which can take a wide range of application of the power supply voltage.

The gain adjustment circuit of the present invention is
(A) an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal and supplied with a voltage from the first voltage source; (b) one of the inverting input terminal and the non-inverting input terminal; A first T-type resistor circuit connected between the terminal side and constituting a negative feedback circuit. (C) Gain connected between one of the inverting input terminal and the non-inverting input terminal and the signal input terminal. And a bias voltage supply circuit connected to the other input terminal different from the one input terminal to which the first T-type resistor circuit is connected.
Further, the bias voltage supply circuit (d) includes (d1) a first bias voltage generation circuit (d2) having a second T-type resistance circuit and generating a voltage proportional to the magnitude of the second voltage source. A second bias voltage generating circuit (d3) comprising a second variable resistor connected to the voltage source and the third voltage source; and a circuit connection for connecting the first bias voltage generating circuit and the second bias voltage generating circuit. Prepare the body. According to the above configuration, the second T-type resistor circuit can generate a relatively small DC bias voltage even when a relatively high voltage source is used, and this relatively small DC bias voltage can be generated by the operational amplifier. By supplying to the input side, it can be used with a relatively wide range of voltage sources. In addition, since the operating point on the input side of the operational amplifier is controlled and adjusted by the second variable resistor that is linked to the first variable resistor, the operating point on the input side of the operational amplifier is adjusted to an appropriate circuit operation in accordance with the adjustment of the voltage gain. Can be controlled and adjusted to points. Further, since the T-type resistance circuit is used for the negative feedback circuit, the voltage gain of the operational amplifier can be increased. It should be noted that the first and second variable resistors include an equivalent resistor formed of a switched capacitor only with a resistor that is a passive element. In addition, the first and second T-type resistance circuits are not only composed of only the resistance which is a passive element, but also include a resistance circuit composed of an equivalent resistance.

Another gain adjustment circuit of the present invention includes an operational amplifier different from the operational amplifier and the first variable resistor between the signal input terminal and one of the inverting input terminal and the non-inverting input terminal of the operational amplifier. A third voltage source is supplied to one of the non-inverting input terminal and the inverting input terminal of another operational amplifier, and another operational amplifier is provided before the operational amplifier. The voltage gain is adjusted by a first variable resistor provided in the signal path between the arithmetic unit and the operational amplifier. According to such a circuit configuration, the input side of the first variable resistor for adjusting the voltage gain is adjusted to a predetermined DC voltage by the third voltage source and another operational amplifier, so that the operational amplifier provided for the gain adjustment circuit The DC bias voltage on the input side can be suppressed to a predetermined magnitude and a predetermined range.

  In another gain adjustment circuit of the present invention, the first variable resistor and the second variable resistor are interlocked. According to such a configuration, the operating point of the DC voltage of the gain adjusting circuit can be adjusted according to the gain adjustment by the second variable resistor that is linked to the first variable resistor that adjusts the voltage gain.

  Another gain adjustment circuit of the present invention includes a first T-type resistor circuit and a second T-type resistor circuit. The first feedback resistor and the second feedback resistor of the first T-type resistor circuit have a first common connection point connected in series, and one end of the first feedback resistor is on the output terminal side of the operational amplifier, One end of the second feedback resistor is connected to one of the non-inverting input terminal and the inverting input terminal, a third feedback resistor is connected between the first common connection point and the ground terminal, and the first bleeder is connected. The resistor and the second bleeder resistor have a second common connection point connected in series, and one end of the first bleeder resistor and the second bleeder resistor is a second voltage source, an inverting input terminal, and a non-inverting input terminal. The third bleeder resistor is connected between the second common connection point and the ground terminal. According to such a configuration, the negative feedback circuit of the operational amplifier constituting the gain adjustment circuit is controlled to an appropriate circuit operating point by the second T-type resistor circuit that performs the same electrical operation as the first T-type resistor circuit. Can be adjusted.

  According to another gain adjustment circuit of the present invention, the first bleeder resistor R1a has a resistance value 2 · R1 that is twice that of the first feedback resistor R1, and the second bleeder resistor R2a has a second feedback resistor R2 and the second feedback resistor R2. The third bleeder resistance R3a has the same resistance value and is set equal to the resistance of the parallel resistance of the 2 · R1 and the third feedback resistance R3. According to such a configuration, the bias voltage generation circuit can be configured by the first to third bleeder resistors, and the first bleeder resistor can be directly connected to the voltage source. It is not necessary to provide a new bias voltage source for supplying a voltage source to the generation circuit, and the circuit configuration can be simplified.

  In another gain adjustment circuit of the present invention, the first T-type resistor circuit and the second T-type resistor circuit are formed on the same semiconductor chip, and the first feedback resistor, the second feedback resistor, and the third feedback circuit are provided. The resistor, the first bleeder resistor, the second bleeder resistor, and the third bleeder resistor are each composed of a combination of basic resistance patterns. According to such a configuration, since the first and second T-type resistance circuits are configured with basic resistance patterns, the accuracy of the resistance ratio can be increased. As a result, the bias voltage supplied from the bias voltage supply circuit can be set with high accuracy. Further, the operating point of the DC voltage of the negative feedback circuit composed of the first T-type resistor circuit can be set to a predetermined operating point by responding to the operating point of the DC voltage of the second T-type resistor circuit.

The class D power amplifier of the present invention includes a modulation circuit connected to the subsequent stage of the gain adjustment circuit. The gain adjustment circuit
(A1) An operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal and supplied with a voltage from the first voltage source. (B1) One of the inverting input terminal and the non-inverting input terminal and the output. A first T-type resistor circuit (c1) connected between the terminal side and constituting a negative feedback circuit. (C1) A voltage connected between one of the inverting input terminal and the non-inverting input terminal and the signal input terminal. The first variable resistor (d1) for adjusting the gain is connected to the other input terminal different from the one input terminal to which the negative feedback circuit is connected,
A first bias voltage generation circuit having a second T-type resistance circuit and generating a voltage proportional to the size of the second voltage source; and a third voltage source and a third voltage source connected to the third voltage source A second bias voltage generation circuit comprising two variable resistors, a first bias voltage generation circuit, and a second bias voltage generation circuit, one resistor constituting the second T-type resistance circuit and a second variable A bias voltage supply circuit having a circuit connection body connected by a resistor is provided. Further, the modulation circuit connected to the subsequent stage of the gain adjustment circuit is one of a separately excited oscillation type PWM system and a self-excited oscillation type PWM system.
Since the class D power amplifier of the present invention employs a gain adjustment circuit that can be used with a relatively wide range of voltage sources, it can be easily connected to both the separately-excited oscillation type PWM system and the self-excited oscillation type PWM system. Become.

Yet another class D power amplifier of the present invention is:
(A) An operational amplifier having two input terminals and an output terminal of an inverting input terminal and a non-inverting input terminal and supplied with a first voltage source. (B) One input terminal of two input terminals and a signal input terminal. Connected to the output terminal of the first variable resistor (c) operational amplifier for adjusting the voltage gain and connected to the output terminal of the operational amplifier (d) to which the second voltage source is supplied (d) the signal output terminal connected to the modulation circuit ( e) a first T-type resistor circuit which is connected between the signal output terminal and one input terminal of the operational amplifier and constitutes a negative feedback circuit; and (f) connected to the other input terminal of the operational amplifier to supply a bias voltage. A bias voltage supply circuit. The bias voltage supply circuit (f)
(F1) a first bias voltage generation circuit having a second T-type resistance circuit connected to the same second voltage source as the modulation circuit; (f2) generating a voltage smaller than the first and second voltage sources; And a second bias voltage generation circuit (f3) having a second variable resistor connected to the third voltage source, and a circuit connection body for connecting the first and second bias voltage generation circuits. .

According to the above configuration, the second T-type resistor circuit can generate a relatively small DC bias voltage even when a relatively high voltage source is used, and this relatively small DC bias voltage can be generated by the operational amplifier. A gain adjusting circuit that can be used in a relatively wide range of voltage sources can be provided by supplying it to the input side. In addition, since the operating point on the input side of the operational amplifier is controlled and adjusted by the second variable resistor that is linked to the first variable resistor, the operating point on the input side of the operational amplifier is appropriately adjusted in accordance with the adjustment of the voltage gain. It is possible to control and adjust the circuit operation point. Furthermore, since the T-type resistance circuit is used for the negative feedback circuit, the voltage gain of the gain adjustment circuit can be increased. Since the class D power amplifier of the present invention employs a gain adjustment circuit that can be used with a relatively wide range of voltage sources, connection to the gain adjustment circuit is facilitated even if the voltage source used for the modulation circuit is set over a wide range. .

In another class D power amplifier of the present invention, a capacitor is connected between one input terminal and an output terminal of an operational amplifier, and an integrating circuit is configured by the capacitor, the first variable resistor, and the operational amplifier. The operational amplifier has a gain. It also serves as an adjustment circuit and an integration circuit. According to such a configuration, it is not necessary to separately provide the gain adjustment circuit and the integration circuit used for the class D power amplifier, so that it is possible to provide a class D power amplifier that can simplify the circuit configuration.

  A first T-type resistance circuit of another class D power amplifier according to the present invention includes a first feedback resistor, a second feedback resistor, and a third feedback resistor, and the first feedback resistor and the second feedback resistor. Has a first common connection point connected in series, one end of the first feedback resistor is a signal output terminal connected to the modulation circuit, and one end of the second feedback resistor is one input terminal of the operational amplifier And the third feedback resistor is connected between the first common connection point and the ground terminal, and the second T-type resistance circuit includes the first bleeder resistance, the second bleeder resistance, and the third The first bleeder resistor and the second bleeder resistor have a second common connection point connected in series, and one end of the first bleeder resistor is connected to the second voltage source, One end of the bleeder resistor is connected to the other input terminal of the operational amplifier. Over Da resistor is connected between the ground terminal and the second common connection point. According to such a configuration, the negative feedback circuit of the operational amplifier constituting the gain adjustment circuit is controlled to an appropriate circuit operating point by the second T-type resistor circuit that performs the same electrical operation as the first T-type resistor circuit. A class D power amplifier that can be adjusted can be provided.

In another class D power amplifier of the present invention, the resistance value of the first bleeder resistor R1a is 2 · R1, which is twice as large as the first feedback resistor R1, and the resistance value of the second bleeder resistor R2a is It is the same as the second feedback resistor R2, and the resistance value of the third bleeder resistor R3a is a parallel resistance of 2 · R1 twice as large as the first feedback resistor R1 and the third feedback resistor R3. , R3a = (2 · R1) · R3 / (2R1 + R3). According to such a configuration, the bias voltage generation circuit can be configured by the first to third bleeder resistors, and the first bleeder resistor can be directly connected to the voltage source. It is not necessary to provide a new bias voltage source for supplying a voltage source to the circuit, and a class D power amplifier that can simplify the circuit configuration can be provided.

  The gain adjusting circuit of the present invention and the class D power amplifier including the same have first and second T-type resistance circuits, and the first T-type resistance circuit is configured as a negative feedback circuit. The second T-type resistor circuit generates a bias voltage that is responsive to the gain adjustment and the size of the voltage source. The generated bias voltage is supplied to the input side of the operational amplifier constituting the gain adjustment circuit. With such a circuit configuration, the DC operating point of the negative feedback circuit is controlled and adjusted in conjunction with gain adjustment and the size of the voltage source to be used, and the DC voltage at the time of no signal on the output terminal side of the operational amplifier is set to 1 of the voltage source. / 2 can be set.

(First embodiment)
FIG. 1 shows a gain adjustment circuit according to a first embodiment of the present invention. The gain adjustment circuit 100 includes a signal input terminal 102 to which the analog input signal Sin is input, a first variable resistor RV1 that adjusts the voltage gain of the analog signal input to the signal input terminal 102, an inverting input terminal 108a, and a non-inverting input terminal. An operational amplifier 108 having an output terminal 108c, a signal output terminal 120 from which a gain-adjusted signal is output, and a signal output terminal 120 and an inverting input terminal 108a of the operational amplifier 108 are connected to form a negative feedback circuit. A first T-type resistance circuit T123 and a bias voltage supply circuit 130 are provided.

FIG. 1 shows the output terminal 108c of the operational amplifier 108 directly connected to the signal output terminal 120 for convenience of explanation and drawing. However, various other circuits (not shown) may be connected between the output terminal 108c and the signal output terminal 120. Under such a circuit configuration, the first voltage source E1 that supplies the power supply voltage to the operational amplifier 108 and the voltage sources of various other circuits provided with the signal output terminal 120 are often different. The voltage source of another circuit provided with the signal output terminal 120 is generally higher than that used for the operational amplifier 108. For example, the first voltage source E1 supplied to the operational amplifier 108 is 5V, but a voltage source of 10V to 30V is used for the power amplifier provided with the signal output terminal 120, for example. Of course, a voltage source exceeding 30 V may be supplied to a circuit different from the operational amplifier 108. Under such a circuit configuration, a voltage sufficiently higher than the first voltage source E1 supplied to the operational amplifier 108 is output to the signal output terminal 120.

The first T-type resistor circuit T123 includes a first feedback resistor R1, a second feedback resistor R2, and a third feedback resistor R3. These feedback resistors are referred to as T-type resistor circuits because they are arranged in a so-called T-shape. The T-type resistor circuit is composed of three resistors, but in addition to these T-type resistor circuits, Also included is a so-called ladder structure in which a plurality of stages are connected in cascade. The first feedback resistor R1 and the second feedback resistor R2 are connected in series, and the third feedback resistor R3 is connected between the first common connection point M1 and the ground terminal. One end of the first feedback resistor R1 is connected to the signal output terminal 120, and one end of the second feedback resistor R2 is connected to a common connection point between the inverting input terminal 108a of the operational amplifier 108 and the first variable resistor RV1. In general, a T-type resistor circuit is used for the negative feedback circuit of an operational amplifier or a gain adjustment circuit using the same, or the feedback resistors R1 and R2 are combined into one feedback resistor without using the feedback resistor R3. A circuit configuration is also often used.

As taught in Patent Document 1, it is obvious that a high voltage gain can be obtained if a negative feedback circuit composed of a T-type resistance circuit is provided in an operational amplifier. Note that the first T-type resistor circuit T123 constituting the negative feedback circuit may be connected to the non-inverting input terminal 108b instead of the inverting input terminal 108a, and the analog input signal Sin is input to the non-inverting input terminal 108b. It may be. Further, one or several stages of inverters or buffers may be connected between the output terminal 108 c and the signal output terminal 120 of the operational amplifier 108.

The gain adjustment circuit 100 according to the present invention supplies a DC bias voltage from the bias voltage supply circuit 130 to the non-inverting input terminal 108 b of the operational amplifier 108. Note that the non-inverting input terminal 108b and the inverting input terminal 108a may be replaced with each other. The bias voltage supply circuit 130 includes a first bias voltage generation circuit 132 and a second bias voltage generation circuit 138. The first bias voltage generation circuit 132 includes a second T-type resistance circuit T123a and a second voltage source E2. The second T-type resistance circuit T123a has a first bleeder resistance R1a, a second bleeder resistance R2a, and a third bleeder resistance R3a. The phrase “bleeder resistance” is obvious to those skilled in the art. In the present invention, it is used in a generally well-understood meaning. That is, it refers to a resistor prepared for dividing the voltage of the voltage source or the output voltage to a predetermined voltage level. The second T-type resistor circuit T123a has a function of a so-called voltage dividing circuit that divides the second voltage source E2. The DC voltage VM1a at the second common connection point M1a is substantially equal to the voltage obtained by dividing the second voltage source E2 by the first bleeder resistor R1a and the second bleeder resistor R3a. Third bleeder resistance These bleeder resistances are basically the same as the circuit configuration of the first T-type resistance circuit T123 constituting the negative feedback circuit, and resistors having the same resistance value are used. That is, R1a = R1, R2a = R2, and R3a = R3 are set. However, each feedback resistor and each bleeder resistor constituting the first and second T-type resistance circuits are changed to a size having a predetermined relation ratio according to the output voltage to which they are connected and the size of the voltage source. You can also. Alternatively, R1a = R2a and R1a = R2a = R3a may be set.

One end of the first bleeder resistor R1a is connected to the second voltage source E2. The second voltage source E2 is a voltage source supplied to another circuit (not shown) to which the signal output terminal 120 is connected. The second voltage source E2 is generated, for example, to ½ the size based on the first voltage source E1. FIG. 1 illustrates an example in which the output terminal 108 c of the operational amplifier 108 is directly connected to the signal output terminal 120. Under such a circuit configuration, the second voltage source E2 is ½ the voltage source E1 supplied to the operational amplifier 108. This is because the midpoint voltage Vo of the signal output terminal 120 is set to a half of the first voltage source when there is no signal, and considering the operating voltage of the operational amplifier 108, This is because it is necessary to supply substantially the same DC bias voltage to the inverting input terminal 108a and the non-inverting input terminal 108b. However, the setting of the second voltage source E2 does not require any relationship with the size of the first voltage source E1. That is, the second voltage source E2 can be set separately from the first voltage source E1.

In the case where the signal output terminal 120 is provided in a circuit different from the operational amplifier 108, the second voltage source E2 is set to ½ the size of the voltage source supplied to another circuit. That is, the size of the second voltage source E2 is determined according to the size of the voltage source supplied to another circuit (not shown) connected to the subsequent stage of the operational amplifier 108.

The second bleeder resistor R2a constituting the first bias voltage generating circuit 132 is connected in series with the first bleeder resistor R1a, and a third bleeder resistor R3a is connected between the second common connection point M1a and the ground terminal. Connecting. One end of the second bleeder resistor R2a is connected to the second variable resistor RV2 constituting the second bias voltage generation circuit 138 and the non-inverting input terminal 108b of the operational amplifier 108.

The second bias voltage generation circuit 138 includes a third voltage source E3 and a second variable resistor RV2. The second variable resistor RV2 is configured to be interlocked with the variable resistor RV1 for adjusting the voltage gain. The resistance value of the second variable resistor RV2 is selected to be the same as that of the first variable resistor RV1. Therefore, the second variable resistor RV2 is always placed at the same resistance value in conjunction with the first variable resistor RV1. The first variable resistor RV1 and the second variable resistor RV2 may be slidable, that is, the resistance value may be continuously changed, or the resistance value may be changed stepwise. Alternatively, any format such as a so-called electronic volume format that is electronically variable as disclosed in Patent Document 2 may be used. Recently, an electronic volume type has been widely used.

The first variable resistor RV1 and the second variable resistor RV2 according to the present invention can be configured using a switched capacitor without using a resistor itself as a passive element as disclosed in Patent Document 3.

In addition, not only the first variable resistor RV1 and the second variable resistor RV2 but also the first feedback resistor R1, the second feedback resistor R2, and the third feedback are configured to form an equivalent resistor using the switched capacitor. The resistor R3, the first bleeder resistor R1a, the second bleeder resistor R2a, and the third bleeder resistor R3a can be expanded. Of course, at least one of the first variable resistor RV1, the second variable resistor RV2, the first T-type resistor circuit, and the second T-type resistor circuit may be formed of a switched capacitor.

The bias voltage supply circuit 130 according to the present invention includes a first bias voltage generation circuit 132 and a second bias voltage generation circuit 138, and both of these bias voltage generation circuits are configured as a second bleeder resistor R2a. And it connects via the circuit connection body which consists of 2nd variable resistance RV2. In other words, the second bleeder resistor R2a is also one resistor constituting the first bias voltage generation circuit 132, but also has a function of connecting the first bias voltage generation circuit 132 and the second bias voltage generation circuit 138. Hold together. Similarly, the second variable resistor RV2 is also one variable resistor constituting the second bias voltage generation circuit 138, but connects the first bias voltage generation circuit 132 and the second bias voltage generation circuit 138. It also has functions. The “circuit connector” corresponds to a combined resistor R20a shown in FIGS. 4A and 4B described later.

A bias voltage V108b is supplied to the non-inverting input terminal 108b of the operational amplifier 108 through a bias voltage supply point M108 that is a common connection point of the series connection body of the second bleeder resistor R2a and the second variable resistor RV2. An input current i108b flows through the non-inverting input terminal 108b of the operational amplifier 108. However, since the input impedance of the operational amplifier is generally extremely high and is several MΩ or more, the magnitude of the input current i108b can be ignored. Therefore, in the following description, the input currents flowing through the two input terminals of the operational amplifier 108 are ignored and regarded as all zero. If the input current i108b flowing through the non-inverting input terminal 108b is considered to be zero, the bias voltage V108b of the non-inverting input terminal 108b is equal to the second common connection point M1a between the first bleeder resistor R1a and the third bleeder resistor R3a. It is determined by the resistance ratio of the DC voltage VM1a and the third voltage source E3, the second variable resistor RV2, and the second bleeder resistor R2a.

(Second Embodiment)
FIG. 2 is equivalent to the gain adjustment circuit shown in FIG. The detailed reason will be described later. The main points are as follows. That is, the first bias voltage generation circuit 132 is different from FIG. In FIG. 2, the second voltage source E2 is set to the same size as the first voltage source E1. That is, it was set to twice the voltage source shown in FIG. Specifically, one end of the first bleeder resistor R1a is directly connected to the first voltage source E1. The first bleeder resistor R1a is twice as large as the first feedback resistor R1, and the third bleeder resistor R3a is 2 · R1 and twice as large as the third feedback resistor R3. Set to the same size as the parallel resistance. Other circuit configurations and circuit conditions are the same as those in FIG. That is, the bleeder resistance R2a is exactly the same as the feedback resistance R2, and the second bias voltage generation circuit 138 is also exactly the same as that of FIG. In FIG. 2, the symbol “//” indicates that both resistors sandwiching this symbol are connected in parallel. Therefore, the indication “R3a = 2 · R1 // R3” indicates that the third bleeder resistor R3a has a resistance twice as large as the first feedback resistor R1 and the third feedback resistor R3 connected in parallel. Shows the state. These definitions are the same in this document, other drawings, and Table 1 described later. Two symbols “//” arranged side by side indicate that a parallel connection exists. For example, in the display “R1a // R20a // R3a”, a first bleeder resistor R1a and a combined resistor R20a are connected in parallel, and a third bleeder resistor R3a is connected in parallel to the parallel-connected device. Represents that This means that these three resistors are connected in parallel.

The size of the third voltage source E3 is set to 1/2 the size of the first voltage source E1 in order to balance the circuit operating point of the operational amplifier 108. That is, if E1 = 5V, E3 = 2.5V is set. The third voltage source E3 can be generated using, for example, a band gap type constant voltage circuit. The third voltage source E3 is fixed to a magnitude of, for example, 2.5 V so as to be always constant without depending on the first voltage source E1 and the second voltage source E2.

(Third embodiment)
FIG. 3 shows another embodiment of the gain adjustment circuit 100 according to the present invention. In FIG. 2, the operational amplifier 104 is provided between the signal input terminal 102 and the first variable resistor RV1, and the third voltage source E3 is supplied to the inverting input terminal or the non-inverting input terminal of the operational amplifier 104. The difference is that it is supplied via line 136. The operational amplifier 104 can be provided with a function as a buffer or a function of inverting the polarity of the analog input signal Sin without providing a signal amplification function. Further, the operational amplifier 104 can have a mute function under the control of a circuit unit (not shown). That is, by providing the operational amplifier 104 in front of the operational amplifier 108, for example, the analog input signal Sin input to the signal input terminal 102 can be blocked from being input to the first variable resistor RV1 and the operational amplifier 108. it can.

In FIG. 3, for example, when an analog input signal Sin having an amplitude value of 3 V or less is input to the signal input terminal 102, an analog of the same amplitude having the third voltage source E3 as a DC voltage component is provided on the output side of the operational amplifier 104. A signal is output. The output analog output signal is input to the inverting input terminal 108a of the operational amplifier 108 via the first variable resistor RV1. Since other circuit configurations and circuit operations are exactly the same as those in FIG. 2, description thereof will be omitted. In FIG. 2, the DC voltage component of the analog input signal Sin input to the signal input terminal 102 is set to approximately ½ of the power supply voltage E1 of the operational amplifier 108. However, in the circuit configuration shown in FIG. The DC voltage component of the input signal Sin is determined by the third voltage source E3. The third voltage source E3 is half the size of the voltage source E1 that supplies the power supply voltage to the operational amplifier 108. When E1 = 5V, E3 = 2.5V is set. The magnitude of E3 = 2.5V is constant without depending on the first voltage source E1 and the second voltage source E2. In the third embodiment shown in FIG. 3, the DC voltage at one end of the first variable resistor RV1 and the second variable resistor RV2 is fixed to 2.5V by the third voltage source E3.

FIGS. 4A and 4B are obtained by extracting the bias voltage supply circuit 130 shown in FIGS. 1 and 2, but for the sake of explaining that the bias voltage supply circuits 130 of FIGS. 1 and 2 are equivalent to each other. It is deformed. That is, in FIG. 4A and FIG. 4B, the second variable resistor RV2 and the second bleeder resistor R2a are integrated, and these are represented by a combined resistor 20a. 4A and 4B are different from each other in the size of the second voltage source E2 and the sizes of the first bleeder resistor R1a and the third bleeder resistor R3a.

  In FIG. 4A, when the circuit connection body in which the second variable resistor RV2 and the second bleeder resistor R2a are integrated is the combined resistor R20a, and the current i108b flowing through the non-inverting input terminal 108b is regarded as zero, the second T The DC voltage VM1aA at the second common connection point M1aA, which is a common connection point of the three bleeder resistors constituting the mold resistor circuit, can be expressed by the following equation (1) when calculated based on Kirchhoff's law. In Equation 1, the parallel combined resistance value of the three resistors of the first bleeder resistor R1a, the combined resistor R20, and the third bleeder resistor R3a is represented by Ro (A).

(Equation 1)
VM1aA = Ro (A). (E3 / R20a + (E1 / 2) / R1a)

  Further, the bias voltage V108b at the common connection point of the first variable resistor RV2 and the second bleeder resistor R2a is expressed by Equation 2 if the ratio α of the second bleeder resistor R2a to the combined resistor R20a is defined as α = R2a / R20a. Can be expressed as

(Equation 2)
V108b = (1-α) · VM1aA + αE3

From Equation 2, the DC voltage VM1aA at the second common connection point M1aA can be expressed by Equation 3.
(Equation 3)
VM1a = (1 / (1-α)) · (V108b−α · E3)
Further, when the formula 1 is substituted into the formula 2, the formula 4 is obtained.
(Equation 4)
V108b = (1-α) · Ro (A) · (E3 / R20a + (E2 / 2) / R1a) + αE3

  If Equation 4 is used, the bias voltage V108b can be obtained without going through the calculation process of obtaining the DC voltage VM1a.

  In FIG. 4B, the second voltage source E2 and the first bleeder resistor R1a are twice the size shown in FIG. 4A. In order that the bias voltage supply circuit 130 shown in FIG. 4B is equivalent to that shown in FIG. 4A, it will be described that the DC voltage VM1aB at the second common connection point M1aB is equal to the DC voltage VM1aA shown in FIG. 4A. Good. This is because the third voltage source E3 and the combined resistor 20a have the same size in FIGS. 4A and 4B. Equation 1 represents the DC voltage VM1aA of the second common connection point M1aA of the bias voltage supply circuit 130 shown in FIG. 4A. In FIG. 4B, the second common connection point of the bias voltage supply circuit 130 is shown. The DC voltage VM1aB of M1aB can be expressed by Equation 5 because Equation 1 can be used. In Equation 5, the parallel combined resistance value when the bleeder resistance 2 · R1a, the combined resistance R20a, and the third bleeder resistance R3a are connected in parallel is represented by Ro (B).

(Equation 5)
VM1aB = Ro (B). (E3 / R20a + (E2) /2.R1a)

  In Equation 5, the parallel combined resistance value Ro (B) corresponds to Ro (A) in FIG. 4A. In order to obtain the third bleeder resistance R3a, since Equations 1 and 5 are equal, Equations 6 and 7 must be established.

(Equation 6)
VM1aA = VM1aB

Equation 6 can be replaced with Equation 7 from Equations 1 and 5.
(Equation 7)
Ro (A). (E3 / R20a + (E2 / 2) / R1a) = Ro (B). (E3 / R20a + (E2) /2.R1a)

Here, paying attention to Equation 7, the following can be understood. That is, the terms (E3 / R20a + (E2 / 2) / R1a) on the left side and (E3 / R20a + (E2) / 2 · R1a) on the right side are both equal. Therefore, in order to establish Equation (7), attention should be paid to Ro (A) and Ro (B) of the parallel combined resistance. That is, the third bleeder resistance R3a (x) when the parallel combined resistance Ro (A) = Ro (B) is satisfied may be obtained. Among the parallel combined resistances Ro (A) and Ro (B), the combined resistance R20a is equal to both, so that finally the parallel resistance of the first bleeder resistance R1a and the third bleeder resistance R3a is equal to The third bleeder resistance R3a (x) to be connected in parallel to the bleeder resistance 2 · R1a may be obtained. Therefore, Formula 8 is established.

(Equation 8)
R1a * R3a / (R1a + R3a) = 2 * R1a * R3 (x) / (2R1a + R3 (x))

  The third bleeder resistance R3 (x) to be obtained by solving Equation 8 can be expressed by Equation 9.

(Equation 9)
R3 (x) = 2R1a · R3a / (2R1a + R3a)

  Equation 9 indicates that the third bleeder resistance R3 (X) is a parallel resistance of the bleeder resistances 2R1a and R3a. Since the first and third bleeder resistors R1a and R3a are equal to the first and third feedback resistors, respectively, the third bleeder resistor R3 (x) to be obtained is a resistance value twice that of the first feedback resistor R1. 2 · R1 and the third feedback resistor R3 can be set to be equal to the parallel resistance value.

  As is clear from the above description, the bias voltage supply circuits 130 shown in FIGS. 1 and 2 are equivalent to each other.

  In the first T-type resistor circuit T123 of the gain adjusting circuit 100 shown in FIG. 1, the first, second, and third feedback resistors R1, R2, and R3 are set to R1 = 40 KΩ, R2 = 50 KΩ, and R3 = 10 KΩ, respectively. Then, the total resistance value RT required to configure the first T-type resistance circuit T123 is RT = R1 + R2 + R3, and thus RT = 100 KΩ. Therefore, the total resistance value necessary for configuring the first bias voltage generation circuit 132 shown in FIG. 1 is 100 KΩ.

  On the other hand, since the total resistance value RT required for configuring the first bias voltage generation circuit 132 shown in FIG. 2 is RT = 2 · R1 + R2 + (2 · R1) // R3, RT = 2 · 40 + 50 + 8 889 = 1388.889 KΩ, and the total resistance RT required for the first bias voltage generation circuit is about 1.4 times that of the circuit condition of FIG.

  Comparing only the total resistance value necessary for configuring the first bias voltage generation circuit 132, the circuit configuration of FIG. 1 seems to be more advantageous than FIG. However, the circuit configuration of FIG. 2 is suitable for configuring the gain adjustment circuit of the present invention. This is because the first bias voltage generation circuit 132 must be connected to the second voltage source under the circuit configuration shown in FIG. The second voltage source E2 is generally generated based on the first voltage source E1. For this reason, in order to generate the second voltage source E2, it is necessary to newly provide a voltage generation circuit of E2 = E1 / 2 using circuit elements such as resistors and operational amplifiers. The area occupied by such a circuit element on the semiconductor chip may require more area than creating a resistor. Even if the area occupied by the circuit element in the semiconductor chip can be made smaller than the increase in resistance, the voltage generation circuit made of the circuit element involves variations in the manufacturing of the semiconductor integrated circuit. The source is not always obtained. Furthermore, there may be a problem that the generated voltage source fluctuates due to a change in ambient temperature. Considering these points, the circuit configuration of FIG. 2 is not less disadvantageous than that of FIG.

  On the other hand, the first bleeder resistor R1a of the first bias voltage generation circuit 132 in FIG. 2 can be directly connected to the second voltage source E2 to the voltage source. There is no need to provide a voltage generation circuit. Further, since it is not necessary to provide a new voltage generation circuit depending on circuit elements, manufacturing variations can be eliminated. In addition, since it is not necessary to use a voltage source generated by a circuit element, it is possible to receive a fixed voltage from a stable voltage source without being affected by changes in the ambient temperature. Can be eliminated.

  FIG. 5 shows a change of the bias voltage V108b of the non-inverting input terminal 108 of the operational amplifier 108 obtained by the formula 2 or the formula 4 with respect to the magnitude of the second variable resistor RV2. The first bleeder resistance R1a = 80KΩ, the second bleeder resistance R2a = 50KΩ, the third bleeder resistance R3a = 8.89KΩ, the third voltage source E3 = 2.5V, and the second variable resistance RV2 from 10KΩ. FIG. 11 is a characteristic diagram when the second voltage source E2 is changed to a range of up to 60 KΩ and the second voltage source E2 is E2 = 10V, 20V, 25V, and 30V.

When the second voltage source E2 is 10V or 20V, the bias voltage V108b supplied to the non-inverting input terminal 108 decreases as the second variable resistor RV2 increases, and when the second voltage source E2 is 25V, the variable resistor RV2 It can be seen that the voltage is constant at 2.5 V without depending on the size. This is because the second voltage source E2 is divided by the first bleeder resistor R1a and the third bleeder resistor R3a, and the DC voltage VM1a generated at the second common connection point M1a and the third voltage source E3 = 2.5V are obtained. This is because they are almost equal. That is, the DC voltage generated in the so-called voltage dividing circuit composed of the first bleeder resistor R1a, the third bleeder resistor, and the second voltage source E2 is substantially equal to that of the third voltage source E3. When the second voltage source E2 exceeds 25V, for example, E2 = 30V, the bias voltage VM108b tends to increase although it is very small as the second variable resistance RV2 increases. That is, under the conditions of the first bleeder resistance R1a = 80 KΩ, the second bleeder resistance R2a = 50 KΩ, the third bleeder resistance R3a = 8.889 KΩ, and the third voltage source E3 = 2.5V, When the voltage source E2 is 25 V or less, the third voltage source E3 is dominant, and when the voltage source E2 is more than 25 V, the second voltage source E2 is dominant. In any case, a combined voltage of the bias voltages generated by both voltage sources is generated as the bias voltage V108b, and the generated bias voltage V108b is supplied to the non-inverting input terminal of the operational amplifier.

When the bias voltage V108b of the non-inverting input terminal 108b of the operational amplifier 108 is set by the second variable resistor RV2, the bias voltage of the non-inverting input terminal 108a of the operational amplifier 108 is set to the same magnitude as the bias voltage V108b. . That is, the bias voltage V108b = V108a. Further, since the second variable resistor RV2 is linked to the first variable resistor RV2, the DC bias voltage of the inverting input terminal 108a of the operational amplifier 108 is adjusted together with the voltage gain adjustment.

Referring to FIG. 5, in the range of the second voltage source E2 = 10V to 30V, the minimum value and the maximum value of the bias voltage V108b are both when the second variable resistor RV2 is 60 KΩ, and the minimum value is E2 = It can be seen that V108b = 1.74V when 10V and the maximum value is V108b = 2.75V when E2 = 30V. Of particular note is that the bias voltage V108b at E2 = 30V is not far from 2.5V, such as 2.75V. This suggests that the first voltage source E1 can be used at 5V and the second voltage source E2 can be used in a relatively wide range up to 30V. Normally, when the second voltage source E2 is used with a relatively high voltage source, the first voltage source E1 must be increased accordingly, but the present invention can eliminate such problems.

  FIG. 6 shows the dependency of the bias voltage V108b on the second voltage source E2. This is a case where the first bleeder resistance R1a = 80 KΩ, the second bleeder resistance R2a = 50 KΩ, the third bleeder resistance R3a = 8.889 KΩ, and the third voltage source E3 = 2.5V. FIG. 6 shows two values when the second variable resistor RV2 is 10 KΩ and 60 KΩ. In the gain adjustment circuit according to the embodiment of the present invention, 10 KΩ and 60 KΩ of the second variable resistor RV2 are the minimum value and the maximum value of the adjustment range, respectively, but these adjustment ranges are one of the design matters. Not too much.

In FIG. 6, when the change of the bias voltage V108b when the second variable resistance RV2 = 10 KΩ is seen, the bias voltage V108b when the second voltage source E2 is E2 = 10V, 15V, 20V, 25V, and 30V, respectively. V108b = 2.28V, 2.35V, 2.43V, 2.50V and 2.57V, which are proportional to the increase in the second voltage source E2.

Similarly, when the change of the bias voltage V108b when the second variable resistor RV2 = 60 KΩ is seen, the bias voltage V108b when the second voltage source E2 is E2 = 10V, 15V, 20V, 25V, and 30V is V108b, respectively. = 1.74V, 1.99V, 2.25V, 2.50V and 2.75V, which is proportional to the increase of the second voltage source E2 as in the case of the second variable resistance RV2 = 10 KΩ. However, it can be seen that the increasing rate of change is greater for the second variable resistor RV2 = 60 KΩ than for RV2 = 10 KΩ.

The change rate of the bias voltage V108b with respect to the change of the second voltage source E2 is inevitably different when the second variable resistance RV2 = 10 KΩ and 60 KΩ. This is because the bias voltage V108b is determined by two components: a voltage component that increases in proportion to the second voltage source E2 and a voltage component supplied from the fixed third voltage source E3. The larger the ratio determined by the third voltage source E3, the smaller the change in the bias voltage V108b. Conversely, the smaller the influence of the third voltage source E3, the larger the change in the bias voltage V108b with respect to the change in the second voltage source E2. Become. The ratio α depending on the third voltage source E3 can be expressed as α = R2a / R20a. That is, α = R2a / (RV2 + R2a). Here, the ratio α is the same factor as the ratio α used in Equations 2 and 3. As is apparent from α = R2a / (RV2 + R2a), it can be seen that the ratio α decreases as the second variable resistance RV2 increases. The smaller the ratio α, the lower the degree of dependence on the third voltage source E3, which is a constant voltage component, and the higher the percentage of dependence on the second voltage source E2.

It can be seen that the change widths P10, P15, P20, and P25 of the respective bias voltages V108b when the second voltage source E2 = 10V, 15V, 20V, and 25V decrease as the second voltage source E2 increases. The change width P25 of the bias voltage V108b when E2 = 25V is almost zero, the change width increases again as E2 increases from E2 = 25V, and the change width P30 when E2 = 30V is E2 = 20V. It can be seen that the change width P20 is substantially equal.

  FIG. 7A and FIG. 7B show calculation results showing how the three voltages generated by the bias voltage supply circuit 130 change with respect to the change of the second voltage source E2. That is, it represents the dependency of the bias voltage V108b, the DC voltage VM1a, and the third voltage source E3 on the second voltage source E2. FIG. 7A shows a case where the second variable resistor RV2 is 10 KΩ, and FIG. 7B shows a case where RV2 is 60 KΩ. The bias voltage V108b is a result calculated based on Equations 1 to 4.

7A and 7B can be understood that the DC voltage VM1a at the second common connection point M1a is substantially the same regardless of the magnitude of the second variable resistor RV2. Referring to FIG. 7A when the second variable resistor RV2 is 10 KΩ, the DC voltage VM1a at the second common connection point M1a when the second voltage source E2 is 10V is 1.18V. On the other hand, referring to FIG. 7B when the second variable resistor RV2 is 60 KΩ, the value is 1.10 V, and the difference between them is only 80 mV. Similarly, when the second voltage source E2 is 30V, the size of VM1a is 2.94V and 2.97V, so the difference between them is only 30mV. That is, it can be seen that the magnitude of the second variable resistor RV2 does not contribute much to the magnitude of the DC voltage VM1a.

  Referring to both FIG. 7A and FIG. 7B, when the bias voltage V108b is similarly viewed, the bias voltage V108b when the second voltage source E2 is 10V is 2.28V and 1.74V, respectively. The difference is 540 mV, which is about 7 times the difference voltage of the DC voltage VM1a. Similarly, when the second voltage source E2 is 30V, the bias voltage V108b is 2.57V and 2.75V, so the difference voltage between them is 180 mV, which is about 6 times the difference voltage of the DC voltage VM1a.

  Such a difference between the DC voltage VM1a and the bias voltage V108b is one of the major features of the bias voltage supply circuit of the present invention. That is, the DC voltage VM1a at the second common connection point M1a is dominated by the first voltage generation circuit 132, but the bias voltage V108b at the non-inverting input terminal 108b of the amplifier 108 is the same as that of the second voltage generation circuit 138. This is determined by which of the voltage generation circuits 132 is dominant. As apparent from FIGS. 7A and 7B, the change of the bias voltage V108b with respect to the second voltage source E2 is determined based on the magnitudes of the DC voltage VM1a and the third voltage source E3. It becomes the size.

  In any case, the bias voltage supply circuit 130 used in the gain adjustment circuit 100 of the present invention depends on the first bias voltage generation circuit 132 that generates a bias voltage proportional to the second voltage source E2 and the second voltage source. By combining a second bias voltage generation circuit 138 that generates a constant bias voltage that is not generated, an intermediate bias voltage is generated, and this bias voltage is supplied to one of the two input terminals of the operational amplifier. It is a thing.

  In the description so far, the bias voltage supply circuit 130 has been mainly used. This is because the technical idea of the present invention is particularly characterized by the presence of the bias voltage supply circuit 130, and the bias voltage V108b supplied from the bias voltage supply circuit 130 to one input terminal of the operational amplifier is the electric power of the gain adjustment circuit of the present invention. This is because it greatly affects the target characteristics. However, the set bias voltage V108b adjusts the DC circuit operating point of the negative feedback circuit composed of the first T-type resistor circuit T123 connected to the other input terminal 108a of the operational amplifier 108 to a predetermined level. Finally, the midpoint voltage of the signal output terminal 120, that is, the DC voltage when there is no signal, is approximately half of the voltage source with respect to gain adjustment and the size and fluctuation of the voltage source. The effect of the present invention is exhibited only by holding. Therefore, the following describes how the bias voltage V108b set by the bias voltage supply circuit 130 and the DC voltage VM1a at the second connection point M1a control and adjust the first T-type resistor circuit T123. .

  FIG. 8 is an equivalent circuit diagram for obtaining the midpoint voltage Vo of the signal output terminal 120. The midpoint voltage Vo is a DC voltage at the signal output terminal 120 when no analog input signal is input, that is, when there is no signal. FIG. 8 shows the first feedback resistor R1, the second feedback resistor R2, and the third feedback resistor R3. The circuit configuration of FIG. 8 is exactly the same as the first T-type resistance circuit T123 that constitutes the negative feedback circuit. That is, the first feedback resistor R1 and the second feedback resistor R2 are connected in series and have a first common connection point M1, and one end of the first feedback resistor R1 is connected to the signal output terminal 120, One end of the feedback resistor R2 is connected to the inverting input terminal 108a of the operational amplifier 108, respectively. It can be considered that the inverting input terminal 108a is supplied with the bias voltage V108a adjusted to the same magnitude as the bias voltage V108b. A third feedback resistor R3 is connected between the first common connection point M1 and the ground terminal. The resistance values of the three feedback resistors are set to R1 = 40 KΩ, R2 = 50 KΩ, and R3 = 10 KΩ, respectively. The first feedback resistor R1 and the second feedback resistor R2 are set to be four times and five times as large as the third feedback resistor R3, respectively, but these relationships are only one of the design matters. Absent. As will be described later, when the T-type resistance circuit shown in FIG. 8 is used in the negative feedback circuit, the maximum voltage gain is obtained when R1 = R2 in the same range of the sum of the first and second feedback resistance values. For example, assuming that R1 + R2 = 90 KΩ is constant, a higher voltage gain is obtained when R1 = R2 = 45 KΩ than when R1 = 40 KΩ and R2 = 50 KΩ. Incidentally, if the balance between the resistance values of the two is further lost and R1 = 30 KΩ and R2 = 60 KΩ are set, the voltage gain Gv at that time becomes smaller than that when R1 = 40 KΩ and R2 = 50 KΩ.

Aside from setting the voltage gain Gv, if Kirchhoff's law is applied to the T-type resistor circuit of FIG. 8, the midpoint voltage Vo, the DC voltage VM1 at the first common connection point M1, and the first to third feedbacks are applied. If the direct currents flowing through the resistors R1, R2 and R3 are i1, i2 and i3, respectively, they can be expressed by the following mathematical formulas.
(Equation 10)
Vo = VM1 + R1 · i1
(Equation 11)
VM1 = R3 · i3
(Equation 12)
i2 = (VM1-V108a) / R2
(Equation 13)
i1 + i2 = i3
Equation 14 is obtained from Equation 13.
(Equation 14)
i1 = i3-i2 = (VM1 / R3)-(VM1-V108a) / R2
Substituting Equation 14 into Equation 10 yields Equation 15.
(Equation 15)
Vo = VM1 + R1 · i1 = VM1 + R1 ((VM1 / R3) − (VM1−V108a) / R2)
In Equation 15, the DC voltage VM1a at the second common connection point M1a can be equal to VM1a in Equation 1, the bias voltage V108a can be equal to the bias voltage V108b, and when the DC voltage VM1aA is applied to Equation 1, Table 1 The calculation results shown in (1) are obtained.

Table 1 shows the calculation results when the first and second variable resistors are RV1 and RV2, respectively, which are set to equal resistance values and the resistance values of these variable resistors are 10 KΩ and 60 KΩ.

The calculation results shown in Table 1 are the same as those shown in FIGS. 7A and 7B, respectively, except for the midpoint voltage Vo. However, the calculation results shown in Table 1 are displayed with a more effective number of digits than the values shown in FIGS. 7A and 7B in order to increase the calculation accuracy of the midpoint voltage Vo.

  Further, Table 1 also shows the numerical values of the main items in order to help the calculation of each DC voltage such as the first and second common connection points M1 and M1a. For example, the ratios α and α · E3 are useful for obtaining the bias voltage V108b when the DC voltage VM1a at the second connection point M1a is known in the equation (2). For example, when RV1 = RV2 = 10 KΩ and the second voltage source E2 = 10V, the bias voltage V108b is V108b = (1−α) · VM1a + α · E3, so V108b = (1−50 / 60) · 1. A calculation result of 176 + 2.083 = 2.279V is obtained.

  Further, the coefficient 1 / (1-α) shown in Table 1 is useful for obtaining the DC voltage VM1a at the second connection point M1aA using Equation 3. According to Equation 3, since VM1aA = (1 / (1-α)) · (V108b−α · E3), VM1aA when RV1 = RV2 = 10KΩ and E2 = 10V is VM1aA = 6 · ( 2.279−2.083) = 1.176V is obtained.

  The coefficient α · E3 shown in Table 1 represents a so-called contribution ratio indicating how much the third voltage source E3 contributes to the magnitude of the bias voltage V108b. The ratio α is defined as α = R2a / (RV2 + R2a) as described above. The combined resistor R20a in Table 1 is described above, but represents the series resistance of the second variable resistor RV2 and the second bleeder resistor R2a, and R20a = RV2 + R2a, which determines the magnitude of the ratio α. Involved. When the second variable resistance RV2 = 10 KΩ and the second bleeder resistance R2a = 50 KΩ, the combined resistance R20a = 60 KΩ. When RV2 = 60 KΩ and R2a = 50 KΩ, the combined resistance R20a = 110 KΩ.

  The parallel combined resistance Ro (A) represents a parallel combined resistance when the first bleeder resistance R1a, the combined resistance R20a, and the third bleeder resistance R3a are connected in parallel in FIG. 4A.

  Table 2 shows the calculation results of the direct current flowing through the first feedback resistor R1, the second feedback resistor R2, and the third feedback resistor R3a in FIG.

The currents i1, i2, and i3 flowing through the first bleeder resistor R1, the second bleeder resistor R2, and the third bleeder resistor R3 are expressed by Equations 12-14, the voltage VM1a at the second connection point M1a, and the bias voltage V108b (V108a). And the midpoint voltage Vo. When the second voltage source E2 is 30V, the current i1 flowing through the first feedback resistor R1 becomes negative. That is, the direction of the current shown in FIG. 8 is reversed, and the current i3 flows from the first connection point M1 toward the signal output terminal 120.

FIG. 10 shows the calculation result of the voltage gain Gv of the gain adjustment circuit 100 of the present invention. The voltage gain Gv of the gain adjustment circuit 100 shown in FIGS. 1 and 2 is the voltage gain Gv between the analog input signal Sin input to the signal input terminal 102 and the output signal Sout output to the signal output terminal 120. It is expressed by Equation 16.
(Equation 16)
Gv = (R2 / RV1). (R1 / R3) + (R1 + R2) / RV1
Incidentally, the voltage gain Gv1 in the negative feedback circuit to which the third feedback resistor R3 is not connected can be expressed by Expression 17 because the third feedback resistor R3 can be regarded as infinite.
(Equation 17)
Gv1 = (R1 + R2) / RV1

It should be noted that, as is clear from Equation 16, the first term on the right side, (R2 / RV1) · (R1 / R3), the sum of the first feedback resistor R1 and the second feedback resistor R2 is the same under these conditions. The voltage gain Gv is maximized when the feedback resistors are equal. For example, when R1 + R2 = 90 KΩ, when R1 = R2, that is, when R1 = 45 KΩ and R2 = 45 KΩ, the voltage gain Gv is larger than when R1 = 40 KΩ and R2 = 50 KΩ. Further, if the balance between the resistance values of the two is lost and set to, for example, R1 = 60 KΩ and R2 = 30 KΩ, the voltage gain Gv further decreases than that at the maximum. Therefore, this may be taken into consideration when designing the first T-type resistor circuit T123 and the second T-type resistor circuit T123a.

Comparing Equation 16 and Equation 17, the voltage gain Gv of the negative feedback circuit using the T-type resistor circuit is (R2 / RV1) · (R1) compared with the voltage gain Gv1 of the negative feedback circuit not using it. It can be seen that it is larger by / R3).
If the first variable resistor RV1 is changed from 10 KΩ to 60 KΩ, and the first bleeder resistor R1 = 40 KΩ, the second bleeder resistor R2 = 50 KΩ, and the third bleeder resistor R3 = 10 KΩ, then RV1 = 10 KΩ, 20 KΩ. , 30KΩ, 40KΩ, 50KΩ, and 60KΩ, the respective voltage gains Gv are obtained as follows: Gv = 29.2db, Gv = 23.2db, Gv = 19.7db, Gv = 17.2db, Gv = 15.3db and Gv = 13.7 db. In the embodiment of the present invention, the maximum value and the minimum value of the voltage gain Gv are set to 29.2 db and 13.7 db, respectively, but this is only one of the design matters.

(Fourth embodiment)
FIG. 11 shows a class D power amplifier according to the present invention. The gain adjustment circuit 100 shown in FIG. 3 is applied to a class D power amplifier. Of course, the gain adjustment circuit 100 shown in FIGS. 1 and 2 may be applied to a class D power amplifier.

The class D power amplifier 200 includes a signal input terminal 102. For example, an analog input signal Sin having an amplitude value of 3 V or less is input to the signal input terminal 102. A third voltage source E3 is connected to a non-inverted input terminal (not shown) of the operational amplifier 104 via a bias voltage supply line 136. Supply. The size of the third voltage source E3 is preferably ½ of the size of the first voltage source E1 supplied to the operational amplifier 104. That is, when E1 = 5V, E3 = 2.5V is set.

On the output side of the operational amplifier 104, an analog input signal of 3 having the same amplitude value with the third voltage source E3 as a DC voltage component is output. The output analog signal is input to the inverting input terminal 108a of the operational amplifier 108 via the first variable resistor RV1. The minimum resistance value of the first variable resistor RV1 is set to 10 KΩ, and the maximum value is set to 60 KΩ. The variable range of the first variable resistor RV1 is 10 KΩ to 60 KΩ, but this variable range is only one of the design matters. It may be set as appropriate according to the resistance value of the first T-type resistor circuit T123 constituting the negative feedback circuit described later and the adjustment range of the voltage gain Gv.

The other end of the first variable resistor RV1 is connected to the inverting input terminal 108a of the operational amplifier 108. An integrating capacitor C1 is connected between the output terminal 108c and the inverting input terminal 108a of the operational amplifier 108. The size of the integrating capacitor C1 is, for example, 35 pF, and is a size that does not become an obstacle to being built in a semiconductor integrated circuit. The size of the integrating capacitor C1 affects the frequency characteristics of the gain adjustment circuit 100 and the class D power amplifier 200. The operational amplifier 108 to which the integrating capacitor C1 is connected has the functions of both the gain adjustment circuit and the integrating circuit of the class D power amplifier 200. This is one of the features of the present invention. That is, the class D power amplifier of the present invention integrates an integration circuit and a gain adjustment circuit. With such a circuit configuration, the circuit configuration of the class D power amplifier can be simplified.

The power amplifier 200 shown in FIG. 11 is usually composed of a semiconductor integrated circuit. Simplification of the circuit configuration leads to a reduction in the size of the semiconductor chip. In addition, the electrical characteristics of the entire class D power amplifier can be improved by simplifying the circuit configuration. Normally, as the number of circuit connection stages increases, the subsequent circuit is affected by the previous circuit. For example, in a class D power amplifier, in a circuit configuration in which the integration circuit is provided in the preceding stage of the gain adjustment circuit, fluctuations in the circuit operating point of the gain adjustment circuit affect the subsequent integration circuit. Further, when the class D power amplifier is configured by a semiconductor integrated circuit, variations in electrical characteristics in manufacturing the semiconductor integrated circuit further affect the subsequent circuit. Further, the gain adjustment circuit has a problem that the DC bias voltage fluctuates with the change of the AC voltage gain.

The modulation circuit 110 is connected to the output terminal 108 c side of the operational amplifier 108. A modulation circuit 110 shown in FIG. 11 is a pulse modulation circuit in a broad sense disclosed in Patent Document 4 above. That is, the modulation circuit 110 of the present invention includes all or a part of the comparators, gate drivers, and power transistors necessary for the class D power amplifier. In addition to these, the class D power amplifier is also known to include a dead time (DT) correction circuit and a level shifter. The second voltage source E2 supplied to the modulation circuit 110 including a power amplifier connected to the signal output terminal 120 on the output side of the modulation circuit 110 is supplied to the operational amplifier 108, for example, the first voltage. The source E1 is higher than 5V, and its magnitude E2 is, for example, 10V to 30V. Alternatively, E2 may exceed 30V.

The signal output terminal 120 is connected to a first T-type resistor circuit T123 constituting a negative feedback circuit. One end of the first feedback resistor R1 is connected to the signal output terminal 120. The second feedback resistor R2 forms a series connection body connected in series with the first feedback resistor, and a third feedback resistor R3 is connected between the first common connection point M1 and the ground terminal. Is done. One end of the second feedback resistor R2 is connected to an inverting input terminal 108a of an operational amplifier 108 having both an integration circuit and a gain adjustment circuit. Note that the first T-type resistor circuit T123 constituting the negative feedback circuit may be connected to the non-inverting input terminal 108b of the operational amplifier 108. The bias voltage V108b is supplied from the bias voltage supply circuit 130 to the non-inverting input terminal 108b of the operational amplifier 108. The bias voltage supply circuit 130 is the same as that shown in FIG.

The bias voltage supply circuit 130 includes a first bias voltage generation circuit 132 and a second bias voltage generation circuit 138. The first bias voltage generation circuit 132 includes a second T-type resistance circuit T123a and a second voltage source E2. The second T-type resistance circuit T123a has a first bleeder resistance R1a, a second bleeder resistance R2a, and a third bleeder resistance R3a. A DC voltage VM1a is generated at the common connection point of these three bleeder resistors, that is, the second common connection point M1a. The first bias voltage generation circuit 132 is connected to the second bias voltage generation circuit 138 via the second bleeder resistor R2a. The DC voltage VM1a is substantially determined by the resistance ratio between the first bleeder resistor R1a and the third bleeder resistor R3a.

The second T-type resistance circuit T123a is one voltage dividing circuit. By adopting the T-type resistor circuit 123a, the DC voltage VM1a at the second common connection point M1a can be divided to the same magnitude as the DC voltage on the input side of the operational amplifier 108. As a result, the DC coupling between the operational amplifier 108 and various other circuits to which the second voltage source E2 is connected can be easily performed.

The magnitude of the DC voltage VM1a is determined based on the magnitude of the second voltage source E2 applied to various circuits. For example, if the maximum value of the second voltage source E2 is 30V, when VM1a is E2 = 30V, the resistances of the first bleeder resistor R1a and the third bleeder resistor R3a are set so as not to greatly exceed 2.5V. Determine the ratio.

The first variable resistor RV1, the second variable resistor RV2, the first T-type resistor circuit T123, and the second T-type resistor circuit T123a constituting the class D power amplifier 200 shown in FIG. However, not only the resistance of the passive element but also a switched capacitor may be used. At least one or all of these can be composed of switched capacitors. Note that a clock signal is required to drive the switched capacitor, and a triangular wave signal or a rectangular wave pulse generated by the modulation circuit 110 can be used as the clock signal.

(Fifth embodiment)
FIG. 12 shows another embodiment of the class D power amplifier according to the present invention. The bias voltage supply circuit 130 is different from FIG. The bias voltage supply circuit 130 shown in FIG. 12 is the same as that shown in FIG. Other circuits and components other than the bias voltage supply circuit 130, that is, the signal input terminal 102, the operational amplifier 108, the first variable resistor RV1, the first T-type resistor circuit T123, the modulation circuit 110, and the signal output terminal 120 Since these are exactly the same as those in FIG. 11, detailed description thereof is omitted.

FIG. 13 shows the calculation results of the frequency characteristics of the class D power amplifier shown in FIGS. A so-called cut-off frequency fc at which the voltage gain Gv is minus 3 db can be expressed by Equation 18.

(Equation 18)
fc = Gh / (2π · C1 · (R1 + R2 + (R1 · R2) / R3))

In Equation 18, Gh is the voltage gain of the modulation circuit 110. Gh is determined by the amplitude of the triangular wave signal S2 and the second voltage source E2 supplied to the modulation circuit 110. For example, when the amplitude of the triangular wave signal S2 is 3V and the second voltage source E2 is 12V, the voltage gain of the modulation circuit 110 Gh = E2 / S2 = 12V / 3V = 4. Therefore, it can be seen that the triangular wave signal S2 and the second voltage source E2 need only be increased in order to increase the voltage gain Gh of the modulation circuit. In Equation 18, C1 is the capacitance value of the integrating capacitor C1, and C1 = 35PF in one embodiment of the present invention. In Equation 18, R1, R2, and R3 are feedback resistors used in the first T-type resistor circuit T123, that is, the negative feedback circuit. In Equation 18, it can be seen that R1 + R2 + (R1 · R2) / R3) is equal to the value when the magnitude of the first variable resistor RV1 is “1” in Equation 16 in which the voltage gain Gv is obtained. .

If R1 = 40KΩ, R2 = 50KΩ, R3 = 10KΩ, C1 = 35PF, and Gh = 4 in order to obtain the cutoff frequency fc, the cutoff frequency fc is
fc = 4 / (2 · 3.14 · 35 · 10 ⁻¹² · (40 · 10 ³ + 50 · 10 ³ + (40 · 10 ³ · 50 · 10 ³ ) / 10 · 10 ³ )) = 62.8 KHz Become.
As apparent from Equation 18, the first variable resistor RV1 is not affected at all by the cutoff frequency fc. This is preferable for the gain adjustment circuit 100 and the class D power amplifier 200 of the present invention. In general, when an integration circuit is configured using an operational amplifier, the time constant of the integration circuit changes depending on the impedance on the input side, so that the cutoff frequency fc also changes according to gain adjustment. In the present invention, such a problem can be eliminated by employing a negative feedback circuit composed of a T-type resistance circuit.

(Sixth embodiment)
FIG. 14 shows a more specific circuit configuration of the modulation circuit 110 shown in FIGS. 12 and 13 and its peripheral circuits. The class D power amplifier shown in FIG. 14 includes a modulation circuit 110, and the modulation circuit 110 includes a comparator 112, a triangular wave signal generation circuit 114, a gate driver 116, and power transistors TR1 and TR2.

  An integration signal S1 that has been voltage-amplified and integrated by the operational amplifier 108 is input to the inverting input terminal 112a of the comparator 112. The triangular wave signal S2 is input to the non-inverting input terminal 112b of the comparator 112. The triangular wave signal S2 is a carrier signal for pulse width modulation (PWM) of the integration signal S1. The triangular wave signal S2 is generated by the carrier signal generator 114, and its frequency is set to 500 KHz, for example, and its amplitude value is set to 3 V, for example. As described above, the amplitude value of the triangular wave signal S2 is one factor that determines the frequency characteristic of the gain adjustment circuit 100 or the class D power amplifier. For the triangular wave signal S2, for example, a frequency sufficiently higher than an audible audio frequency of 20 Hz to 20 KHz is selected in an audio power amplifier. In the present invention, the frequency is set to 500 KHz, which is 20 times or more the audible audio frequency. However, practically, the frequency of the triangular wave signal S2 is about 200 KHz. The triangular wave signal generation circuit 114 can be constituted by, for example, an operational amplifier or a hysteresis comparator (Schmitt trigger circuit). The hysteresis comparator can also be regarded as one operational amplifier. When a positive feedback circuit is used for the operational amplifier, a hysteresis comparator can be produced.

  When the integration signal S1 is input to the inverting input terminal 112a of the comparator 112, the integration signal S1 is pulse-width modulated by the triangular wave signal S2, that is, a PWM signal is output to the output terminal 112c of the comparator 112. This PWM signal is input to the gate driver 116 at the subsequent stage. The gate driver 116 amplifies the PWM signal output from the comparator 112 in order to drive the power transistors TR1 and TR2 at the subsequent stage.

  The power transistors TR1 and TR2 amplify the PWM signal output from the gate driver 116. The power-amplified PWM signal is output to the signal output terminal 120. The PWM signal output to the signal output terminal 120 is supplied to the low pass filter 140. The low-pass filter 140 is composed of, for example, a coil and a capacitor. The analog signal demodulated after being band-limited by the low-pass filter 140 is supplied to the speaker 150.

  The PWM signal output to the signal output terminal 120 is fed back to the inverting input terminal 108a of the operational amplifier 108 via the first T-type resistor circuit T123 that constitutes a negative feedback circuit. The negative feedback circuit including the first T-type resistance circuit T123 shown in FIG. 14 performs negative feedback from the output side to the input side of the class D power amplifier. As a result, distortion that tends to occur in the class D power amplifier can be reduced. It should be noted that the voltage gain of the power amplifier shown in FIG.

The comparator 112 constituting the pulse modulation circuit in the narrow sense of the present invention uses a PWM method in which the integration signal S1 is modulated by a triangular wave signal S2 whose frequency is fixed and whose period does not change. The PWM modulation circuit provided with the triangular wave generation circuit 114 for generating the triangular wave signal S2 is generally called a separately excited oscillation type PWM system. In the specific PWM modulation circuit of the present invention, such a separately excited oscillation type PWM method is used, but a so-called self-excited oscillation type PWM modulation method as disclosed in Patent Document 6 can also be used. The gain adjustment circuit according to the present invention can also be applied to a delta-sigma modulation PWM difference integrator shown in Patent Document 7.

The triangular wave signal S2 generated by the triangular wave signal generation circuit 114 can be used as a clock signal for driving the above-described switched capacitor directly or via a frequency divider after shaping the waveform into a rectangular wave pulse. .

Although FIG. 14 shows a so-called single-ended type power amplifier, the present invention is not limited to this. For example, the present invention can be applied to a BTL type power amplifier.

  15A to 15C schematically show a process in which the PWM signal is generated by the comparator 112. FIG. The horizontal axis schematically represents time, and the vertical axis schematically represents the level of various signals. FIGS. 15A, 15B, and 15C represent processes in which PWM signals having duty ratios of 10%, 50%, and 90% are generated, respectively. In FIG. 15A, the integration signal S1 is input to the inverting input terminal 112a of the comparator 112, and the triangular wave signal S2 is input to the non-inverting input terminal 112b. When the triangular wave signal S2 is higher than the integration signal S1, a high level is output to the output terminal 112c of the comparator 112. Conversely, when the triangular wave signal S2 is lower than the integration signal S1, a low level is output to the output terminal 112c. The PWM signal output to the output terminal 112c is output to the signal output terminal 120 via the gate driver 116 and the power transistors TR1 and TR2. The amplitude of the PWM signal output to the signal output terminal 120 is the same as that of the voltage source E2 supplied to the power transistors TR1 and TR2. In the comparator 112, the DC bias voltage of both is set so that the maximum value S1H and the minimum value S1L of the integration signal S1 are within the amplitude of the triangular wave signal S2.

  FIG. 15B schematically shows a case where the duty ratio is 10%. Compared to FIG. 15A, the time for which the level of the triangular wave signal S2 exceeds the integration signal S1 is shortened, so the duty ratio is small. Since the basic operation is the same as that in FIG. 15A, a detailed description is omitted.

  FIG. 15C schematically shows a case where the duty ratio is 90%. Compared to FIGS. 15A and 15B, the time for which the level of the triangular wave signal S2 exceeds the integration signal S1 becomes longer, so the duty ratio becomes larger. Since the basic operation is the same as that in FIG. 15A, a detailed description is omitted.

  FIG. 16A schematically shows an example in which the first T-type resistance circuit T123 constituting the negative feedback circuit and the second T-type resistance circuit T123a which is the main circuit of the bias voltage supply circuit are constituted by semiconductor integrated circuits. In the example shown in FIG. 16A, the first T-type resistor circuit T123 and the second T-type resistor circuit T123a correspond to those shown in FIG. 2 or FIG. The first, second, and third feedback resistors are R1 = 40 KΩ, R2 = 50 KΩ, and R3 = 10 KΩ, respectively. Each bleeder resistance constituting the second T-type resistance circuit T123a is set to R1a = 80 KΩ, R2a = 50 KΩ, and R3a = 8.889 KΩ, respectively. The third bleeder resistor R3a is configured by parallel connection of 80 KΩ, which is twice as large as the first feedback resistor R1, and the resistance value of the third feedback resistor R3, that is, 10 KΩ.

When viewed in front of FIG. 16A, terminals connected to the signal output terminal 120 and the second voltage source E2 are arranged in the upper part of the central portion. The upper left part shows a configuration in which the first feedback resistor R1 is connected in series with four resistors, partial feedback resistors R1-1, R1-2, R1-3, and R1-4. One terminal of the partial feedback resistor R1-1 is connected to the signal output terminal 120. If the resistance values of the partial feedback resistors R1-1, R1-2, R1-3, and R1-4 are 10 KΩ, the total resistance value of the feedback resistor R1 is set to 40 KΩ. Each of the partial feedback resistors R1-1, R1-2, R1-3, and R1-4 is set to be equal to the resistance of a third feedback resistor R3 described later.

  The third feedback resistor R3 is arranged with only one resistor adjacent to the partial feedback resistor R1-4 constituting the first feedback resistor R1. The third feedback resistor R3 is set as a basic resistance pattern in one embodiment of the present invention, and its resistance value is 10 KΩ. In addition to the third feedback resistor R3, a resistor having a relatively small resistance value such as 1 KΩ, 2 KΩ, or 5 KΩ may be prepared as the basic resistance pattern. One end of the third feedback resistor is connected to the first common connection terminal M1, and the other end is connected to the ground terminal GND.

Adjacent to the third feedback resistor R3, the second feedback resistor R2 is arranged by connecting five resistors of partial feedback resistors R2-1, R2-2, R2-3, R2-4 and R2-5 in series. . One end of the partial feedback resistor R2-5 is connected to the first variable resistor RV1. If the resistance value of each partial feedback resistor is 10 KΩ, the total resistance value of the second feedback resistor R2 is 50 KΩ. The first feedback resistor R1, the second feedback resistor R2, and the third feedback resistor R3 constitute a first T-type resistor circuit T123, that is, a negative feedback circuit.

  16A, the second bleeder resistor R2a is formed by connecting five resistors, ie, partial feedback resistors R2a-1, R2a-2, R2a-3, R2a-4, and R2a-5, in series at the lower left. Shows what has been done. If the resistance value of each of these partial feedback resistors is 10 KΩ, the total resistance value of the second bleeder resistor R2a is 50 KΩ. One end of the partial feedback resistor R2a-1 is connected to the second variable resistor RV2, and one end of the partial feedback resistor R2a-5 is connected to the second common connection point M1a.

  16A, the first bleeder resistor R1a is connected to the partial feedback resistors R1a-1, R1a-2, R1a-3, R1a-4, R1a-5, R1a-6, R1a-7 and R1a- 8 shows eight partial feedback resistors connected in series. If each of these partial feedback resistors is 10 KΩ, the total resistance value of the first bleeder resistor R1a is 80 KΩ.

A partial bleeder resistor R3a-II is arranged in the lower right portion when looking straight at FIG. Partial bleeder resistor R3a-II has partial bleeder resistors R3a-1, R3a-2, R3a-3, R3a-4, R3a-5, R3a-6, R3a-7 and R3a-8, and these eight resistors are Connected in series. Since the resistance values of the partial bleeder resistors R3a-1 to R3a-8 are 10 KΩ, the total resistance value of the partial bleeder resistors R3a-II is 80 KΩ. Since the partial bleeder resistors R3a-I and R3a-II are connected in parallel, the final resistance value of the third bleeder resistor R3a is 10 KΩ // 80 KΩ, and the magnitude thereof is 8.889 KΩ.

  FIG. 16B shows another embodiment in which the first T-type resistance circuit T123 constituting the negative feedback circuit and the second T-type resistance circuit T123a which is the main circuit of the bias voltage supply circuit are constituted by semiconductor integrated circuits. . This is basically the same as that of FIG. 16A. That is, the third feedback resistor R3 is arranged as a basic resistance pattern. In order to give priority to the third bleeder resistor R3a and the third feedback resistor R3a adjacent to each other as much as possible, the third bleeder resistor R3a-1 is placed between the first partial bleeder resistors R1a-4 and R1a-5. I arranged it so that it was sandwiched between.

When the gain adjustment circuit and the class D power amplifier of the present invention are configured in a semiconductor integrated circuit, the first and second T-type resistance circuits T123 and T123a that are electrically equivalent and require accuracy in the resistance ratio are provided. In the case of a semiconductor integrated circuit, it is preferable that both are arranged as close as possible.

  The gain adjustment circuit and the class D power amplifier according to the present invention can adjust the DC operating point of the operational amplifier according to the adjustment of the voltage gain, and can be applied to the use of a relatively wide range of voltage sources. The utility value is extremely high.

It is a figure which shows the gain adjustment circuit concerning embodiment of this invention. It is a figure which shows another gain adjustment circuit concerning embodiment of this invention. It is a figure which shows another gain adjustment circuit concerning embodiment of this invention. It is a figure which shows the bias voltage supply circuit used for the gain adjustment circuit concerning embodiment of this invention. It is a figure which shows another bias voltage supply circuit used for the gain adjustment circuit concerning embodiment of this invention. It is a characteristic figure showing change of a bias voltage to the size of the 2nd variable resistance of a bias supply circuit used for a gain adjustment circuit concerning an embodiment of the invention. It is a characteristic view showing a change of a bias voltage with respect to the size of the second voltage source of the bias supply circuit used in the gain adjustment circuit of the present invention. The change of the direct-current voltage of the 2nd T type resistance circuit with respect to the magnitude | size of the 2nd voltage source of the bias supply circuit used for the gain adjustment circuit of this invention, a bias voltage, and a 3rd voltage source is shown, 2nd variable resistance It is a characteristic view when is 10 KΩ. The change of the direct-current voltage of the 2nd T type resistance circuit with respect to the magnitude | size of the 2nd voltage source of the bias supply circuit used for the gain adjustment circuit of this invention, a bias voltage, and a 3rd voltage source is shown, 2nd variable resistance It is a characteristic view when is 60 KΩ. It is an equivalent circuit diagram for obtaining the midpoint voltage of the gain adjustment circuit according to the embodiment of the present invention. It is a characteristic view showing the change of the midpoint voltage with respect to the voltage source E2 of the gain adjustment circuit concerning embodiment of this invention. It is a figure which shows the voltage gain characteristic of the gain adjustment circuit concerning embodiment of this invention. It is a circuit diagram which shows the class D power amplifier concerning embodiment of this invention. It is a circuit diagram which shows another class D power amplifier concerning embodiment of this invention. It is a figure which shows the frequency characteristic of the gain adjustment circuit concerning embodiment of this invention. It is a circuit block diagram which shows the modulation circuit of the class D power amplifier of this invention. It is a figure for demonstrating the circuit operation | movement with a 50% duty ratio in the modulation circuit used for the class D power amplifier of this invention. It is a figure for demonstrating the circuit operation | movement with a 10% duty ratio in the modulation circuit used for the class D power amplifier of this invention. It is a figure for demonstrating the circuit operation | movement with a 90% duty ratio in the modulation circuit used for the class D power amplifier of this invention. It is a figure which shows the resistance arrangement | positioning pattern which shows an example when the 1st and 2nd T-type resistance circuit of the gain adjustment circuit of this invention is arrange | positioned on the semiconductor chip of a semiconductor integrated circuit. FIG. 16B is a resistor arrangement pattern diagram showing an embodiment different from FIG. 16A.

Explanation of symbols

100 gain adjustment circuit
102 signal input terminal 106 signal input terminal 108 operational amplifier 110 modulation circuit 112 comparator 114 triangular wave signal generation circuit 116 gate driver 120 signal output terminal 130 bias voltage supply circuit 132 first bias voltage generation circuit 136 bias voltage supply line
138 Second bias voltage generation circuit 140 Low-pass filter 150 Speaker
200 class D power amplifier R1 first feedback resistor R2 second feedback resistor R3 third feedback resistor R1a first bleeder resistor R2a second bleeder resistor R3a third bleeder resistor TR1, TR2 power transistor T123 first T-type resistor circuit T123a Second T-type resistor circuit RV1 First variable resistor RV2 Second variable resistor E1 First voltage source E2 Second voltage source E3 Third voltage source

Claims (24)

An operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal, to which a voltage is supplied from a first voltage source, one of the inverting input terminal and the non-inverting input terminal, and the output terminal And a first T-type resistor circuit that is connected between the input terminal and the non-inverting input terminal and a signal input terminal. A first variable resistor for adjusting a gain; and a bias voltage supply circuit connected to another input terminal different from the one input terminal to which the first T-type resistor circuit is connected. The voltage supply circuit has a second T-type resistance circuit, generates a voltage proportional to the size of the second voltage source, a first bias voltage generation circuit, a third voltage source, and the third voltage source The second variable resistor connected to the Comprising a second bias voltage generating circuit, a gain adjustment circuit, characterized in that it comprises a circuit connecting member which connects the first bias voltage generation circuit and the second bias voltage generating circuit.   A series connection of an operational amplifier different from the operational amplifier and the first variable resistor is provided between the signal input terminal and one of the inverting input terminal and the non-inverting input terminal of the operational amplifier. Providing the third voltage source to one of an inverting input terminal and a non-inverting input terminal of the another operational amplifier, and providing the other operational amplifier in a stage preceding the operational amplifier, 2. The gain adjustment circuit according to claim 1, wherein the voltage gain is adjusted by the first variable resistor provided in a signal path between the arithmetic unit and the operational amplifier.   2. The gain adjustment circuit according to claim 1, wherein the second voltage source is generated based on the first voltage source.   The magnitude of the voltage supplied from the first voltage source, the second voltage source, and the third voltage source is the order of the second voltage source, the first voltage source, and the third voltage source. The gain adjustment circuit according to claim 1, wherein:   2. The gain adjustment circuit according to claim 1, wherein the voltage of the third voltage source is ½ of the magnitude of the first voltage source.   The circuit connection body that connects the first bias voltage generation circuit and the second bias voltage generation circuit includes the one resistor and the second variable resistor that constitute the second T-type resistance circuit. The combined bias voltage synthesized by the second voltage source and the third voltage source is applied to either the inverting input terminal or the non-inverting input terminal of the operational amplifier via the common connection point of the circuit connection body. The gain adjusting circuit according to claim 1, wherein the gain adjusting circuit is supplied.   3. The gain adjustment circuit according to claim 1, wherein the first variable resistor and the second variable resistor are interlocked with each other. The first T-type resistor circuit has a first feedback resistor, a second feedback resistor, and a third feedback resistor, and the second T-type resistor circuit has a first bleeder resistor and a second bleeder resistor. The gain adjusting circuit according to claim 1, further comprising a third bleeder resistor.   The first feedback resistor and the second feedback resistor have a first common connection point connected in series, and one end of the first feedback resistor is connected to the output terminal side of the operational amplifier, and the second feedback resistor is connected to the second feedback resistor. One end of the feedback resistor is connected to one of the inverting input terminal and the non-inverting input terminal, the third feedback resistor is connected between the first common connection point and the ground terminal, The first bleeder resistor and the second bleeder resistor have a second common connection point connected in series, and one end of the first bleeder resistor and the second bleeder resistor is connected to the second voltage source and the second bleeder resistor. The third bleeder resistor is connected to either one of an inverting input terminal and the non-inverting input terminal, and the third bleeder resistor is connected between the second common connection point and a ground terminal. Item 9. The gain adjustment circuit according to Item 8.   The first feedback resistor and the first bleeder resistor, the second feedback resistor and the second bleeder resistor, and the third feedback resistor and the third bleeder resistor are set to be equal to each other. The gain adjustment circuit according to claim 8.   11. The gain adjustment circuit according to claim 10, wherein the first feedback resistor and the second feedback resistor are set to be equal, and the first bleeder resistance and the second bleeder resistor are set to be equal.   The first bleeder resistor R1a has a resistance value 2 · R1 that is twice the first feedback resistor R1, and the second bleeder resistor R2a has the same resistance value as the second feedback resistor R2. 9. The gain adjustment circuit according to claim 8, wherein the third bleeder resistance R3a is set equal to a resistance value of a parallel resistance of the 2 · R1 and the third feedback resistance R3.   The first T-type resistor circuit and the second T-type resistor circuit are formed on the same semiconductor chip, and the first feedback resistor, the second feedback resistor, the third feedback resistor, the first feedback resistor, 9. The gain adjustment circuit according to claim 8, wherein the bleeder resistance, the second bleeder resistance, and the third bleeder resistance are each configured by a combination of basic resistance patterns.   The basic resistance pattern includes the first feedback resistor, the second feedback resistor, the third feedback resistor, the first bleeder resistor, the second bleeder resistor, and the third bleeder resistor. 14. The gain adjustment circuit according to claim 13, wherein the gain adjustment circuit is any one.   The at least one of the first variable resistor, the second variable resistor, the first T-type resistor circuit, and the second T-type resistor circuit is configured by a switched capacitor. Item 2. The gain adjustment circuit according to Item 1. A class-D power amplifier in which a modulation circuit is connected to the subsequent stage of the gain adjustment circuit according to claim 1. An operational amplifier having two input terminals and an output terminal of an inverting input terminal and a non-inverting input terminal and supplied with the first voltage source, and between one input terminal and the signal input terminal of the two input terminals A first variable resistor connected for gain adjustment; a modulation circuit connected to the output terminal side of the operational amplifier to which a second voltage source is supplied; a signal output terminal connected to the modulation circuit; A first T-type resistor circuit which is connected between a signal output terminal and the one input terminal of the operational amplifier and constitutes a negative feedback circuit, and is connected to the other input terminal of the operational amplifier and supplies a bias voltage. A bias voltage supply circuit, the bias voltage supply circuit being connected to the second voltage source and having a second T-type resistor circuit; and the first and second voltage sources. Smaller than electric And a second bias voltage generation circuit having a second variable resistor connected to the third voltage source, and a circuit connecting the first and second bias voltage generation circuits class D power amplifier and supplying a bias voltage to the other input terminal through the circuit connecting material and a connection member.   The first variable resistor and the second variable resistor are linked to each other, and the voltage gain of the operational amplifier is adjusted by the first variable resistor, and the input side of the operational amplifier is adjusted by the second variable resistor. The class D power amplifier according to claim 17, wherein the operating voltage is adjusted.   A capacitor is connected between the one input terminal and the output terminal of the operational amplifier, and the capacitor, the first variable resistor, and the operational amplifier constitute an integration circuit, and the operational amplifier includes a gain adjustment circuit, the The class D power amplifier according to claim 17, which also serves as an integration circuit.   The first T-type resistor circuit includes a first feedback resistor, a second feedback resistor, and a third feedback resistor, and the first feedback resistor and the second feedback resistor are connected in series. And one end of the first feedback resistor is connected to the signal output terminal connected to the modulation circuit, and one end of the second feedback resistor is connected to one input terminal of the operational amplifier. And the third feedback resistor is connected between the first common connection point and a ground terminal, and the second T-type resistor circuit includes a first bleeder resistor, a second bleeder resistor, and a third The first bleeder resistor and the second bleeder resistor have a second common connection point connected in series, and one end of the first bleeder resistor is connected to the second voltage source In addition, one end of the second bleeder resistor is connected to the operational amplifier. 18. The class D power amplifier according to claim 17, wherein the class D power amplifier is connected to each of the other input terminals, and the third bleeder resistor is connected between the second common connection point and a ground terminal. .   18. The class D power amplifier according to claim 17, wherein the second voltage source is generated based on the first voltage source.   The resistance value of the first bleeder resistor R1a is 2 · R1, which is twice as large as the first feedback resistor R1, and the resistance value of the second bleeder resistor R2a is the same as that of the second feedback resistor R2. The resistance value of the third bleeder resistor R3a is the parallel resistance of the double feedback resistor R3 and the third feedback resistor R3, and R3a = (2 · R1) · R3 / ( 21. The class D power amplifier according to claim 20, wherein the class D power amplifier is set to 2R1 + R3).   The at least one of the first variable resistor, the second variable resistor, the first T-type resistor circuit, and the second T-type resistor circuit is configured by a switched capacitor. Item 18. A class D power amplifier according to item 17. The class D power amplifier according to claim 23, wherein the switched capacitor is driven by a triangular wave signal or a rectangular wave pulse generated by the modulation circuit.