JP2010074308A - Radio communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a radio communication system wherein, even when radio transmission is executed from a plurality of transmission terminal devices, a reception terminal device can execute frequency adjustment in response to a clock frequency of each transmission terminal device without using a preamble. <P>SOLUTION: In this radio communication system, the reception terminal device 4 is provided with a regeneration circuit 4e including: a frequency information generation means to generate frequency information related to frequency adjustment of a clock signal used for a regeneration process of a received signal based on a baseband signal; a means to set frequency adjustment timing before reception start for estimating a point immediately before starting radio communication based on start timing and a transmission cycle of the radio communication by a radio transmission terminal device, and setting the point as frequency adjustment timing before reception start; and a frequency adjustment means to execute the frequency adjustment of the clock signal at the frequency adjustment timing before reception start. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a radio communication system comprising a plurality of transmission terminal apparatuses that periodically and independently perform burst-like radio transmission and a single reception apparatus that receives signals transmitted by the plurality of transmission terminal apparatuses. .

  Conventionally, when information data is transmitted in a carrier band as a burst in the TDMA method, voice activation method, packet transmission method, or the like, transmission is performed with a preamble added to the head of the information data.

  On the receiving side, training for carrier wave recovery and bit timing recovery necessary for demodulation is performed using this preamble, and synchronization is established in a short period so that it can be accurately demodulated from the head of the information data.

  Specifically, the conventionally used preamble includes a carrier recovery unit having a pattern in which “1” continues (or “0” continues), and bits in a pattern in which “1” and “0” repeat alternately. And a timing reproduction unit. The burst becomes an unmodulated continuous wave in the carrier recovery unit. Therefore, carrier recovery is performed in a phase locked loop using the carrier recovery unit. In the bit timing reproduction unit, the burst includes the most bit timing information. Therefore, bit timing recovery is performed by a tank circuit, a phase locked loop, or the like using the bit timing recovery unit.

  Since the preamble described above becomes a “discard bit”, it is preferably as short as possible. Furthermore, ideally, it is preferable not to use a preamble. Under such circumstances, for example, the following technique is proposed in Patent Document 1.

That is, Patent Document 1 discloses a technique for reducing the preamble by AD-converting and storing the preamble and estimating the frequency offset and initial phase using the stored data.
Japanese Patent No. 2513330

  By the way, there is a wireless communication system that includes a plurality of transmission terminal devices that independently and periodically perform wireless transmission using bursts, and a reception terminal device that receives signals wirelessly transmitted by these transmission terminal devices. .

  When the technique disclosed in Patent Document 1 described above is applied to the reproduction circuit of the receiving terminal apparatus in such a wireless communication system, the frequency of the reproduction clock is adjusted using a signal in the preamble period. Therefore, a preamble period having a predetermined length is required.

  The present invention has been made in view of the above circumstances, and even when wireless transmission is performed from a plurality of transmission terminal devices, the present invention is particularly substantially the same from a plurality of transmission terminal devices at substantially the same position. Even when wireless transmission is performed at the timing, the receiving terminal device provides a wireless communication system capable of performing frequency adjustment according to the clock frequency of each transmitting terminal device without using a preamble. For the purpose.

In order to achieve the above object, a wireless communication system according to the first aspect of the present invention comprises:
A wireless communication system comprising: a plurality of wireless transmission terminal devices each performing wireless transmission at a predetermined transmission cycle; and a receiving terminal device that receives a signal wirelessly transmitted by the wireless transmission terminal device,
The receiving terminal device includes an antenna for receiving a signal wirelessly transmitted by the wireless transmitting terminal device, and a baseband signal generating means for generating a baseband signal by performing a demodulation process on the signal received by the antenna And a reproducing circuit for reproducing communication data based on the baseband signal,
The regeneration circuit is
Based on the baseband signal, frequency information generating means for generating frequency information related to frequency adjustment of a clock signal used for the reproduction processing of the baseband signal;
Based on the start timing of wireless transmission by the wireless transmission terminal device and the predetermined transmission cycle, a time point immediately before the start of wireless transmission by the wireless transmission terminal device is estimated, and the time point is set as a frequency adjustment timing before reception start. A frequency adjustment timing setting means before starting reception;
Frequency adjustment means for performing frequency adjustment of the clock signal based on the frequency information at the frequency adjustment timing before the start of reception;
It is characterized by having

  According to the present invention, even when wireless transmission is performed from a plurality of transmission terminal apparatuses, it is particularly a case where wireless transmission is performed at substantially the same timing from a plurality of transmission terminal apparatuses at substantially the same position. However, the receiving terminal apparatus can provide a radio communication system capable of performing frequency adjustment according to the clock frequency of each transmitting terminal apparatus without using a preamble.

  Hereinafter, a wireless communication system according to an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a system configuration example when the wireless communication system according to the first embodiment of the present invention is applied to a nondestructive inspection system. As shown in FIG. 1, the wireless communication system according to the first embodiment includes a mobile transmitter 2, a fixed transmitter 3, and a receiver 4.

  The mobile transmitter 2 is a device that autonomously moves to capture an image of the inspection target portion 1 and its vicinity, and wirelessly transmit image data acquired by the imaging. Specifically, the mobile transmitter 2 autonomously moves around the inspection target unit 1 to perform imaging at a constant cycle, and wirelessly transmits image data acquired by the imaging at a constant cycle.

  The fixed transmitter 3 is a device that captures an image of the operating state of the mobile transmitter 2 from a predetermined fixed position and wirelessly transmits image data and the like acquired by the image capturing. Specifically, the fixed transmitter 3 takes an image of the entire moving range of the inspection target unit 1 and the mobile transmitter 2 and picks up an image, and wirelessly transmits image data and the like acquired by the shooting. Although the details will be described later, the fixed transmitter 3 also performs photographing and wireless transmission at a constant cycle, but uses a different cycle and modulation method from the mobile transmitter 2 described above.

  The receiver 4 is a device that receives and records image data wirelessly transmitted from the mobile transmitter 2 and the fixed transmitter 3. As will be described in detail later, the receiver 4 performs image data by performing demodulation processing and reproduction processing according to each transmitter on the signals wirelessly transmitted from the mobile transmitter 2 and the fixed transmitter 3. The image data is filed and recorded. Note that when the wireless transmission timing by the mobile transmitter 2 and the wireless transmission timing by the fixed transmitter 3 are expected to overlap, the reception processing for the mobile transmitter 2 is preferentially performed.

  The mobile transmitter 2 and the fixed transmitter 3 both transmit a certain amount of data each time. Therefore, the time required for each transmitter to transmit data wirelessly (transmission period) is a predetermined time.

  On the other hand, the pixel number and data rate of the image data wirelessly transmitted by the mobile transmitter 2 are different from the pixel number and data rate of the image data wirelessly transmitted by the fixed transmitter 3. In the first embodiment, for convenience of explanation, the data rate of radio transmission by the mobile transmitter 2 is 4 Mbps, and the data rate of radio transmission by the fixed transmitter 3 is 2 Mbps.

  Hereinafter, the configuration of the receiver 4 will be described with reference to FIG. FIG. 2 is a diagram illustrating a configuration example of the receiver 4. As shown in FIG. 2, the receiver 4 includes an antenna array 4a, an AD arithmetic circuit 4b, a directivity control circuit 4c, a high frequency processing circuit 4d, a reproduction circuit 4e, a data bus 4f, and a memory 4g. A hard disk drive (HD) 4h and a CPU 4k.

  The antenna array 4a, the AD arithmetic circuit 4b, and the directivity control circuit 4c constitute an adaptive array antenna. This adaptive array antenna is a variable directivity antenna for tracking the mobile transmitter 2.

  Specifically, in the adaptive array antenna, the directivity control circuit 4c changes the arithmetic algorithm for the signal received by the antenna array 4a by the AD arithmetic circuit 4b based on an instruction from the CPU 4k. In this way, the directivity of the adaptive antenna is changed, and tracking with respect to the mobile transmitter 2 and direction switching to the fixed transmitter 3 are performed. Since the adaptive array antenna is a known technique, further detailed description is omitted.

  The high frequency processing circuit 4d demodulates the signal output from the AD arithmetic circuit 4b by digital arithmetic processing to generate a baseband signal.

  Since the modulation scheme of the mobile transmitter 2 and the modulation scheme of the fixed transmitter 3 are different, the high-frequency processing circuit 4d determines the transmission timing of the mobile transmitter 2 and the transmission timing of the fixed transmitter 3. At the same time, the demodulation processing is performed by switching the contents of the digital arithmetic processing. This switching instruction is transmitted from the CPU 4k to the high frequency processing circuit 4d through the data bus 4f.

  The reproduction circuit 4e reproduces the baseband signal output from the high frequency processing circuit 4d. As shown in FIG. 2, the reproduction circuit 4e includes a timing generation circuit 4e1, a frequency synchronization circuit 4e2, a phase synchronization circuit 4e3, and a data latch circuit 4e4.

  More specifically, in the reproduction circuit 4e, the data latch circuit 4e4 latches the image data in the input baseband signal in units of bits based on the reproduction clock output from the phase synchronization circuit 4e3. After data is created and the bit data is collected into word data, the word data is collected into block unit data and output.

  The image data output from the data latch circuit 4e4 is sequentially stored in the memory 4g via the data bus 4f, and is filed together for one frame and stored in the HD 4h. The image data thus filed and stored in the HD 4h is separately subjected to image processing by the CPU 4k and used for inspection processing on the inspection target unit 1.

  The directivity control of the adaptive array antenna with respect to the mobile transmitter 2 is performed by the CPU 4k performing image processing on the image data of the fixed transmitter 3 and detecting the position of the mobile transmitter 2 based on the image processing result. This is done by determining the pointing direction.

  By the way, the baseband signal generated by the harmonic processing 4d is also output to the timing generation circuit 4e1 included in the reproduction circuit 4e. The timing generation circuit 4e1 detects a synchronization pattern in the baseband signal, outputs a first synchronization pattern detection signal and a second synchronization pattern detection signal to the phase synchronization circuit 4e3, and detects a second synchronization pattern to the frequency synchronization circuit 4e2. In addition to outputting a signal, a reproduction timing signal is output to the data latch circuit 4e4 from the detection timing of the synchronization pattern.

  The reproduction timing signal is used for setting the processing timing of the processing performed by the data latch circuit 4e4, that is, the above-described “processing for creating word data from bit data and creating block unit data from word data”.

  The frequency synchronization circuit 4e2 creates a baseband clock from the second synchronization pattern detection signal output from the timing generation circuit 4e1.

  Note that, as described above, the frequency of the baseband clock differs between the case of receiving a signal wirelessly transmitted from the mobile transmitter 2 and the case of receiving a signal wirelessly transmitted from the fixed transmitter 3. Accordingly, an instruction from the CPU 4k is transmitted to the frequency synchronization circuit 4e2 through the data bus 4f in accordance with the transmitter that is the transmission source of the signal related to the reception process. Details of the processing by the frequency synchronization circuit 4e2 will be described later.

  The phase synchronization circuit 4e3 generates a reproduction clock from the first synchronization pattern detection signal, the second synchronization pattern detection signal, and the baseband clock.

  Various techniques for determining the phase of the recovered clock from the synchronization pattern detection signal have been proposed. As a representative technique, for example, a synchronization pattern detection signal is generated by matching the data sampled with a clock having a frequency that is an integral multiple of the data rate with a synchronization pattern, and the detection width and detection phase of the synchronization pattern detection signal are generated. A technique of determining the recovered clock phase based on the above can be mentioned. This technique is also used in the first embodiment.

  Specifically, in the wireless communication system according to the first embodiment, since the data rate of the mobile transmitter 2 is 4 Mbps and the data rate of the fixed transmitter 3 is 2 Mbps, it is 12 times the data rate. Sampling is performed using the frequency clock, and the phase of the recovered clock is selected from the 12 divided phases. For this reason, as the frequency of the baseband clock, 48 MHz is used in the reception processing of the signal wirelessly transmitted from the mobile transmitter 2, and 24 MHz is used in the reception processing of the signal wirelessly transmitted from the fixed transmitter 3. I use it.

  Here, the selection of the phase of the recovered clock is not performed until the next synchronization pattern is detected. Therefore, the phase accuracy of the recovered clock during that time is determined by the frequency difference between the frequency of the baseband clock divided by 12 and the data rate of the mobile transmitter 2 or the data rate of the fixed transmitter 3.

  In the first embodiment, the frequency of the baseband clock is adjusted by measuring the detection interval of the synchronization pattern detection signal. Hereinafter, a method of adjusting the frequency of the baseband clock will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a timing chart relating to reception processing of a signal wirelessly transmitted from the mobile transmitter 2.

  As shown in FIG. 3, wireless transmission by the mobile transmitter 2 is performed periodically in units of one frame. Here, as shown in an enlarged manner in FIG. 3, the reception process corresponding to one transmission period has the following configuration. That is, as the baseband signal, a first synchronization pattern (first unique word; UW1) that does not appear elsewhere in the transmission data is arranged at the beginning of the frame, and then the unique information of the mobile transmitter 2 is used. Certain terminal specific information is arranged to form the first block, and a plurality of blocks each made up of the second synchronization pattern (second unique word; UW2) and image data are arranged to form one frame.

  Here, the synchronization pattern detection signal is output when the patterns match as described above. For this reason, as shown in FIG. 3, the last one bit period of the synchronization pattern detection signal is the output period.

  The frequency of the baseband clock is adjusted by measuring the interval between the synchronization pattern detection signals. The time from the time of detection of the first second synchronization pattern shown in FIG. 3 (time (b)) to the time of detection of the next second synchronization pattern (time (c)) is measured using a baseband clock, The frequency difference is detected by comparing the measurement result with the installation value.

  Specifically, based on the mobile transmitter 2, for example, if one block is composed of 4000 bits of data, considering that the data rate is 4 Mbps, data transfer for one block is not possible. 1 ms is required.

  That is, when the mobile transmitter 2 is used as a reference, the frequency of the baseband clock at the time of reception is 48 MHz, so that 18000 is counted for 48000 clocks. Therefore, if the count value from the detection time of the first second synchronization pattern (time (b)) to the detection time of the next second synchronization pattern (time (c)) is, for example, 48002, the mobile transmitter 2 is turned on. As a reference, the frequency of the baseband clock is 48.002 MHz. In this case, the frequency is synchronized by lowering the frequency by 0.002 MHz. In the example shown in FIG. 3, the frequency is adjusted after the “calculation period” has elapsed, that is, at the time (d).

  By the way, the measurement accuracy of the frequency difference can be increased by extending the measurement period. Specifically, if the synchronization pattern is measured every 10 blocks, for example, the measurement accuracy is 10 times. For example, when the last frequency adjustment in the frame is performed at the time (g), the frequency adjustment value is stored in a register in the frequency synchronization circuit 4e2, and the time immediately before the start of transmission of the next frame ((a) At the time).

  Note that at the time immediately before the start of transmission of the next frame (time (a)), the directivity control of the adaptive array antenna, the demodulation algorithm setting of the high-frequency processing circuit 4d, and the mobile transmitter in the reproduction circuit 4e Switching to processing corresponding to 2 is also performed.

  Hereinafter, a method for selecting the mobile transmitter 2 and the fixed transmitter 3 by the receiver 4 and the frequency adjustment timing before the start of reception will be described with reference to FIG.

  In the wireless communication system according to the first embodiment, the transmission cycle of the mobile transmitter 2 and the transmission cycle of the fixed transmitter 3 are set to predetermined values in advance. Therefore, it is possible to predict the transmission start time of the next frame when the transmission start of the frame is actually detected.

  In this way, using the fact that the transmission start time of the next frame can be predicted, the receiver 4 responds to the transmitter to be received at the timing immediately before the transmission is started by each transmitter. Adjust the frequency.

  Specifically, as in the period from time (h) to time (j) shown in FIG. 4, the frequency before the start of reception is adjusted when the transmission target transmitter changes. On the other hand, when a plurality of frames are continuously received from the same transmitter, for example, during a period from time (j) to time (k), since the adjustment value at the time of reception of the previous frame remains, reception starts. Do not adjust the previous frequency.

  Hereinafter, priority processing when the transmission timing of the mobile transmitter 2 and the transmission timing of the fixed transmitter 3 collide will be described.

  In the wireless communication system according to the first embodiment, priority is given to reception from the mobile transmitter 2. For example, in the period in which the transmission timing is expected to collide (for example, the period from time (j) to time (k) shown in FIG. 4), only the mobile transmitter 2 is set as a transmission target transmitter.

  In the wireless communication system according to the first embodiment, the transmission cycle of the mobile transmitter 2 and the transmission cycle of the fixed transmitter 3 are determined in advance. Therefore, by detecting the transmission timing of the mobile transmitter 2 and the transmission timing of the fixed transmitter 3, it is possible to predict a transmission timing collision with reference to the detection.

  Specifically, for example, when it is predicted that the timing of the next transmission by the fixed transmitter 3 will collide with the transmission timing of the mobile transmitter 2 at time (j) shown in FIG. In the period from the time point to the time point (k), only the mobile transmitter 2 receives the signal.

  Hereinafter, the operation of the receiver 4 immediately after the start of the collision prediction inspection at the transmission timing described above will be described. Information related to the mobile transmitter 2 and the fixed transmitter 3 is input to the receiver 4 at the start of the inspection.

  Immediately after the start of the inspection, the receiver 4 receives a signal wirelessly transmitted from the fixed transmitter 3 that is always fixed, so that the algorithm of the high-frequency processing circuit 4d corresponds to the fixed transmitter 3 and performs a reception process. Do.

  After detecting the transmission timing of the fixed-type transmitter 3 by performing the reception process of the signal wirelessly transmitted from the fixed-type transmitter 3 in this manner, the high-frequency processing circuit 4d is used during the transmission idle period of the fixed-type transmitter 3. Is switched to the mobile transmitter 2 to receive a signal wirelessly transmitted from the mobile transmitter 2 and detect the transmission timing of the mobile transmitter 2.

  After grasping the transmission timings of the mobile transmitter 2 and the fixed transmitter 3 by the above-described processing, processing according to the priority is performed. Therefore, in order to perform processing according to the priority, the algorithm of the high-frequency processing circuit 4d and the operation content of the reproduction circuit 4e are switched as appropriate. With the processing described above, the reception processing for signals wirelessly transmitted from the mobile transmitter 2 and the fixed transmitter 3 immediately after the start of the inspection and the grasping of the transmission timing of those signals are performed.

  FIG. 5 is a diagram illustrating a configuration example of the frequency synchronization circuit 4e2.

  As shown in FIG. 5, the frequency synchronization circuit 4e2 includes a frequency difference detection circuit 4e21, a control value generation circuit 4e22, a control value selection circuit 4e23, a DA conversion circuit 4e24, a voltage control oscillator 4e25, and a frequency division circuit 4e26. And a frequency synchronization control circuit 4e27.

  The frequency difference detection circuit 4e21 is a circuit that obtains the above-described frequency difference by counting the period of the synchronization pattern with a baseband clock. The frequency difference detection signal output from the frequency difference detection circuit 4e21 is input to the control value generation circuit 4e22.

  The control value generation circuit 4e22 generates a next frequency adjustment value based on the current frequency control value and the frequency difference detection signal, and based on this frequency adjustment value, the frequency of the voltage control oscillator 4e25 in the subsequent stage It is a circuit that generates a frequency control value according to the control characteristics. The output (frequency control value) of the control value generation circuit 4e22 is stored in the register of the frequency synchronization control circuit 4e27 and is added to the control value selection circuit 4e23, and then to the DA conversion circuit 4e24 via the control value selection circuit 4e23. The input value is converted into an analog value, and then the frequency is adjusted by the voltage controlled oscillator 4e25.

  Since the frequency of the voltage controlled oscillator 4e25 is controlled around 48 MHz, the frequency dividing circuit 4e26 does not perform frequency dividing processing when receiving a signal wirelessly transmitted from the mobile transmitter 2. On the other hand, the frequency dividing circuit 4e26 switches the frequency of the baseband clock to 24 MHz by performing a frequency dividing process when receiving a signal wirelessly transmitted from the fixed transmitter 3. As described above, the frequency dividing circuit 4e26 switches between 48 MHz and 24 MHz.

  By the way, in the frequency adjustment before the start of reception, the frequency adjustment value stored in the register of the frequency synchronization control circuit 4e27 is output to the control value selection circuit 4e23, and the frequency adjustment is performed based on the frequency adjustment value. When the frequency adjustment during reception is performed, the output of the control value selection circuit 4e23 is switched to the frequency control value output from the control value generation circuit 4e22, and the frequency control is performed using the frequency control value.

  Hereinafter, the configuration and operation of the frequency difference detection circuit 4e21 will be described with reference to FIG.

  FIG. 6 is a diagram illustrating a configuration example of the frequency difference detection circuit 4e21. The frequency difference detection circuit 4e21 includes a counter control circuit 4e211, a counter 4e212, a measurement interval register 4e213, and a subtraction circuit 4e214.

  The counter control circuit 4e211 to which the second synchronization pattern detection signal and the baseband clock are added generates a reset signal for the counter 4e212. Here, a baseband clock is added as a count clock to the counter 4e212, and the detection interval of the second synchronization pattern is counted by the baseband clock by the counter 4e212. The output of the counter 4e212 is applied to the subtraction circuit 4e214.

  In the subtraction circuit 4e214, the value output from the counter 4e212 is subtracted from the value set in the measurement interval register 4e213, and the subtraction result is output as a frequency difference detection signal.

  In the example described with reference to FIG. 3, the output of the counter 4e212 is 48002, and the set value of the measurement interval register 4e213 is 48000. Therefore, in this example, the frequency difference detection signal is 2, and the voltage controlled oscillator 4e25 is controlled so that the frequency is lowered by 0.002 MHz from the current frequency.

  As described above, according to the first embodiment, even when wireless transmission is performed from a plurality of transmission terminal devices, in particular, substantially the same timing from a plurality of transmission terminal devices at substantially the same position. Even when wireless transmission is performed by the receiver terminal device, it is possible to provide a wireless communication system capable of performing frequency adjustment according to the clock frequency of each transmitter terminal device without using a preamble. it can.

  More specifically, for example, accurate frequency adjustment is possible without providing a preamble period and performing so-called frequency pull-in, thereby improving communication efficiency.

  Furthermore, since the reception process according to the priority as described above is performed, if it is predicted that a communication with a high priority is performed during a communication with a low priority, the reception process with a low priority is not performed. Accordingly, since unnecessary reception processing is not performed, power consumption can be reduced.

  Further, since the variable directivity antenna is used as described above, it is possible to perform good reception processing even when the wireless transmission terminal moves like the mobile transmitter 2, and a compact antenna. Configuration is possible.

  Further, in the detection based on the synchronization pattern as described above, it is possible to acquire information related to the frequency even when the frequency error is large. Furthermore, according to the wireless communication system according to the first embodiment, it is possible to create a frequency adjustment value at a frequency adjustment timing before starting reception. Further, as described above, according to the radio communication system according to the first embodiment, since it can be configured to include radio transmission terminals using different modulation schemes, the applicable range is expanded.

[Second Embodiment]
The wireless communication system according to the second embodiment of the present invention will be described below with reference to the drawings. In order to avoid duplication of explanation, only differences from the radio communication system according to the first embodiment will be described. One of the main differences between the radio communication system according to the first embodiment and the radio communication system according to the second embodiment is that the configuration of the reproduction circuit provided in the receiver of the radio communication system and the frequency difference due to the reproduction circuit This is the adjustment method. This will be specifically described below.

  FIG. 7 is a diagram illustrating a configuration example of the reproduction circuit 4e ′ of the receiver 4 ′ included in the wireless communication system according to the second embodiment. As shown in FIG. 7, the difference from the reproduction circuit 4e in the first embodiment described above is the configuration and operation of the phase synchronization circuit 4e3 ′ and the frequency synchronization circuit 4e2 ′.

  The frequency synchronization circuit 4e2 ′ calculates a frequency difference based on a difference between representative phases in different block periods, and performs frequency adjustment based on the frequency difference.

  The phase synchronization circuit 4e3 ′ detects the edge phase of the baseband signal during one block period, calculates the representative phase based on the detection result, and adjusts the phase of the recovered clock based on the calculation result.

  Hereinafter, a method of adjusting the frequency of the baseband clock will be described with reference to FIG. FIG. 8 is a diagram illustrating an example of a timing chart regarding processing of a reception target of a signal wirelessly transmitted from the mobile transmitter 2.

  The time point (a) shown in FIG. 8 is a time point immediately before transmission of one frame is started. Similar to the first embodiment, the frequency adjustment before the reception start is performed using the frequency adjustment value detected during the reception of the previous frame at the time point (a).

  Subsequently, the representative phase is detected in the period from time (b) to time (c) and in the period from time (c) to time (d). The detection of the representative phase is also performed for all blocks because it is also used for adjusting the phase of the recovered clock. However, for convenience of explanation, the case where the representative phase in the period from (b) to (c) and (c) to (d) is used in the generation of the frequency adjustment value will be described as an example. .

  In the detection of the representative phase, the center phase of the edge distribution of the baseband signal in one block period is detected using a baseband clock, and the frequency difference is detected from the shift amount of the center phase between blocks.

  Specifically, for example, if one block is composed of 4000 bits of data as in the first embodiment, the data rate is 4 Mbps, and 1 ms is required for data transfer for one block. When receiving a signal transmitted wirelessly from the mobile transmitter 2, the frequency of the baseband clock 2-42 is 48 MHz and the data rate is 4 Mbps, so detection is performed with a phase accuracy obtained by dividing one bit period into twelve. .

  For example, when the representative phase in the period from (b) to (c) is the phase “3” and the representative phase in the period from (c) to (d) is the phase “5”, the baseband The clock is counted up by 2 counts compared to the clock of the mobile transmitter 2 during one block period, and a frequency difference = 2 is output.

  Here, since the number of counts in one block period of the baseband clock in the case of complete frequency synchronization is 48000 counts, the count value in one block period is 48002 in the above-described state.

  This is because when the clock of the mobile transmitter 2 is 48 MHz, the frequency of the baseband clock is 48.002 MHz, and the frequency is synchronized by lowering the frequency by 0.002 MHz.

  The processing described above is performed during the period from the time point (d) to the time point (e), the frequency adjustment value is calculated, and the frequency adjustment process during reception is performed at the time point (e).

  In the example described above, the comparison of the representative phase is performed between adjacent blocks. However, if the frequency difference becomes small and the accuracy of the frequency adjustment value needs to be increased, the interval between the blocks to be compared is increased. Of course, it is possible to cope with this.

  When the last frequency adjustment in the frame is performed at the time (g), the frequency adjustment value is stored in a register in the frequency synchronization circuit 4e2 ′, and the time immediately before the start of transmission of the next frame ((a ) Time) is reset.

  Hereinafter, the calculation of the representative phase by the phase synchronization circuit 4e3 ′ will be described in detail with reference to FIG. FIG. 9 is a diagram illustrating a time chart for explaining the edge phase detection method of the baseband signal.

  The measurement window is created by counting the baseband clock every period corresponding to one bit width of the baseband signal. In the second embodiment, the frequency of the baseband clock is set to 12 times the bit rate. Therefore, the measurement window is a period in which 12 baseband clocks are counted as shown in FIG.

  For detection of the representative phase, the measurement window is divided into 12 sub-windows, the sub-window position where the edge of the baseband signal is located is detected, and the detection result is accumulated for one block period to create a histogram. However, the histogram is subjected to arithmetic processing.

  FIG. 10 is a diagram illustrating a configuration example of the phase synchronization circuit 4e3 ′. As shown in FIG. 10, the phase synchronization circuit 4e3 ′ includes an edge extraction circuit 4e31, an AND gate block 4e32, an edge number counter block 4e33, a histogram calculation circuit 4e34, a subwindow generation circuit 4e35, and a timing control circuit 4e36. And a clock phase selection circuit 4e37.

  The edge extraction circuit 4e31 is a circuit that generates an edge signal by detecting both rising and falling edges of a baseband signal. The edge signal generated by the edge extraction circuit 4e31 is input to the AND gate block 4e32.

  The sub-window generation circuit 4e35 divides one bit period into 12 sub-window periods, and 12 gate signals (first phase_gate signal to twelfth phase_gate signal) that become Hi level for each sub-window period. ).

  The AND gate block 4e32 uses the edge signal and the gate signal to detect in which phase the edge signal is generated, and counts up signals (first phase_) to the edge number counter corresponding to each partial phase. This is a circuit for supplying a count-up signal to a twelfth phase_count-up signal. The AND gate block 4e32 is configured by combining 12 AND gates with two inputs. One input is an edge signal output from the edge extraction circuit 4e31, and the other input is a subwindow generation circuit 4e35. The gate signal is added. The output of each AND gate is supplied to the first edge number counter to the twelfth edge number counter in the edge number counter block 4e33.

  The edge number counter block 4e33 is a circuit including twelve edge number counters (a first edge number counter to a twelfth edge number counter) corresponding to the number of subwindows. The edge number counter block 4e33 creates a histogram of the edge phase of the baseband signal by counting the number of edges for each subwindow.

  The histogram calculation circuit 4e34 is a circuit that performs calculation processing based on the histogram generated by the edge number counter block 4e33 and generates a representative phase by the calculation processing.

  The clock phase selection circuit 4e37 is a circuit that generates a reproduction clock. The clock phase selection circuit 4e37 adjusts the phase of the recovered clock using the baseband clock, the representative phase, and the control signal output from the timing control circuit 4e36.

  The timing control circuit 4e36 is a circuit that creates a control signal to be supplied to each circuit in the phase synchronization circuit 4e3 ′ based on the baseband clock, the first synchronization pattern detection signal, and the second synchronization pattern detection signal.

  Note that the timing control circuit 4e36 also has a function of creating an initial phase adjustment signal for adjusting the phase of the recovered clock based on the first synchronization pattern detection signal and the second synchronization pattern detection signal.

  This initial phase adjustment signal is a signal for adjusting the phase of the reproduction clock during a period in which phase adjustment based on the baseband signal edge information is not possible (first block period), and includes the first synchronization pattern detection signal and the second synchronization pattern detection signal. Created from phase information.

  FIG. 11 is a diagram illustrating a configuration example of the frequency synchronization circuit 4e2 ′. As shown in FIG. 11, the frequency synchronization circuit 4e2 includes a frequency difference detection circuit 4e21 ′, a control value generation circuit 4e22, a control value selection circuit 4e23, a DA conversion circuit 4e24, a voltage control oscillator 4e25, and a frequency divider circuit. 4e26 and a frequency synchronization control circuit 4e27 ′. As shown in FIG. 11, the configuration and operation of the frequency difference detection circuit 4e21 ′ and the frequency synchronization control circuit 4e27 ′ are different from the frequency synchronization circuit 4e2 in the first embodiment described above.

  The frequency difference detection circuit 4e21 ′ is a circuit that generates a frequency difference detection signal that is a difference between two representative phases. The point that the frequency difference detection signal is generated from the representative phase in this way is different from the operation / function of the frequency difference detection circuit 4e21 ′ in the first embodiment.

  The frequency synchronization control circuit 4e27 ′ is a circuit that generates a control signal in the frequency synchronization circuit 4e2 ′. Unlike the frequency synchronization control circuit 4e27 in the first embodiment, the frequency synchronization control circuit 4e27 ′ in the second embodiment generates a phase buffer control signal and outputs it to the frequency difference detection circuit 4e21 ′.

  Hereinafter, the configuration of the frequency difference detection circuit 4e21 ′ will be described with reference to FIG. FIG. 12 is a diagram illustrating a configuration example of the frequency difference detection circuit 4e21 ′. As shown in FIG. 12, the frequency difference detection circuit 4e21 ′ includes a first data phase buffer 4e211 ′, a second data phase buffer 4e212 ′, and a subtraction circuit 4e213 ′.

  The representative phase and the phase buffer control signal are added to the first data phase buffer 4e211 '. The first data phase buffer 4e211 'captures the representative phase at the timing indicated by the phase buffer control signal and outputs it to the second data phase buffer 4e212' and the subtraction circuit 4e213 '.

  The phase buffer control signal is a signal for instructing timing for capturing a representative phase for frequency difference detection. For example, in the operation example shown in FIG. 8, the phase buffer control signal indicates the timings at the time (c) and the time (d).

  That is, in this case, at the timing of (c), the representative phase of the period of the data phase measurement period (1) shown in FIG. 8, that is, the period of (b) to (C) is the first data phase buffer. 4e211 'and the contents of the first data phase buffer 4e211' are moved to the second data phase buffer 4e212 'at the timing of the next time point (d), that is, the period of the data phase measurement period (2), that is, (c) The representative phase of the period from the time point to the time point (d) is stored in the first data phase buffer 4e211 '.

  The frequency difference detection signal, which is the output of the subtraction circuit 4e213 ', is obtained from the value of the representative phase in the period of the data phase measurement period (2) shown in FIG. This is a value obtained by subtracting the value of the representative phase in the period of the phase measurement period (1), that is, the period from the time point (b) to the time point (c).

  As described above, according to the second embodiment, it is possible to provide a radio communication system having the following effects in addition to the same effects as the radio communication system according to the first embodiment.

  That is, according to the radio communication system according to the second embodiment, after the polarity change positions in the baseband signal are accumulated for a predetermined measurement period, the arithmetic processing is performed to generate representative phase information, and the predetermined measurement period Since the representative phase information is generated again after the elapse of time and the information on the frequency is generated based on the two pieces of representative phase information obtained by these, the measurement error due to the reception state can be further reduced. That is, more accurate frequency information can be obtained.

[Third embodiment]
Hereinafter, a radio communication system according to a third embodiment of the present invention will be described with reference to the drawings. In order to avoid duplication of explanation, only differences from the radio communication system according to the first embodiment will be described. One of the main differences between the radio communication system according to the first embodiment and the radio communication system according to the third embodiment is that the radio communication system according to the third embodiment includes a plurality of mobile transmitters 2. This is a particularly effective radio communication system. This will be specifically described below.

  FIG. 13 is a diagram illustrating a configuration example of a wireless communication system according to the third embodiment. As shown in FIG. 13, the point having a plurality of mobile transmitters 2-1 and 2-2 is one of the main differences from the wireless communication system according to the first embodiment described above.

  Note that the mobile transmitters 2-1 and 2-2 both move autonomously around the inspection object 1 and take images at regular intervals in the same manner as the mobile transmitter 2 in the first embodiment. In addition to wireless transmission of data, infrared imaging is performed. Here, regarding the priority mentioned above, it is assumed that the mobile transmitter 2-2 is set highest.

  The receiver 4 ″ is different from the receiver 4 in the first embodiment in the following points. That is, the receiver 4 ″ in the third embodiment includes an antenna unit 4a ′ configured by combining five unidirectional antennas 4a1 to 4a5), and a plurality of reproduction circuits 40e1 and 40e2. Is different from the receiver 4 in the first embodiment.

  FIG. 14 is a diagram illustrating a configuration example of the receiver 4 ″. As shown in FIG. 14, the receiver 4 ″ includes an antenna unit 4a ′ for tracking the mobile transmitters 2-1, 2-2, high-frequency processing circuits 4d1, 4d2, and reproduction circuits 40e1, 40e2. A data bus 4f, a memory 4g, an HD 4h, and a CPU 4k.

  The antenna unit 4a ′ includes five unidirectional antennas 4a1 to 4a5 and an antenna selection circuit that selects and outputs two unidirectional antennas from the five unidirectional antennas 4a1 to 4a5. 4a7 and a switching control circuit 4a8 for controlling the operation of the antenna selection circuit 4a7 based on an instruction from the CPU 4k.

  The high-frequency processing circuits 4d1 and 4d2 are both circuits that demodulate the high-frequency signal output from the antenna unit 4a ′. These high-frequency processing circuits 4d1 and 4d2 have the same function as the high-frequency processing circuit 4d in the first embodiment, and also have a function of first performing AD conversion on an input signal to convert it into a digital signal. This is because the signal output from the antenna unit 4a ′ is a high-frequency signal, and thus it is necessary to perform AD conversion on the high-frequency signal to convert it to a digital signal.

  Note that demodulation processing by digital arithmetic processing performed after conversion to a digital signal is the same as that of the high-frequency processing circuit 4d in the first embodiment. Further, the demodulation processing algorithm of the high-frequency processing circuits 4d1 and 4d2 is appropriately changed according to the type of the transmitter that is the transmission source of the signal to be received, similarly to the high-frequency processing circuit 4d in the first embodiment.

  Both the reproducing circuits 40e1 and 40e2 have the same function as the reproducing circuit 4e in the first embodiment. Here, the output signal from the high frequency processing circuit 4d1 is input to the reproduction circuit 40e1, and the output signal from the high frequency processing circuit 4d2 is input to the reproduction circuit 40e2, and the reproduction processing is performed. Note that the reproduction processing by the reproduction circuits 40e1 and 40e2 is the same processing as the reproduction processing by the reproduction circuit 4e in the first embodiment.

  Hereinafter, with reference to FIG. 13 and FIG. 14, the operation of the receiver 4 ′ for wireless transmission by the mobile transmitters 2-1 and 2-2 and the fixed transmitter 3 will be described.

  In the example of the positional relationship shown in FIG. 13, the signal transmitted wirelessly by the mobile transmitter 2 is received most strongly by the unidirectional antenna 4a2, and the signal transmitted wirelessly by the fixed transmitter 3 is unidirectional. The antenna 4a5 receives the strongest signal, and the unidirectional antenna 4a1 receives the signal transmitted wirelessly by the mobile transmitter 2-2.

  Here, as to which unidirectional antenna is used to receive a signal wirelessly transmitted from each transmitter, the CPU 4k determines whether or not the mobile transmitter 2-based on the image captured by the fixed transmitter 3. The optimal antenna is selected by determining the positions 1 and 2-2.

  The antenna selection circuit 4a7 is based on an instruction from the CPU 4k via the switching control circuit 4a8, and in the example of the positional relationship shown in FIG. 13, any two of the unidirectional antennas 4a1, 4a2, 4a5 The unidirectional antenna and the high frequency processing circuit are connected so that the output of the directional antenna is input to the high frequency processing circuits 4d1 and 4d2, respectively.

  Hereinafter, with reference to FIG. 15, the selection operation of the mobile transmitters 2-1 and 2-2 and the fixed transmitter 3 by the receiver 4 ″ and the frequency adjustment operation before the reception start after the selection operation will be described. . FIG. 15 is a diagram illustrating an example of a timing chart of a reception destination selection operation by the receiver 4 ″.

  That is, when the transmission periods of the mobile transmitters 2-1 and 2-2 and the fixed transmitter 3 are the example shown in FIG. 15, the receiver 4 ″ selects the receiver of the receiver by the following method.

(Method 1) The reproduction circuit 40e2 performs reproduction processing on a signal wirelessly transmitted by a transmitter having the highest priority (in this example, the mobile transmitter 2-2).

(Method 2) The reproduction circuit 40e1 performs reproduction processing on a signal wirelessly transmitted by a transmitter having the second highest priority (in this example, the mobile transmitter 2-1).

(Method 3) With regard to the reproduction process for the signal wirelessly transmitted by the third and subsequent priority transmitters (in this example, the fixed type transmitter 3), if the reproduction circuit 40e1 has a free space for performing the reproduction process. If the reproduction circuit 40e1 has no space and the reproduction circuit 40e2 has a space, the regeneration circuit 40e2 performs the processing. Note that if the reproduction circuit 40e2 has no free space, reception to the transmitter is not performed.

  When the operation of selecting a receiver as a receiver is performed by such a method, for example, the operation is represented by a timing chart shown in FIG.

  That is, the regeneration circuit 40e1 preferentially processes the transmission signal of the mobile transmitter 2, and transmission from the mobile transmitter 2 is not predicted as in the period from (c) time to (d) and In a period during which transmission from the fixed transmitter 3 is predicted, the transmission signal of the fixed transmitter 3 is processed.

  Further, the regeneration circuit 40e2 preferentially processes the transmission signal of the mobile transmitter 2-2, and the transmission from the mobile transmitter 2-2 is performed during the period from the time point (e) to the time point (f). When the prediction circuit 40e1 is not predicted and there is no vacancy in processing the transmission signal from the fixed transmitter 3, the transmission signal from the fixed transmitter 3 is processed.

  Further, when the transmitter to be processed in each reproduction circuit is switched, as shown in FIG. 15, the frequency adjustment of the baseband clock (frequency adjustment before the start of reception) is performed immediately before the transmission from the transmitter after the switching is started. Is called.

  Hereinafter, the exchange of the frequency adjustment value between the reproduction circuits will be described.

  In the period from the time point (e) to the time point (f) in the time chart shown in FIG. 15, the reproduction circuit 40 e 2 performs a reproduction process on the fixed transmitter 3. In this case, as the frequency adjustment value used in the frequency adjustment before reception start performed at the time (e), the frequency adjustment value obtained by the reproduction processing performed by the reproduction circuit 40e1 during the period from the time (c) to the time (d). Is used. Specifically, the frequency adjustment value is transferred according to the following processing procedure.

  First, the frequency adjustment value performed at the end of the period from the time point (c) to the time point (d) is stored in the frequency synchronization control circuit 4e27 of the reproduction circuit 40e1. The frequency adjustment value is read by the CPU 4k and stored in the memory 4g. Subsequently, the frequency adjustment value is read from the memory 4g by the CPU 4k immediately before the time point (e) and written to the frequency synchronization control circuit 4e27 of the reproduction circuit 40e2. Finally, the frequency adjustment before the start of reception is performed by the frequency adjustment value at time (e).

  Also in the frequency adjustment before reception start performed at time (g) in FIG. 15, the frequency adjustment value obtained during the period from time (e) to time (f) by the same processing procedure as that described above is the reproduction circuit 40e1. Used for frequency adjustment.

  The frequency adjustment value is transferred between the reproduction circuits by the processing procedure described above.

  Note that the details of the frequency adjustment processing before the start of reception are as described in the first embodiment, and thus the description thereof is omitted here.

  As described above, according to the third embodiment, it is possible to provide a wireless communication system having the following effects in addition to the same effects as the wireless communication system according to the first embodiment.

  That is, according to the wireless communication system according to the third embodiment, since the antenna to be used for reception can be selected from the plurality of unidirectional antennas 4a1 to 4a5, the mobile wireless devices 2-1 and 2- Even when the wireless transmission terminal device moves as shown in FIG. 2, it is possible to perform good reception processing, and directivity control can be easily performed. In addition, it is possible to easily cope with a case where reception from a plurality of wireless transmission terminal devices is performed simultaneously. Furthermore, since the receiver 4 is provided with a plurality of reproduction circuits 40e1 and 40e2, application to a wireless communication system including a large number of wireless transmission terminal devices becomes easier.

  The present invention has been described based on the first to third embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications and applications can be made within the scope of the gist of the present invention. Of course, it is possible.

  Further, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

(Appendix)
The invention having the following configuration can be extracted from the specific embodiment.

(1)
A receiving circuit for receiving and processing signals wirelessly transmitted by a plurality of wireless transmission terminal devices each performing wireless transmission at a predetermined transmission cycle,
Based on the wireless transmission period and transmission timing of the wireless transmission terminal device, a clock adjustment timing setting unit that estimates a time point immediately before the start of wireless transmission by the wireless transmission terminal device and sets the time point as a clock preparation timing;
A frequency adjustment value determining means for determining a frequency adjustment value in frequency adjustment of a clock signal used for the reception processing with reference to a clock signal component included in a signal wirelessly transmitted from the wireless transmission terminal device;
Frequency adjustment execution means for executing frequency adjustment of the clock signal by the frequency adjustment value at the clock preparation timing;
A receiving circuit comprising:

(Corresponding embodiment)
The embodiment relating to the receiving circuit described in (1) corresponds to the first to third embodiments. In these embodiments, the wireless transmission terminal device corresponds to, for example, mobile transmitters 2, 2-1, 2-2, and fixed transmitter 3, and the reception circuit includes, for example, the reproduction circuits 4, 4 ′, 4 ″ corresponds.

1 is a diagram showing an example of a system configuration when a wireless communication system according to a first embodiment of the present invention is applied to a nondestructive inspection system. The figure which shows the example of 1 structure of a receiver. The figure which shows an example of the timing chart regarding the process of the receiving object of the signal transmitted by radio | wireless from the mobile transmitter. The figure which shows the selection of the transmission object transmitter by a receiver, and the frequency adjustment timing before a reception start. The figure which shows the example of 1 structure of a frequency synchronous circuit. The figure which shows the example of 1 structure of a frequency difference detection circuit. The figure which shows the example of 1 structure of the reproducing | regenerating circuit of the receiver with which the radio | wireless communications system which concerns on 2nd Embodiment of this invention comprises. The figure which shows an example of the timing chart regarding the process of the receiving object of the signal transmitted by radio | wireless from the mobile transmitter. The figure which shows the time chart explaining the edge phase detection method of a baseband signal. The figure which shows the example of 1 structure of a phase-locked loop. The figure which shows the example of 1 structure of a frequency synchronous circuit. The figure which shows the example of 1 structure of a frequency difference detection circuit. The figure which shows the example of 1 structure of the radio | wireless communications system which concerns on 3rd Embodiment of this invention. The figure which shows the example of 1 structure of a receiver. The figure which shows an example of the timing chart of the receiver selection operation | movement by a receiver.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 2,2-1,2-2 ... Mobile transmitter, 3 ... Fixed type transmitter, 4 ... Receiver, 4a ... Antenna array, 4b ... AD arithmetic circuit, 4c ... Directivity control circuit, 4d ... High frequency processing circuit 4e ... reproduction circuit, 4f ... data bus, 4g ... memory, 4h ... hard disk drive, 4k ... CPU, 4e1 ... timing generation circuit, 4e2 ... frequency synchronization circuit, 4e3 ... phase synchronization circuit, 4e4 ... data latch circuit, 4h ... HD, 4d ... harmonic processing, 4e21 ... frequency difference detection circuit, 4e22 ... control value generation circuit, 4e23 ... control value selection circuit, 4e24 ... DA conversion circuit, 4e25 ... voltage controlled oscillator, 4e26 ... frequency divider circuit, 4e27 ... frequency Synchronization control circuit, 4e211 ... counter control circuit, 4e212 ... counter, 4e213 ... measurement interval register 4e214 ... subtraction circuit, 4e31 ... edge extraction circuit, 4e32 ... AND gate block, 4e33 ... edge number counter block, 4e34 ... histogram operation circuit, 4e35 ... subwindow generation circuit, 4e36 ... timing control circuit, 4e37 ... clock phase selection circuit 4e211 '... 1st data phase buffer, 4e212' ... 2nd data phase buffer, 4e213 '... Subtraction circuit, 4a ... Antenna unit, 4d1, 4d2 ... High frequency processing circuit, 4a7 ... Antenna selection circuit, 4a8 ... Switching control circuit, 4d1, 4d2 ... high frequency processing circuit, 4a1 to 4a5 ... unidirectional antenna, 4, 4 ', 4 "... reproduction circuit, 40e1, 40e2 ... reproduction circuit.

Claims (9)

A wireless communication system comprising: a plurality of wireless transmission terminal devices each performing wireless transmission at a predetermined transmission cycle; and a receiving terminal device that receives a signal wirelessly transmitted by the wireless transmission terminal device,
The receiving terminal device includes an antenna for receiving a signal wirelessly transmitted by the wireless transmitting terminal device, and a baseband signal generating means for generating a baseband signal by performing a demodulation process on the signal received by the antenna And a reproducing circuit for reproducing communication data based on the baseband signal,
The regeneration circuit is
Based on the baseband signal, frequency information generating means for generating frequency information related to frequency adjustment of a clock signal used for the reproduction processing of the baseband signal;
Based on the start timing of wireless transmission by the wireless transmission terminal device and the predetermined transmission cycle, a time point immediately before the start of wireless transmission by the wireless transmission terminal device is estimated, and the time point is set as a frequency adjustment timing before reception start. A frequency adjustment timing setting means before starting reception;
Frequency adjustment means for performing frequency adjustment of the clock signal based on the frequency information at the frequency adjustment timing before the start of reception;
A wireless communication system comprising: The antenna is an antenna whose reception characteristics can be changed, and the baseband signal includes terminal identification information set for each of the wireless transmission terminal devices,
The receiving terminal device
Priority detecting means for detecting a communication priority set for each of the wireless transmission terminal devices according to the terminal identification information included in the baseband signal;
Predicted transmission period information generating means for generating predicted transmission period information indicating a start time and a transmission period of the next radio transmission based on the start timing of the radio transmission by each of the radio transmission terminal devices and the predetermined transmission cycle;
Based on the communication priority and the predicted transmission period information, determine a wireless transmission terminal device to be subjected to reception processing next, so as to be suitable for reception of signals wirelessly transmitted by the determined wireless communication terminal device, A reception characteristic changing means for changing the reception characteristic of the antenna in accordance with the frequency adjustment timing before the start of reception;
The wireless communication system according to claim 1, comprising:   The wireless communication system according to claim 2, wherein the antenna is a variable directivity antenna, and the change of the reception characteristic is directivity control of the variable directivity antenna.   The antenna is an antenna unit including a plurality of unidirectional antennas, and the reception characteristics are changed by wireless transmission from a plurality of unidirectional antennas by a wireless transmission terminal device to be subjected to reception processing next. The wireless communication system according to claim 2, wherein the wireless communication system is a process of selecting a unidirectional antenna suitable for receiving a received signal. The receiving terminal device has a plurality of the reproduction circuits,
According to the communication priority, the predicted transmission period information, and the predicted operating states of the plurality of reproduction circuits, each of the reproduction circuits determines a radio transmission terminal device to be subjected to reception processing next. The wireless communication system according to claim 2.   The frequency information generating means detects a frequency difference by comparing a detection period of a synchronization pattern periodically included in the baseband signal with a counter period in the receiving terminal device, The radio communication system according to claim 1, wherein the frequency information is generated based on a detection result.   The frequency information generating means performs a representative phase measurement operation for generating representative phase information by performing arithmetic processing after accumulating the polarity change positions in the baseband signal for a predetermined measurement period, with a predetermined measurement interval period. The radio communication system according to claim 1, wherein the frequency information is generated based on representative phase information obtained by each representative phase measurement operation, which is executed a plurality of times.   The reproduction circuit adjusts the frequency of the clock signal during the reception period of the signal wirelessly transmitted by the wireless transmission terminal device as the frequency adjustment during reception, and at the last reception frequency adjustment timing during the reception period. The radio communication system according to claim 1, wherein the frequency adjustment value is a frequency adjustment value in frequency adjustment performed at a frequency adjustment timing before the start of reception in the next reception process. The reproduction circuit responds by performing the demodulation processing by digital arithmetic processing and changing the contents of the digital arithmetic processing for a plurality of modulation signals, and the reproduction circuit responds to the frequency adjustment timing before the reception start. The wireless communication system according to claim 2, wherein the contents of the digital arithmetic processing are changed so as to be suitable for reception of a signal wirelessly transmitted by a wireless transmission terminal device to be subjected to reception processing next.

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