JP2010073851A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the heat dissipation performance of a semiconductor chip without causing the enlargement of a heat-dissipation member, in a semiconductor device having the semiconductor chip in the multilayer board composed of resin. <P>SOLUTION: This semiconductor device includes: a multi-layer substrate 10 which laminates resin layers 1 to 8 formed of a plurality of resins; and a plate-like semiconductor chip 20 formed in the multi-layer substrate 10. One plate face 21 which is a face perpendicular to a thickness direction of the semiconductor chip 20 of a surface of the semiconductor chip 20 is thermally connected to a heat dissipation member 30 for dissipating the heat of the semiconductor chip 20. A heat dissipation layer 15 connected thermally to the side 23 which is a face extended in the thickness direction of the semiconductor chip 20 of the surface of the semiconductor chip 20 is formed in the multi-layer substrate 10. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is provided inside a multilayer substrate made of resin, and more particularly to improvement in heat dissipation of the semiconductor chip.

  Conventionally, as this type of semiconductor device, a device including a multilayer substrate in which a plurality of resin layers made of a resin are laminated and a semiconductor chip provided inside the multilayer substrate has been proposed (for example, Patent Document 1).

Here, in order to ensure heat dissipation of the semiconductor chip, a conductive film or a heat sink is conventionally provided on one plate surface, which is a surface orthogonal to the thickness direction of the semiconductor chip, of the surface of the semiconductor chip that is generally plate-shaped. Etc. are thermally connected.
JP 2002-329803 A

  However, in the past, since the heat dissipation member is only thermally connected to one plate surface of the semiconductor chip, it is not possible to increase the heat capacity of the heat dissipation member with this conventional configuration in order to further improve heat dissipation. This leads to an increase in the size of the heat dissipating member, which is not preferable.

  Moreover, in the said patent document 1, although the heat radiating member shall consist of metal foils, such as Cu foil, the thickness of this metal foil is a very thin thing of about 18-35 micrometers normally, for example, and its heat capacity is small. Therefore, for example, there is a problem that a transient thermal resistance of 10 msec to 100 msec becomes large and cannot be applied to an in-vehicle device or the like in which a large amount of power is instantaneously applied.

  The present invention has been made in view of the above problems, and in a semiconductor device in which a semiconductor chip is provided inside a multilayer substrate made of resin, the heat dissipation of the semiconductor chip is improved without causing an increase in the size of the heat dissipation member. The purpose is to let you.

  In order to achieve the above object, according to the first aspect of the present invention, a side surface that is a surface extending in the thickness direction of the semiconductor chip (20) among the surfaces of the semiconductor chip (20) is provided inside the multilayer substrate (10). 23) is provided with a heat dissipation layer (15) thermally connected.

  According to this, in addition to heat radiation from the one plate surface (21) of the semiconductor chip (20) being performed by the heat radiating member (30) as in the prior art, further, from the side surface (23) of the semiconductor chip (20). Since heat dissipation is performed by the heat dissipation layer (15), the heat dissipation path can be increased, so that the heat dissipation performance of the semiconductor chip (20) can be improved without increasing the size of the heat dissipation member.

  Here, in the invention according to claim 2, the semiconductor chip (20) is arranged in a state in which the thickness direction thereof is along the lamination direction of the resin layers (1 to 8) in the multilayer substrate (10), The multi-layer substrate (10) is provided with a recess (11) that is recessed along the laminating direction of the resin layers (1 to 8). The semiconductor chip (20) is accommodated in the recess (11), and the recess (11) Resin which makes a side surface and the side surface (23) of a semiconductor chip (20) face each other and provides a heat dissipation layer (15) between a plurality of resin layers (1 to 8) and constitutes a recess (11) It is exposed to the side surface of the recess (11) from between the layers (1 to 4), and the exposed portion of the heat dissipation layer (15) and the side surface (23) of the semiconductor chip (20) are brought into contact in the recess (11). It is characterized by thermal connection.

  According to this, the thermal connection between the side surface (23) of the semiconductor chip (20) and the heat dissipation layer (15) can be appropriately performed inside the multilayer substrate (10).

  In this case, as in the invention described in claim 3, each resin layer (1-8) is provided with a thermally conductive via (16) penetrating in the thickness direction, and a plurality of resin layers (1-1) are provided. 8) The heat dissipation layer (15) provided between the heat dissipation members (30) is thermally connected to each other in the laminating direction of the resin layers (1 to 8) via the vias (16), and the heat dissipation member (30) is heated. May be connected to each other.

  According to this, the heat dissipation layers (15) provided between the respective layers of the resin layers (1 to 8) can be thermally connected, and the heat of the heat dissipation layer (15) can be released to the heat dissipation member (30). This enables efficient heat dissipation.

  Further, as in the invention described in claim 4, a solder ball (40) made of solder for connecting to the outside is provided on the multilayer substrate (10), and the heat dissipation layer (15) is provided via the via (16). The solder balls (40) may be thermally connected.

  Accordingly, the heat of the heat dissipation layer (15) can be released to the outside via the solder balls (40), which is preferable for efficient heat dissipation.

  Further, the invention according to claim 5 is characterized in that the heat dissipation layer (15) has a portion protruding outward from the surface of the multilayer substrate (10).

  According to this, the heat radiation layer (15) has a projecting portion, thereby increasing the heat radiation area to the outside, which is preferable for improving heat radiation.

  In the invention according to claim 6, the spring having spring elasticity in the direction in which both the parts (15, 23) are separated between the heat radiation layer (15) and the side surface (23) of the semiconductor chip (20). The member (50) is interposed, and both the parts (15, 23) are thermally connected via the spring member (50).

  According to this, the contact between the heat dissipation layer (15) and the side surface (23) of the semiconductor chip (20) is improved by the spring elasticity of the spring member (50), and the thermal connection between the two parts (15, 23) is improved. This is preferable for securing.

  Further, in the invention according to claim 7, the heat dissipation layer (15) is further on the opposite side of the surface of the semiconductor chip (20) from the one plate surface (21) inside the multilayer substrate (10). The other plate surface (22) is also thermally connected.

  According to this, the heat radiation by the heat radiation layer (15) is also possible from the other plate surface (22) of the semiconductor chip (20), which is preferable.

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. A semiconductor device shown in each of the following embodiments is a vehicle-mounted semiconductor device and is mounted on a vehicle-mounted electronic product such as an engine ECU. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(First embodiment)
1A is a diagram illustrating a schematic cross-sectional configuration of the semiconductor device 100 according to the first embodiment of the present invention, and FIG. 1B is a schematic plan view illustrating a planar pattern of the heat dissipation layer 15 in the semiconductor device 100. It is. In FIG. 1B, the portion of the heat dissipation layer 15 protruding into the recess 11 of the multilayer substrate 10 is shown in a state before being bent.

  The semiconductor device 100 of the present embodiment is broadly divided into a multilayer substrate 10, a semiconductor chip 20 provided inside the multilayer substrate 10, and a heat dissipation member 30 thermally connected to one plate surface 21 of the semiconductor chip 20. And is configured.

  The multilayer substrate 10 is a PALAP (Patterned Prepay LAy up Process) substrate in which a plurality of resin layers 1 to 8 made of resin are laminated. These resin layers 1 to 8 are made of a thermoplastic resin such as a liquid crystal polymer, and bonded by hot pressing, as in a general PALAP substrate.

  Although the number of the resin layers 1 to 8 is not limited, the number of layers is 8 here. The planar size of the resin layers 1 to 8 is, for example, about 10 mm × 10 mm, and the thickness is 25 to 100 μm per layer.

  The semiconductor chip 20 is a chip such as an IC chip or a transistor element made of a silicon semiconductor made of a general semiconductor process, and has a plate shape. Here, it is a rectangular plate-shaped chip like a general one, for example, about 5 × 5 mm. Moreover, the thickness of the semiconductor chip 20 is thicker than the thickness of each resin layer 1-8, for example, is 0.1-0.4 mm.

  The multilayer substrate 10 is provided with a recess 11 that is recessed along the direction in which the resin layers 1 to 8 are stacked (the vertical direction in FIG. 1A), and the semiconductor chip 20 is accommodated in the recess 11. ing. Here, the recess 11 is provided closer to one surface of the multilayer substrate 10 (upper surface in FIG. 1A).

  Since the thickness of the semiconductor chip 20 is larger than the thickness of one resin layer, in order to accommodate the semiconductor chip 20 in the recess 11, the depth of the recess 11 is equal to the thickness of two or more resin layers. It needs to be recessed. Here, the recess 11 is recessed by the thickness of the second, third, and fourth three resin layers 2 to 4 from the one surface side of the multilayer substrate 10.

  Further, as shown in FIG. 1, the planar shape of the recess 11 is a rectangle slightly larger than the semiconductor chip 20 so that the semiconductor chip 20 can be inserted. The recess 11 is closed by the resin layer 1 constituting one surface of the multilayer substrate 10, that is, the resin layer 1 positioned first on the one surface side of the multilayer substrate 10, and is configured as a cavity inside the multilayer substrate 10. . Hereinafter, this resin layer 1 is referred to as a first resin layer 1.

  In such a closed recess 11, the semiconductor chip 20 is arranged in a state where the thickness direction of the semiconductor chip 20 is along the stacking direction of the resin layers 1 to 8. In other words, the plate surfaces 21 and 22 of the semiconductor chip 20 and the stacking direction are substantially orthogonal.

  One plate surface 21 of the semiconductor chip 20 is a surface orthogonal to the thickness direction of the semiconductor chip 20 in the surface of the semiconductor chip 20. The second resin layer 1 is opposed.

  The other plate surface 22 of the semiconductor chip 20, which is the surface opposite to the one plate surface 21, faces the bottom of the recess 11, that is, the resin layer 5 located fifth from the one surface side of the multilayer substrate 10. ing. Further, the side surface 23 of the semiconductor chip 20 is a surface extending in the thickness direction of the semiconductor chip 20 in the surface of the semiconductor chip 20, and the side surface 23 of the semiconductor chip 20 is within the recess 11. Opposite the side.

  Here, like the general PALAP substrate, electrical wirings 12 and 13 for taking out signals from the semiconductor chip 20 are formed on the multilayer substrate 10. Here, the electrical wirings 12 and 13 are provided on the four resin layers 5 to 8 located on the other surface (the lower surface in FIG. 1A) side of the multilayer substrate 10.

  The electrical wirings 12 and 13 are located between the resin layers 5 to 8 and are formed in a desired pattern between the resin layers 5 to 8 and the individual resin layers 5 to 8 so as to pass through each interlayer. A via 13 that electrically connects the wiring 12 is formed.

  The interlayer wiring 12 is made of a metal foil such as Cu patterned by etching or the like, and the via 13 is conductive and thermally conductive such as a metal paste filled in a through hole penetrating the resin layers 5 to 8 and cured. Made of excellent material.

  More specifically, the interlayer wiring 12 is, for example, a Cu foil having a thickness of about 9 to 35 μm, and the via 13 is, for example, 75 to 300 μm in diameter and has a higher melting point than a solder such as Ag—Sn. Made of metal paste.

  The electrical wirings 12 and 13 are electrically connected in contact with pads 24 provided on the other plate surface 22 of the semiconductor chip 20. The pad 24 is made of Au, Cu, solder or the like. For example, the via 13 and the pad 24 of the electrical wiring are electrically connected by mutual alloy reaction.

  Next, a heat dissipation configuration in the semiconductor device 100 will be described. First, a heat radiating via 14 is provided in a portion of the first resin layer 1 facing the one surface 21 of the semiconductor chip 20. The heat dissipation via 14 is a thermally conductive via that penetrates the first resin layer 1 in the thickness direction.

  The heat dissipation via 14 is made of a material having excellent conductivity and thermal conductivity similar to the via 13 of the electric wiring. Here, the heat radiating via 14 has the same planar shape as the semiconductor chip 20, but is not limited to this. For example, the heat radiating via 14 has the same 75 to 300 μm as the via 13 of the electric wiring. A cylindrical shape having a diameter may have a configuration in which a plurality of the resin layers 1 are regularly or randomly scattered in a portion of the first resin layer 1 facing the one surface 21 of the semiconductor chip 20.

  The one plate surface 21 of the semiconductor chip 20 and the heat dissipation member 30 are thermally connected through the heat dissipation via 14. Here, it is preferable that one plate surface 21 of the semiconductor chip 20 is plated with Au, Ni or the like to ensure the connectivity between the one plate surface 21 and the heat dissipation via 14.

  As the heat radiating member 30, a general plate-shaped heat sink is employed. Here, the heat radiating member 30 is substantially the same plane size as the multilayer substrate 10 and has a thickness of, for example, 0.1 to 1 mm, and is made of a metal material having good thermal conductivity such as Cu or Al.

  The heat of the semiconductor chip 20 is radiated from one plate surface 21 of the semiconductor chip 20 by the heat radiating member 30. Further, in the present embodiment, as a configuration for radiating the heat of the semiconductor chip 20, the heat radiation layer 15 thermally connected to the side surface 23 of the semiconductor chip 20 is provided in the multilayer substrate 10.

  Here, the heat dissipation layer 15 is a layered layer provided between the plurality of resin layers 1 to 8. The heat dissipation layer 15 can be made of the same material, thickness, and manufacturing method as the interlayer wiring 12 of the electric wiring. Further, as shown in FIG. 1B, the planar pattern has a wiring shape in which one end is located on the concave portion 11 side and the other end side extends to the peripheral portion of the multilayer substrate 10.

  Among the heat radiation layers 15, those located between the resin layers 1 to 4 constituting the recess 11 have one end exposed in the recess 11 on the side surface of the recess 11. On the side surface of the recess 11, an interlayer between the resin layers 1 to 4 constituting the recess 11 is located, and the heat dissipation layer 15 is exposed between the interlayer.

  The exposed portion of the heat dissipation layer 15 and the side surface 23 of the semiconductor chip 20 are in contact with each other in the recess 11, and the heat dissipation layer 15 and the semiconductor chip 20 are thermally connected. The exposed portion of the heat dissipation layer 15 originally protrudes into the recess 11 as shown in FIG. 1B, and this is directed toward the bottom of the recess 11 as shown in FIG. In contact with the side surface 23 of the semiconductor chip 20.

  Further, as shown in FIG. 1A, each of the resin layers 1 to 8 is provided with a thermally conductive via 16 penetrating in the thickness direction. The thermally conductive via 16 is made of the same material, shape, and manufacturing method as the electrical signal via 13.

  And each heat dissipation layer 15 provided between the plurality of resin layers 1 to 8 is thermally connected across the individual resin layers 1 to 8 through thermally conductive vias 16. That is, these heat dissipation layers 15 are thermally connected to each other in the stacking direction of the resin layers 1 to 8.

  Further, each heat radiation layer 15 is thermally connected to the heat radiation member 30 through a thermally conductive via 16 provided in the first heat radiation layer 1. The thermal connection configuration of the heat dissipation layer 15 through the via 16 is not limited to the wiring-shaped heat dissipation layer 15 extending from the side of the recess 11 in FIG. The rectangular heat radiation layer 15 is also the same.

  The heat dissipation layer 15 and the heat conductive via 16 are provided in each layer and each resin layer by the same material as the interlayer wiring 12 and via 13 of the electric wiring, respectively, but the function thereof is the electric wiring 12. , 13 does not contribute to the connection of electrical signals for operating the semiconductor chip 20.

  A solder ball 40 made of solder is provided on the other surface of the multilayer substrate 10, and the semiconductor device 100 is connected to an external member via the solder ball 40. Each interlayer wiring 12 is electrically connected to a solder ball 40 through a via 13 of electrical wiring. In addition, each heat dissipation layer 15 is thermally connected to the solder ball 40 through a thermally conductive via 16.

  Next, a method for manufacturing the semiconductor device 100 will be described with reference to FIGS. FIG. 2 is a process diagram showing the present manufacturing method, and FIG. 3 is a process diagram of the manufacturing method subsequent to FIG. 2. The work in each process is shown in a cross section corresponding to FIG.

  First, in the seven resin layers 2 to 8 except for the first resin layer 1, openings for forming the recesses 11, electric wirings 12 and 13, a heat radiation layer 15, and a heat conductive via 16 are formed. . Here, the electrical wirings 12 and 13 and the heat radiation layer 15 and the heat conductive via 16 are produced by a general method such as drilling a resin layer, etching a metal foil, printing / curing a metal paste, or the like. Done.

  Then, as shown in FIG. 2A, these seven resin layers 2 to 8 are aligned and laminated. At this time, the heat radiation layer 15 provided in the three resin layers 2 to 4 constituting the recess 11 is protruded into the recess 11 by about the thickness of each resin layer (for example, 25 to 100 μm). Thereby, a work as shown in FIG. 2B is completed. Note that the planar configuration of the workpiece in FIG. 2B corresponds to that shown in FIG.

  Next, as shown in FIG. 2C, the semiconductor chip 20 is inserted from the opening of the recess 11, and the semiconductor chip 20 is installed in the recess 11. At this time, the semiconductor chip 20 is inserted into the recess 11 while the semiconductor chip 20 pushes down the portion of the heat dissipation layer 15 protruding into the recess 11.

  FIG. 4 is an enlarged view showing a portion where the heat dissipation layer 15 is pushed down by the semiconductor chip 20. By doing so, as described above, the heat dissipation layer 15 is in contact with the side surface 23 of the semiconductor chip 20 while being bent in the recess 11, and the side surface 23 of the semiconductor chip 20 and the heat dissipation layer 15 are firmly in contact.

  In the installation of the semiconductor chip 20, the pad 24 of the semiconductor chip 20 and the via 13 of the electrical wiring are brought into contact with each other at the bottom of the recess 11. When the mounting of the semiconductor chip 20 on the multilayer substrate 10 is completed in this way, the work shown in FIG. 3A is completed.

  Next, as shown in FIG. 3B, the first resin layer 1 in which the heat dissipation vias 14 are formed is laminated thereon, and the recess 11 is closed. Next, as shown in FIG.3 (c), the thermal radiation member 30 is stacked on it.

  Thereafter, the workpiece is pressed together with a predetermined heat and pressure. Thereby, between each resin layer 1-8, between the resin layer and the heat radiating member 30, between the pad 24 of the semiconductor chip 20 and the thermally conductive via 16, and between the semiconductor chip 20 and the heat radiating via 14 The space is joined by thermocompression bonding or alloy reaction.

  Thereafter, the solder balls 40 are mounted on the other surface of the multilayer substrate 10 by a general method. Thus, the semiconductor device 100 of this embodiment is completed. The semiconductor device 100 is used by being connected to an external member via the solder ball 40.

  FIG. 5 shows a specific example in which the semiconductor device 100 is attached to an external member, and is a schematic cross-sectional view showing an example in which the semiconductor device 100 is mounted on a mother board 200 and a case 300 as external members. .

  The mother board 200 is, for example, a general circuit board, and the case 300 is a metal case such as Al that houses the mother board 200. The semiconductor device 100 is electrically and thermally connected to the mother board 200 via the solder balls 40 on the other surface side of the multilayer substrate 10. On the one surface side of the multilayer substrate 10, the heat dissipation member 30 is a silicone gel. It adheres via the heat conductive gel 310 which consists of these.

  By the way, according to the present embodiment, not only the heat radiating member 30 is thermally connected to one plate surface 21 of the semiconductor chip 20, but also heat is applied to the side surface 23 of the semiconductor chip 20 inside the multilayer substrate 10. A thermally connected heat dissipation layer 15 is provided. That is, in addition to the heat dissipation path by the heat dissipation member 30, a heat dissipation path by the heat dissipation layer 15 from the side surface 23 of the semiconductor chip 20 is further formed.

  Therefore, according to this embodiment, the heat dissipation of the semiconductor chip 20 can be improved without increasing the size of the heat dissipation member as compared with the conventional case. Specifically, the heat dissipation path by the heat dissipation layer 15 will be described with reference to the example of FIG. 5 described above. The heat of the semiconductor chip 20 reaches the heat conductive via 16 from the side surface 23 through the heat dissipation layer 15 and dissipates heat. The member 30 can escape to a heat radiating body having a larger heat capacity than the heat radiating layer 15.

  Then, heat is radiated from the heat radiating member 30 to the heat radiating body having a larger heat capacity such as the case 300 through the gel 310. In FIG. 5, heat from the side surface 23 of the chip 20 can be released from the heat dissipation layer 15 to the solder ball 40 and further to the mother board 200 through the heat conductive via 16.

  Further, by disposing as many heat radiation layers 15 and heat conductive vias 16 as possible in contact with the side surfaces 23 of the semiconductor chip 20, the thermal conductivity of the multilayer substrate 10 as a whole is increased, and therefore the semiconductor device 100 as a whole. The heat dissipation is improved.

  Here, FIGS. 6 and 7 are schematic plan views showing other planar shapes of the heat dissipation layer 15. As the planar shape of the heat radiation layer 15, various forms are possible other than the wiring shape extending from the side of the recess 11 as shown in FIG. 1B, for example, FIG. A shape as shown in FIG. 7 is possible.

  The heat radiation layer 15 shown in FIG. 6 is the same as the part shown in FIG. 1B in the portion protruding into the concave portion 11, but in the portion other than the concave portion 11, that is, the portion located between the resin layers, It has a continuously connected shape.

  Moreover, in the heat radiating layer 15 shown in FIG. 7, the part which protrudes in the recessed part 11 is also the shape connected continuously. 6 and 7 are connected to each other through the heat conductive vias 16 as described above, and the same effects as described above are exhibited.

  FIG. 8 is a schematic cross-sectional view showing another shape of the thermally conductive via 16. In FIG. 8, the heat conductive via 16 has a larger diameter than that of FIG. Thus, the size and number of the thermally conductive vias 16 are not particularly limited.

(Second Embodiment)
FIG. 9 is a diagram showing a schematic cross-sectional configuration of a semiconductor device 110 according to the second embodiment of the present invention. Here, the difference from the first embodiment will be mainly described.

  As in the first embodiment, the heat dissipation layer 15 has a wiring shape with one end positioned on the concave portion 11 side and the other end extending to the peripheral portion of the multilayer substrate 10. The other end of 15 protrudes outward from the side surface of the multilayer substrate 10. In other words, the other end of the heat dissipation layer 15 that is opposite to the one end thermally connected to the side surface 23 of the semiconductor chip 20 protrudes outward from the surface of the multilayer substrate 10.

  According to this embodiment, since the other end of the heat dissipation layer 15 is a portion protruding to the outside of the multilayer substrate 10, the heat dissipation area to the outside of the heat dissipation layer 15 is increased accordingly. Therefore, there is an advantage that the heat dissipation efficiency of the heat from the side surface 23 of the semiconductor chip 20 is increased, and the heat dissipation can be improved.

  FIG. 10 is a schematic cross-sectional view showing an example in which another heat dissipation member 31 is attached to the semiconductor device 110 according to the second embodiment. In FIG. 10, another heat radiating member 31 is brought into thermal contact with the other end of the heat radiating layer 15 protruding from the side surface of the multilayer substrate 10. The other heat radiating member 31 is a plate material similar to the heat radiating member 30, and is fixed by a fastening means (not shown). As a result, heat is radiated from the other end of the heat radiating layer 15 to another heat radiating member 31, and an improvement in heat dissipation can be expected.

(Third embodiment)
FIG. 11A is a diagram illustrating a schematic cross-sectional configuration of the semiconductor device 120 according to the third embodiment of the present invention, and FIG. 11B illustrates a single configuration of the spring member 50 in the semiconductor device 120. It is an external view. Here, the difference from the first embodiment will be mainly described.

  As shown in FIG. 11, in the semiconductor device 120 of the present embodiment, the spring member 50 is interposed between the heat dissipation layer 15 and the side surface 23 of the semiconductor chip 20 in the semiconductor device of the first embodiment. . The spring member 50 has spring elasticity in the direction in which both the parts 15 and 23 are separated, that is, in the left-right direction in FIG.

  Here, the spring member 50 has a corrugated plate shape with projections and depressions in the separated direction, and is made of a metal having high thermal conductivity such as Cu or Al. The heat dissipation layer 15 and the side surface 23 of the semiconductor chip 20 are in thermal contact with each other via the spring member 50 due to spring elasticity exerted in the same direction.

  This configuration is formed by inserting the semiconductor chip 20 into the recess 11 so as to press the spring member 50 against the side surface of the recess 11 after the spring member 50 is disposed in the recess 11. According to the present embodiment, the spring elasticity of the spring member 50 improves the contact between the heat dissipation layer 15 and the side surface 23 of the semiconductor chip 20, and it is easy to ensure the thermal connection between the both parts 15 and 23.

  Further, in the present embodiment, a resin 60 having thermal conductivity is filled between the heat radiation layer 15 and the side surface 23 of the semiconductor chip 20 in the recess 11 so as to seal the spring member 50. Therefore, further improvement in heat dissipation can be expected. This resin 60 is, for example, an epoxy resin containing an alumina filler, and is formed by inserting the semiconductor chip 20 into the recess 11 and then injecting it between the semiconductor chip 20 and the side surface of the recess 11.

(Fourth embodiment)
FIG. 12A is a diagram showing a schematic cross-sectional configuration of a semiconductor device 130 according to the fourth embodiment of the present invention, and FIG. 12B shows a single configuration of the spring member 50 in the semiconductor device 130. It is an external view. The present embodiment has a spring member 50 as in the third embodiment, and the shape of the spring member 50 is changed.

  The spring member 50 of the present embodiment has a leaf spring shape as shown in FIG. Also in this case, the arrangement method of the spring member 50 is the same as that of the third embodiment, and the effect of the spring member 50 is also the same.

(Fifth embodiment)
FIG. 13A is a view showing a schematic cross-sectional configuration of a semiconductor device 140 according to the fifth embodiment of the present invention, and FIG. 13B is an external view showing a state in which the spring member 50 is attached to the semiconductor chip 20. FIG.

  This embodiment is manufactured by inserting the semiconductor chip 20 into the recess 11 after attaching the spring member 50 of the fourth embodiment to the semiconductor chip 20 in advance. The effect of the spring member 50 is the same as described above.

(Sixth embodiment)
FIG. 14 is a diagram showing a schematic cross-sectional configuration of a semiconductor device 150 according to the sixth embodiment of the present invention. Here, the differences from the first embodiment will be mainly described, but the present embodiment is applicable to each of the above embodiments.

  As shown in FIG. 14, a heat dissipation layer 15 is further provided inside the multilayer substrate 10 so as to face the other plate surface 22 of the semiconductor chip 20, and the heat dissipation layer 15 is thermally conductive. The other plate surface 22 of the semiconductor chip 20 is contacted and thermally connected via the via 16.

  The heat dissipation layer 15 is thermally connected to the solder balls 40 in the same manner as the heat dissipation layer 15 shown in the above embodiment. According to the present embodiment, in addition to the effects of the heat dissipation layer 15 in each of the embodiments described above, heat dissipation by the heat dissipation layer 15 is also possible from the other plate surface 22 of the semiconductor chip 20.

(Other embodiments)
In each of the above embodiments, the recess 11 in which the semiconductor chip 20 is housed is closed with the first resin layer 1. However, the first resin layer 1 is omitted, and the semiconductor chip 20 and the heat dissipation member are omitted. 30 may be brought into direct contact with a die bonding material or the like.

  In each of the above embodiments, the heat dissipation layer 15 is connected by the heat conductive via 16 and further connected to the heat dissipation member 30 to improve heat dissipation. The configuration without the via 16 may be used.

  In addition, as in each of the embodiments described above, it is preferable in terms of heat dissipation if the heat dissipation layer 15 is thermally connected to the solder balls 40, but it may not be particularly connected. That is, the structure without the solder balls 40 connected to the heat dissipation layer 15 may be used.

  Moreover, in each said embodiment, although the thermal radiation layer 15 was provided between the layers of the adjacent resin layers 1-8, besides that, by resin molding etc., inside each resin layer 1-8. The heat dissipation layer may be embedded.

(A) is a schematic sectional drawing of the semiconductor device which concerns on 1st Embodiment of this invention, (b) is a schematic plan view which shows the planar pattern of the thermal radiation layer in the semiconductor device. It is process drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process drawing of the manufacturing method following FIG. It is an enlarged view which shows the part by which the thermal radiation layer was pushed down by the semiconductor chip. It is a schematic sectional drawing which shows one specific example which attached the semiconductor device which concerns on 1st Embodiment to the external member. It is a schematic plan view which shows the other planar shape of the thermal radiation layer in 1st Embodiment. It is a schematic plan view which shows the other planar shape of the thermal radiation layer in 1st Embodiment. It is a schematic sectional drawing which shows the other shape of the heat conductive via in 1st Embodiment. It is a schematic sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a schematic sectional drawing which shows the example which attached another heat radiating member to the semiconductor device which concerns on 2nd Embodiment. (A) is a schematic sectional drawing of the semiconductor device which concerns on 3rd Embodiment of this invention, (b) is an external view which shows the single-piece | unit structure of the spring member in the semiconductor device. (A) is a schematic sectional drawing of the semiconductor device which concerns on 4th Embodiment of this invention, (b) is an external view which shows the single-piece | unit structure of the spring member in the semiconductor device. (A) is a schematic sectional drawing of the semiconductor device which concerns on 5th Embodiment of this invention, (b) is an external view which shows the state which attached the spring member to the semiconductor chip. It is a schematic sectional drawing of the semiconductor device which concerns on 6th Embodiment of this invention.

Explanation of symbols

1-8 Resin layer 10 Multilayer substrate 11 Recess 15 Heat dissipation layer 16 Thermally conductive via 20 Semiconductor chip 21 One plate surface 22 of semiconductor chip 23 Other plate surface 23 of semiconductor chip Side surface 30 of semiconductor chip Heat dissipation member 40 Solder ball 50 Spring member

Claims (7)

A multilayer substrate (10) in which a plurality of resin layers (1-8) made of resin are laminated;
A semiconductor chip (20) having a plate shape provided inside the multilayer substrate (10),
Of one surface of the semiconductor chip (20), which is a surface orthogonal to the thickness direction of the semiconductor chip (20), a heat radiating member that radiates heat from the semiconductor chip (20) is provided on one plate surface (21). 30) are thermally connected,
In the multilayer substrate (10), a heat dissipation layer (thermally connected to a side surface (23) which is a surface extending in the thickness direction of the semiconductor chip (20) of the surface of the semiconductor chip (20)). 15). A semiconductor device comprising: The semiconductor chip (20) is arranged in a state in which the thickness direction is along the lamination direction of the resin layers (1 to 8) in the multilayer substrate (10),
The multilayer substrate (10) is provided with a recess (11) that is recessed along the stacking direction of the resin layers (1-8),
The semiconductor chip (20) is housed in the recess (11), and the side surface of the recess (11) and the side surface (23) of the semiconductor chip (20) are opposed to each other.
The heat dissipation layer (15) is provided between the plurality of resin layers (1 to 8) and between the resin layers (1 to 4) constituting the recess (11). Is exposed on the side,
The exposed portion of the heat dissipation layer (15) and the side surface (23) of the semiconductor chip (20) are in contact with each other in the recess (11) and are thermally connected. The semiconductor device described. Each of the resin layers (1 to 8) is provided with a thermally conductive via (16) penetrating in the thickness direction,
The heat-dissipating layer (15) provided between the plurality of resin layers (1-8) is thermally coupled to each other in the stacking direction of the resin layers (1-8) via the vias (16). The semiconductor device according to claim 2, wherein the semiconductor device is connected and thermally connected to the heat radiating member. The multilayer substrate (10) is provided with solder balls (40) made of solder for connecting to the outside,
The semiconductor device according to claim 3, wherein the heat dissipation layer (15) is also thermally connected to the solder ball (40) through the via (16).   The semiconductor device according to any one of claims 1 to 4, wherein the heat dissipation layer (15) has a portion protruding outward from a surface of the multilayer substrate (10).   Between the heat dissipation layer (15) and the side surface (23) of the semiconductor chip (20), a spring member (50) having spring elasticity is interposed in a direction in which both the parts (15, 23) are separated. The semiconductor device according to claim 1, wherein both the parts (15, 23) are thermally connected via the spring member (50).   Further, the heat dissipation layer (15) is formed on the other plate surface (22) of the surface of the semiconductor chip (20) opposite to the one plate surface (21) inside the multilayer substrate (10). The semiconductor device according to claim 1, wherein the semiconductor device is also thermally connected.

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