JP2010073804A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device which is small-sized and is in high-speed operation. <P>SOLUTION: An output gate electrode 24 having a width almost equal to that of a transfer electrode 19 of the CCD horizontal transfer register 14 is disposed at the final stage of the CCD horizontal transfer register 14 having a transfer channel 18 formed to have a constant width L1. Under the output gate electrode 24, a narrowing down portion 23b is formed near an FD portion 16, the narrowing down portion being higher in potential than the transfer channel 18 and being narrowed down sharply in its width L4 from the CCD horizontal transfer register 14 toward the FD portion 16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a horizontal transfer register of a solid-state imaging device.

  In recent years, solid-state imaging devices used for mobile phones, digital cameras, and the like have been desired to have higher performance.

  A conventional solid-state imaging device has a plurality of light receiving elements formed in a matrix on the surface of a well of opposite conductivity type formed on a single conductive type semiconductor substrate, and is connected to these light receiving elements, and photoelectric conversion is performed by the light receiving elements. A plurality of CCD vertical transfer registers that transfer the signal charges obtained by the above, and a CCD horizontal transfer register that is connected to these CCD vertical transfer registers and transfers the signal charges transferred to the CCD vertical transfer registers to the output circuit. It is configured.

  In such a solid-state imaging device, a CCD horizontal transfer register is formed on the surface of a well formed on a semiconductor substrate, and a CCD channel which is an impurity region for transferring signal charges, and a signal on the CCD channel It is composed of a plurality of transfer electrodes arranged in a direction perpendicular to the charge transfer direction. Here, the CCD channel is formed of a wide impurity region in order to obtain a sufficient transfer capacity. On the other hand, the signal charge transferred by the CCD horizontal transfer register is connected to the final stage through an output gate that prevents backflow of the signal charge, and voltage is applied to a floating diffusion portion (hereinafter referred to as FD portion) that is a capacitance. It is converted and output. The FD portion is formed with a sufficiently small area in order to obtain a high output voltage. Therefore, an impurity region (hereinafter referred to as a channel narrowing region) for transferring signal charges from the CCD horizontal transfer register to the FD portion is formed in the output gate portion so as to be narrower in the signal charge transfer direction. Yes.

  As described above, when signal charges are transferred from a wide range of CCD horizontal transfer registers to an FD portion having a small area via an output gate, there are the following problems.

  When the channel width is abruptly narrowed in the signal charge transfer direction, the potential formed by the channel narrowing region becomes lower as the channel width is narrower due to the narrow channel effect. Therefore, in the vicinity of the output gate, there is a problem that the potential gradient becomes gentle or a reverse gradient occurs, and the signal charge remains without being transferred normally. Note that the above-described potential defects due to the narrow channel effect are generally provided outside the channel, and the channel stopper barrier, which is an impurity layer of the opposite conductivity type to the channel region, becomes a channel narrowing region as the channel width becomes narrower. This is because the impurity concentration decreases in the vicinity of the junction between the channel squeezing region and the channel stopper barrier, and the potential necessary for channel formation decreases.

  Therefore, the channel narrowing region is provided from the CCD horizontal transfer register in front of the charge transfer direction from the output gate, so that the narrowing angle is formed smaller than 80 ° at which the transfer efficiency rapidly deteriorates, thereby deteriorating the transfer efficiency of the signal charge. A solid-state imaging device capable of suppressing the above is known (for example, see Patent Document 1).

  Further, in the channel narrowing region, a higher concentration impurity layer is formed in the vicinity of the junction with the FD portion, and a high potential portion is formed, so that deterioration of transfer efficiency in the output gate can be suppressed. An imaging device is known (see, for example, Patent Document 2).

  However, in the solid-state imaging devices described in Patent Documents 1 and 2, since the channel narrowing area is provided from the CCD horizontal transfer register in order to avoid a sudden narrowing, the channel width becomes narrow, and the transfer of the CCD horizontal transfer register is reduced. There is a problem that the capacity decreases.

Patent Document 2 discloses a solid-state imaging device that can suppress a decrease in transfer capacity by forming a wide electrode width and increasing a transfer length. However, since the transfer length is lengthened, there is a problem that the signal charge transfer time becomes long and the high-speed performance of the device is lost. Furthermore, there is a problem that the apparatus becomes large.
Japanese Patent Laid-Open No. 10-256531 JP 2003-209243 A

  An object of the present invention is to provide a solid-state imaging device that is small and capable of high-speed operation.

  The solid-state imaging device of the present invention includes a second conductivity type well formed on a first conductivity type semiconductor substrate, a first conductivity type first impurity region formed on the surface of the well, and the first conductivity type well. A transfer channel having a plurality of second conductivity type second impurity regions formed at a predetermined interval on the surface of the impurity region, and formed on the first impurity region of the transfer channel and transferred by the transfer channel Formed on the plurality of first transfer electrodes formed perpendicular to the charge transfer direction and the second impurity region of the transfer channel, and formed between the plurality of first transfer electrodes, respectively. A plurality of second transfer electrodes, an output gate electrode formed adjacent to and in parallel with the final stage of these second transfer electrodes, and a first impurity region under the output gate electrode Towards the surface of the charge transfer direction Is formed so as to be narrower, and is formed by being joined to the channel narrowing portion of the first conductivity type having a higher concentration than the first impurity region and the end of the channel narrowing portion, and having a higher concentration than the channel narrowing portion. And a floating diffusion portion of one conductivity type.

  According to the present invention, it is possible to provide a small-sized solid-state imaging device capable of high-speed operation.

  Hereinafter, the solid-state imaging device according to the present embodiment will be described with reference to the drawings.

  1A is an enlarged top view of a part of the CCD horizontal transfer register of the solid-state imaging device according to the present embodiment, and FIG. 1B is a partially enlarged view of FIG. 1A. 2A shows a cross-sectional view of the broken line XX ′ structure of FIG. 1A, and FIG. 2B shows the state of the potential formed in the solid-state imaging device shown in FIG. 2A.

  As shown in FIG. 2A, the solid-state imaging device according to the present embodiment outputs a plurality of CCDs vertically transferred from a plurality of photodiodes (not shown) to a p-type well 12 formed on an n-type semiconductor substrate 11. A CCD horizontal transfer register 14 for transferring signal charges transferred by a register (not shown) to the output unit 13 is formed. The output unit 13 is formed at the final stage of the CCD horizontal transfer register 14 and is connected to the output gate unit 15 for preventing the backflow of the transferred signal charge, and the transferred signal charge is set to a voltage. An FD unit 16 that converts and outputs the signal and a reset unit 17 that is connected to the FD unit 16 and discharges the signal charges transferred to the FD unit 16 at a desired timing.

  As shown in FIG. 1A, the CCD horizontal transfer register 14 is formed in the p-type well 12 shown in FIG. 2A with a constant width L1, and a transfer channel 18 for transferring signal charges and a signal charge on the transfer channel 18 are formed. The plurality of transfer electrodes 19 are formed perpendicular to the transfer direction and parallel to each other. Here, as shown in FIG. 2A and FIG. 2B, the transfer channel 18 is directed to the direction of signal charge transfer by a plurality of CCD vertical transfer registers (not shown) connected to a plurality of photodiodes (not shown). A first n-type impurity region 20 formed in the vertical direction, and first and second p-type impurity regions 211 and 212 formed on the surface of the first n-type impurity region 20 at regular intervals. It is configured. Here, the second p-type impurity region 212 is formed with a higher concentration than the first p-type impurity region 211. The transfer channel 18 formed in this way has a high potential in the order of the second p-type impurity region 212, the first p-type impurity region 211, and the first n-type impurity region 20, as indicated by the broken line in FIG. 2B. It is formed to become.

  The transfer electrode 19 on the transfer channel 18 includes a transfer electrode storage unit 191 formed on the first n-type impurity region 20 between the first and second p-type impurity regions 211 and 212, This is a multilayer electrode structure including transfer electrode barrier portions 192 formed on the second p-type impurity regions 211 and 212. A transfer electrode 18 adjacent to an output gate electrode 24 described later is a transfer electrode register final stage 193. These electrodes 191, 192, 193 are made of polysilicon, for example. As shown in FIG. 1A, the electrode widths L2 of the transfer electrode storage unit 191, the transfer electrode barrier unit 192, and the transfer electrode register final stage 193 are formed substantially equal to each other.

  As shown in FIGS. 2A and 2B, the output gate portion 15 is formed to extend from the terminal end of the first p-type impurity region 211 below the transfer electrode register final stage 193 to a region extending to the FD portion 16. an output channel 23 comprising an n-type impurity region 20 and a second n-type impurity region 22 formed at a higher concentration near the FD portion 16 on the surface of the first n-type impurity region 20, and the output channel And an output gate electrode 24 made of, for example, polysilicon. As shown in FIG. 1A, the electrode width L3 of the output gate electrode 24 is formed substantially equal to the transfer electrode storage unit 191, the transfer electrode barrier unit 192, and the transfer electrode register final stage 193. Here, the output channel 23 formed in the output gate portion 15 will be described with reference to FIGS.

  3A, FIG. 3B, and FIG. 3C show structural sectional views along broken lines A1-A1 ′, broken lines B1-B1 ′, and broken lines C1-C1 ′ in FIG. 1B, respectively, and FIG. 4A and FIG. The structural sectional view along broken line A2-A2 'and broken line B2-B2' is shown.

  The output channel 23 formed under the output gate electrode 24 as shown in FIGS. 3 and 4 is composed of the first impurity region 20, and as shown in FIG. 1B, the channel non-restricted portion 23a having a constant width L1. Similarly, as shown in FIG. 1B, the width L4 becomes narrower from the terminal end of the non-channel narrowing portion 23a toward the FD portion 16, and the first impurity region 20 and the second impurity region 22 formed on the surface thereof. And a channel narrowing portion 23b made of As shown in FIG. 1A, the channel narrowing portion 23b passes through the FD portion 16 and is parallel to the transfer channel (the extension direction of the dashed line XX ′ in FIG. 1A) and the side portion 23b-1 of the channel narrowing portion 23b. Are formed at an angle of 86.5 degrees. Here, as shown in FIGS. 1A and 1B, the width of the junction between the channel narrowing portion 23b and the non-channel narrowing portion 23a is preferably formed to match L1. The reason for this will be described later.

  Next, the potential formed by the above-described channel narrowing portion 23b will be described with reference to FIGS. FIG. 5 shows potentials formed by the impurity regions at the positions of the cross sections shown in FIGS. 3A, 3B, and 3C. FIG. 6 shows the potential formed by the impurity regions at the positions of the cross sections shown in FIGS. 4A and 4B. Indicates potential.

  As shown in FIG. 5, the potential formed by the channel narrowing portion 23 b becomes higher in the direction from the channel non-thinning portion 23 a to the FD portion 16. Further, as shown in FIG. 6, the potential is increased from the end 23b-2 of the channel narrowing portion 23b toward the central portion 23b-3.

  The signal charges output from the output gate unit 15 as described above are processed by the following FD unit 16 unit and reset unit 17. These FD part 16 and reset part 17 are the following structures, for example.

  As shown in FIGS. 2A and 2B, the FD portion 16 is formed on the surface of the second n-type impurity region 22 that is formed to extend with a certain width from the terminal end of the output gate portion 15 to the reset portion 17. In this region, the first n + impurity region 25 having a higher concentration is formed. The first n + impurity region 25 is a portion that functions as a capacitance in which the transferred signal charge is accumulated, and Q = CV (Q: charge amount, C: capacitance, V: output voltage). Depending on the relationship, the signal charge is converted into a voltage and output. The FD unit 16 is connected to an amplifier 26 that amplifies the converted voltage.

  The reset unit 17 includes a second n-type impurity region 22 extended from the end of the second impurity region 22 constituting the FD unit 16, and the FD unit 16 on the surface of the second n-type impurity region 22. The second n + impurity region 25 formed at a predetermined interval from the first n + impurity region 25 constituting the first n + impurity region 25 and the second n + impurity region 25, 27 between the first n + impurity region 25 and 27. And a reset electrode 28 formed on the type impurity region 22. Such a reset unit 17 discharges unnecessary signal charges accumulated in the first n + impurity region 25 to the second n + impurity region 27 by applying a voltage pulse to the reset electrode 28 at a desired timing. ing. Here, the first n + impurity region 25 and the second n + impurity region 27 have the same impurity concentration in this embodiment, but the second n + impurity region 27 has the same impurity concentration as the first n + impurity region 27. It may be n + impurity region 25 or more.

  In the configuration described above, the transfer electrodes 191 and 192, the output gate electrode 24 and the reset electrode 28 are formed on the insulating film 29 formed on the p-type well 22.

  Next, a signal charge transfer method by the above-described solid-state imaging device will be described with reference to FIGS. 7A and 7B.

  The above-described solid-state imaging device operates by a so-called two-phase driving method. That is, a transfer electrode 19a composed of a pair of transfer electrode storage units 191 and a transfer electrode barrier unit 192, and a transfer composed of another transfer electrode storage unit 191 and a transfer electrode barrier unit 192 adjacent to the transfer electrode 19a. In this method, signal charges are transferred by alternately applying pulses having two different voltages to the electrode 19b. The voltage pulses to be applied may be voltage pulses having opposite phases to each other, but here, a case where pulses having two different voltages are applied will be described.

  First, as shown in FIG. 7A, when a high level voltage pulse (VφH) is applied to the transfer electrode 19a and a low level voltage pulse (VφL) is applied to the second transfer electrode 19b and the transfer electrode register final stage 193, respectively, the transfer channel 18 The potential formed at is as shown by the solid line in FIG. 7A. (The dotted line in the figure indicates the potential before the application of the pulse.) At this time, the signal charge 30a indicated by the dotted line below the transfer electrode storage unit 191 constituting the transfer electrode 19b is transferred by the potential gradient, and the black circle 30b. As shown in FIG. 3, the transfer electrode 19a moves below the transfer electrode storage unit 191. At this time, the same voltage as that of the transfer electrode 19b is also applied to the transfer electrode register final stage 193.

  Next, when the low level voltage pulse (VφL) is applied to the transfer electrode 19a and the high level voltage pulse (VφH) is applied to the transfer electrode 19b and the transfer electrode register final stage 193 from the state of FIG. 7A, the transfer channel 18 is formed. The potential is as shown by the solid line in FIG. 7B. (The dotted line in the figure indicates the potential before applying the pulse.) At this time, the signal charge 30a indicated by the dotted line below the transfer electrode storage unit 191 constituting the transfer electrode 19a is transferred by the potential gradient, and the black circle 30b. As shown in FIG. 4, the transfer electrode register moves to the lower stage 193.

  By repeating the above, the signal charges 30 are successively transferred in the transfer channel 18 of the CCD horizontal transfer register 14 and finally moved to the FD unit 16 via the output gate unit 15. Here, in the present embodiment, as shown in FIG. 1A, a channel non-narrowed portion 23a formed of the first n-type impurity region 20 and the first n-type impurity region 20 are formed below the output gate electrode 24. In addition, a channel narrowing portion 23b formed by the second n-type impurity region 22 having a higher concentration than this is formed. Among these, as shown in FIGS. 5 and 6, the potential formed by the channel narrowing portion 23 b is a potential that becomes higher from the end of the transfer channel 18 toward the FD portion 16. Therefore, the signal charge 30 is smoothly transferred to the FD unit 16 by this potential gradient.

  Next, a method for manufacturing the above-described solid-state imaging device will be described with reference to FIG.

  First, for example, P (phosphorus) ions are implanted into the surface of the p-type well 12 formed in the n-type semiconductor substrate 11 to form the first n-type impurity region 20.

  Next, the surface of the first n-type impurity region 20 formed on the surface of the p-type well 12 has a constant interval and the same width L1 as that of the first n-type impurity region 20, for example, B (Iodine) ions are implanted to form a first p-type impurity region 211. Subsequently, B ions are implanted into a part of the surface of the formed first p-type impurity region 211 in the same width L1 as the first n-type impurity region 20 so that the first p-type impurity is implanted. A second p-type impurity region 212 having a higher concentration than the region 211 is formed.

  On the other hand, P ions are further implanted into a region from the end of the non-restricted portion 23 a to the end of the reset portion 17, thereby forming the second n-type impurity region 22 having a higher concentration than the first n-type impurity region 20. At this time, the channel narrowing portion 23b composed of the second n-type impurity region 22 and the first n-type impurity region 20 below the second n-type impurity region 22 is formed as shown in FIG. 1A. The width L4 is formed to be narrower than the width L1 of the transfer channel 18 from the junction with the non-squeezed portion 23a toward the FD portion 16. At this time, the potential formed by the channel narrowing portion 23b is formed as shown in FIGS. Such a potential is formed by ordinary ion implantation. That is, ion implantation is performed using a resist mask having an isosceles triangular opening to form the impurity region 22 having the same concentration, so that the potential is increased in the transfer direction from the vicinity of the end 23b-2 of the narrowed portion 23b. A potential gradient is formed so as to be deeper, and the phenomenon that the potential gradient due to the narrow channel effect becomes gentle can be suppressed. Further, as will be described later, in order to form the first n + -type impurity region 25 having a higher concentration on the surface of the region extended from the second impurity region 22 constituting the channel narrowing portion 23b, the channel The potential formed in the vicinity of the central portion 23 b-3 of the narrowed-down portion forms a potential gradient so that the potential becomes deeper toward the first n + -type impurity region 25. Further, as shown in FIG. 5, as the FD portion 16 is approached, the potential gradient in the vicinity of the side portion 23b-1 of the channel narrowing portion 23b is formed so that the potential becomes deeper in the transfer direction. This also suppresses the phenomenon that the potential gradient due to the narrow channel effect becomes gentle. Therefore, potentials as shown in FIGS. 5 and 6 are formed.

  Here, as shown in FIG. 1A, the width of the junction between the above-described channel narrowing portion 23b and the non-channel narrowing portion 23a is formed to match the width L1 of the non-channel narrowing portion 23a. This is based on the simulation results shown below.

  FIG. 8A shows a simulation result of the signal charge transfer time by the formed channel narrowing portion 23b. In the simulation, as shown by a broken line in FIG. 8B, it is assumed that the signal charges to be transferred follow a locus 31 passing through the vicinity of the side portion 18a of the transfer channel 18 and passing through the vicinity of the side portion 23b-1 of the channel narrowing portion 23b. did.

  8A, when the signal charge is transferred through the locus 31, as shown in FIG. 8B, the width L4 of the channel narrowing portion 23b is reduced by y (the channel narrowing portion 23b FIG. 8B shows the relative delay amount of the transfer time in a case where only the shaded portion shown in FIG. 8B is reduced. In the figure, the signal charge transfer time when y = 0 is set to 1.

  According to FIG. 8A, the larger the width L4 of the channel narrowing portion 23b, the faster the transfer time of the signal charge transferred, and the distance between the end portions 23b-2 of the channel narrowing portion 23b is equal to the width L1 of the channel narrowing portion 23a. It can be seen that the transfer time is maximized when formed so as to match. This result is due to the following reason. That is, the end portion 23b-2 of the channel narrowing portion 23b is formed close to the side portion 18a of the transfer channel, and the end portion 23b-2 of the channel narrowing portion 23b is directed to the central portion 23b-3 of the channel narrowing portion 23b. By forming the channel narrowing portion 23b so as to widen toward the end, a potential gradient is formed so that the potential becomes deeper in the transfer direction from the vicinity of the end 23b-2 of the channel narrowing portion 23b, and the potential gradient due to the narrow channel effect becomes gentle. By suppressing the phenomenon, the signal charge 30 is transferred smoothly.

  As described above, the distance between the end portions 23b-3 of the channel narrowing portion 23b is formed so as to coincide with the width L1 of the non-channel narrowing portion 23a (the width of the transfer channel 18) as shown in the present embodiment. desirable.

  Next, As ions are implanted into a region adjacent to the end of the narrowed portion 23b of the second n-type impurity region 22 with a certain interval, and the first n-type impurity region 22 having a higher concentration than the second n-type impurity region 22 is implanted. Second n + type impurity regions 25 and 27 are formed. The first n + -type impurity region 25 is a region constituting the FD portion 16, and the capacitance of the FD portion 16 is determined by the potential formed by the first n + -type impurity region 25.

  After performing the ion implantation as described above, the transfer electrode storage unit 191, the transfer electrode barrier unit 192, and the final stage of the transfer electrode register are placed at desired positions on the well 12 where the respective impurity regions are formed via the insulating film 29. 193, the output gate electrode 24 and the reset electrode 28 are formed.

  Through the steps as described above, a solid-state imaging device as shown in FIG. 2A can be manufactured. At this time, a potential as shown in FIG. 2B is formed.

  As described above, according to the solid-state imaging device according to the present embodiment, the concentration of the signal charge is higher in the region adjacent to the FD portion 16 below the output gate electrode 24 than in the first n-type impurity region 20. By forming the second n-type impurity region 22 whose width L4 becomes narrower in the transfer direction, the channel narrowing region 23b is formed. At this time, the potential distribution by the channel narrowing region 23b forms a potential gradient that becomes a high potential in the direction from the non-channel narrowing region 23a to the FD portion 16, as shown in FIGS. Therefore, even if the narrowed portion 23b is formed by abruptly narrowing down the second n-type impurity region 22 and the first n-type impurity region 20 formed under the output gate electrode 24, a narrow channel is formed. It is possible to suppress a decrease in transfer efficiency due to the effect. Therefore, under the output gate electrode 24, it is not necessary to gradually narrow the transfer channel 18 width L1 of the CCD horizontal transfer register 14 in order to suppress a decrease in transfer efficiency, and a decrease in transfer capacity can be prevented. Accordingly, it is not necessary to increase the transfer length by increasing the electrode width L2 of the transfer electrode 19, so that a high-speed and small-sized solid-state imaging device can be realized.

  Further, as shown in FIGS. 5, 6, and 7A, the narrow channel effect is formed by forming the channel narrowing portion 23b so that the distance between the end portions 23b matches the width L1 of the non-channel narrowing portion 23a. A potential gradient can be formed so that the potential gradient becomes deeper in the transfer direction from the vicinity of the end 23b-2 of the channel narrowing portion 23b. Therefore, since the transfer time of the signal charge transferred near the side portion 18a of the transfer channel 18 and the side portion 23b-1 of the channel narrowing portion 23b can be shortened, a solid-state imaging device capable of operating at higher speed than before. Can be realized.

  Further, as described above, since the channel narrowing portion 23b under the output gate electrode 24 can be sharply narrowed, the area of the FD portion 16 can be made smaller than before. As a result, it is possible to further reduce the size of the solid-state imaging device and to obtain a higher output voltage than before, and thus it is possible to realize a small-size and high-sensitivity solid-state imaging device.

  Although the embodiment of the present invention has been described above, the embodiment is not limited to the above, and can be modified without departing from the spirit of the present invention.

  For example, in the above-described embodiment, the narrowing angle “a” of the narrowing portion 23 b below the output gate electrode 24 is not limited to the above-mentioned 86.5 °, and may be formed at an angle larger than this. In this case, considering the necessary transfer speed and transfer efficiency, the concentration of the second n-type impurity region 22 constituting the channel narrowing portion 23b may be increased to form a steeper potential gradient. Needless to say, it may be formed at an angle smaller than this.

  In the above-described embodiment, the transfer electrode 19 formed on the transfer channel 18 has a multilayer electrode structure, but may have a single-layer electrode structure in which the transfer electrodes are formed without overlapping each other.

  In the above-described embodiment, the p-type impurity regions 211 and 212 formed under the transfer electrode barrier unit 192 are formed in two types of concentrations. However, the p-type impurity region formed under the transfer electrode barrier portion 192 may be formed at a plurality of concentrations, or a p-type impurity region that gradually decreases in the signal charge transfer direction is formed. May be. In particular, when the p-type impurity region is formed so as to be gradually thinner, the potential formed by the p-type impurity region is not a stepped shape but a smooth potential that increases toward the signal charge transfer direction. Since it has a gradient, it is possible to further increase the transfer efficiency.

  Further, in the method for manufacturing the solid-state imaging device described above, the first n-type impurity region 20 only needs to be formed up to at least a portion that is joined to the second n-type impurity region 22. However, as shown in the present embodiment, when the second n-type impurity region 22 is formed by extending it to the position where the reset portion 17 is formed, ions are not implanted due to mask displacement, and the potential barrier is reduced. It can be prevented from being formed. In the above-described embodiment, for the same reason as described above, the second p-type impurity region 212 is formed on the surface of the first p-type impurity region 211, and the first and second n + -type impurity regions. 25 and 27 are formed on the surface of the second n-type impurity region 22. However, the impurity regions may be formed so that potentials as shown by dotted lines in FIG. 2B are formed. Accordingly, the second p-type impurity region 212 may not be formed on the surface of the first p-type impurity region 211, and the first and second n + -type impurity regions 25 and 27 may be formed of the second n-type impurity region. It does not have to be formed on the surface of the region 22.

It is a top view which shows the CCD horizontal transfer register and output part of the solid-state imaging device by this embodiment. It is a top view which expands and shows the output gate of FIG. 1A. 1B is a structural cross-sectional view taken along a broken line XX ′ in FIG. 1A. FIG. It is explanatory drawing which shows the electric potential distribution formed in the CCD horizontal transfer register and output part of the solid-state imaging device by this embodiment. FIG. 2 is a structural cross-sectional view taken along a broken line A1-A1 ′ in FIG. 1B. FIG. 2 is a structural cross-sectional view taken along a broken line B1-B1 ′ in FIG. 1B. FIG. 2 is a structural cross-sectional view taken along a broken line C1-C1 ′ in FIG. 1B. FIG. 2 is a structural cross-sectional view taken along a broken line A2-A2 ′ in FIG. 1B. FIG. 2 is a structural cross-sectional view taken along a broken line B2-B2 ′ in FIG. 1B. It is explanatory drawing which shows the electric potential distribution formed in the output gate part of the solid-state imaging device by this embodiment. It is explanatory drawing which shows the electric potential distribution formed in the output gate part of the solid-state imaging device by this embodiment. It is explanatory drawing explaining the transfer method of the signal charge by the CCD horizontal transfer register of the solid-state imaging device by this embodiment. It is explanatory drawing explaining the transfer method of the signal charge by the CCD horizontal transfer register of the solid-state imaging device by this embodiment. It is a figure which shows the result of having simulated the mode of the transfer of the signal charge by the output gate part of the solid-state imaging device by this embodiment. It is explanatory drawing for demonstrating the simulation which transfers the signal charge of FIG. 8A.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... n-type semiconductor substrate, 12 ... p-type well, 13 ... Output part, 14 ... CCD horizontal transfer register, 15 ... Output gate part, 16 ... FD part, 17. ..Reset unit, 18 ... transfer channel, 18a ... side of transfer channel, 19, 19a, 19b ... transfer electrode, 191 ... transfer electrode storage unit, 192 ... transfer electrode barrier unit 193 ... Transfer electrode register last stage, 20 ... First n-type impurity region, 211 ... First p-type impurity region, 212 ... Second p-type impurity region, 22 ... Second n-type impurity region, 23... Output channel, 23a... Channel unrestricted portion, 23b... Channel narrowed portion, 23b-1.・ End of narrowing part, 23b-3 24 ... output gate electrode, 25 ... first n + type impurity region, 26 ... amplifier, 27 ... second n + type impurity region, 28 ... reset electrode 29 ... Insulating film, 30a ... Signal charge before transfer, 30b ... Signal charge after transfer, 31 ... Trajectory of transferred signal charge.

Claims (5)

A second conductivity type well formed on the first conductivity type semiconductor substrate;
A first conductivity type first impurity region formed on the surface of the well, and a plurality of second conductivity type second impurity regions formed on the surface of the first impurity region at predetermined intervals. A first channel having;
A plurality of first transfer electrodes formed on the first impurity region of the transfer channel and formed perpendicular to a transfer direction of charges transferred by the transfer channel;
A plurality of second transfer electrodes formed on the second impurity region of the transfer channel and respectively formed between the plurality of first transfer electrodes;
An output gate electrode formed adjacent to and in parallel with the final stage of these second transfer electrodes;
Under the output gate electrode, the first impurity region is formed on the surface of the first impurity region so as to have a width narrower in the charge transfer direction, and has a first conductivity type having a concentration higher than that of the first impurity region. Two channels,
Formed by bonding to the end of the channel narrowing portion, the first conductivity type floating diffusion portion having a higher concentration than the channel narrowing portion;
A solid-state imaging device comprising: A third impurity region of a first conductivity type formed at a predetermined interval from the floating diffusion portion and formed at a concentration higher than the floating diffusion portion;
A reset electrode that is formed on the semiconductor layer between the floating diffusion portion and the third impurity region and discharges the charge transferred to the floating diffusion portion;
The solid-state imaging device according to claim 1, further comprising:   The potential formed by the second channel is higher than the potential formed by the first impurity region and lower than the potential formed by the floating diffusion portion. The solid-state imaging device according to claim 1.   2. The solid-state imaging device according to claim 1, wherein the second impurity region is formed at a plurality of concentrations so that a potential formed thereby increases in a charge transfer direction.   The solid-state imaging device according to claim 1, wherein the first and second transfer electrodes and the output gate electrode are formed with substantially the same width.

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