JP2010056301A5 - - Google Patents
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- JP2010056301A5 JP2010056301A5 JP2008219799A JP2008219799A JP2010056301A5 JP 2010056301 A5 JP2010056301 A5 JP 2010056301A5 JP 2008219799 A JP2008219799 A JP 2008219799A JP 2008219799 A JP2008219799 A JP 2008219799A JP 2010056301 A5 JP2010056301 A5 JP 2010056301A5
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- circuit
- transistor
- mos transistor
- channel mos
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Claims (6)
第2の埋め込みチャネル型トランジスタまたは第1の表面チャネル型トランジスタで構成される低ノイズ回路以外のアナログ回路と、
第2の表面チャネル型トランジスタで構成されるデジタル回路と、
を半導体基板上に備え、
前記第1の埋め込みチャネル型トランジスタでは、N型MOSFETにおいてP型のゲートにN型の不純物が注入されないように、前記P型のゲートの一端部とソース・ドレインを形成するN型の高濃度不純物領域の一端部との間にオフセットが設けられている半導体集積回路。 A low noise analog circuit composed of a first buried channel transistor;
An analog circuit other than a low noise circuit composed of a second buried channel type transistor or a first surface channel type transistor;
A digital circuit composed of a second surface channel transistor;
On a semiconductor substrate,
In the first buried channel type transistor, an N-type high-concentration impurity that forms one end of the P-type gate and a source / drain so that the N-type impurity is not implanted into the P-type gate in the N-type MOSFET. A semiconductor integrated circuit in which an offset is provided between one end of a region .
ゲート電極を前記第1のPチャネル型のMOSトランジスタのゲート電極と接続し、ソース電極を前記第1のPチャネル型のMOSトランジスタのソース電極と接続した第2のPチャネル型のMOSトランジスタと、
ドレイン電極を前記第1のPチャネル型のMOSトランジスタのドレイン電極に接続し、ゲート電極を第1の入力端子とする第1のNチャネル型のMOSトランジスタと、
ドレイン電極を前記第2のPチャネル型のMOSトランジスタのドレイン電極に接続し、ソース電極を前記第1のNチャネル型のMOSトランジスタのソース電極と接続し、ゲート電極を第2の入力端子とする第2のNチャネル型のMOSトランジスタと、
からなる増幅回路において、
前記増幅回路を構成する各々のMOSトランジスタが埋め込みチャネル型であり、前記第1および第2のNチャネル型のMOSトランジスタのゲート電極にN型の不純物が入らないように前記ゲート電極の端部とソース・ドレインを形成する高濃度不純物領域の前記ゲート電極に近いそれぞれの端部とがオフセットしていることを特徴とする半導体集積回路装置。
A first P-channel MOS transistor in which a gate electrode and a source electrode are connected;
A second P-channel MOS transistor having a gate electrode connected to the gate electrode of the first P-channel MOS transistor and a source electrode connected to a source electrode of the first P-channel MOS transistor;
A first N-channel MOS transistor having a drain electrode connected to the drain electrode of the first P-channel MOS transistor and a gate electrode serving as a first input terminal;
The drain electrode is connected to the drain electrode of the second P-channel MOS transistor, the source electrode is connected to the source electrode of the first N-channel MOS transistor, and the gate electrode is used as the second input terminal. A second N-channel MOS transistor;
In an amplifier circuit consisting of
Each MOS transistor constituting the amplifier circuit is a buried channel type, and an end portion of the gate electrode is arranged so that N-type impurities do not enter the gate electrodes of the first and second N-channel MOS transistors. A semiconductor integrated circuit device characterized in that a high concentration impurity region forming a source / drain is offset from each end close to the gate electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008219799A JP5394680B2 (en) | 2008-08-28 | 2008-08-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008219799A JP5394680B2 (en) | 2008-08-28 | 2008-08-28 | Semiconductor integrated circuit device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010056301A JP2010056301A (en) | 2010-03-11 |
JP2010056301A5 true JP2010056301A5 (en) | 2011-07-21 |
JP5394680B2 JP5394680B2 (en) | 2014-01-22 |
Family
ID=42071906
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008219799A Expired - Fee Related JP5394680B2 (en) | 2008-08-28 | 2008-08-28 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
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JP (1) | JP5394680B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018125518A (en) | 2017-02-03 | 2018-08-09 | ソニーセミコンダクタソリューションズ株式会社 | Transistor and manufacturing method |
WO2018142970A1 (en) * | 2017-02-03 | 2018-08-09 | ソニーセミコンダクタソリューションズ株式会社 | Transistor and manufacturing method |
JP6997501B2 (en) * | 2017-03-24 | 2022-01-17 | 旭化成エレクトロニクス株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3282375B2 (en) * | 1994-05-25 | 2002-05-13 | 株式会社デンソー | Complementary insulated gate field effect transistor |
JP2002151599A (en) * | 2000-11-13 | 2002-05-24 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method therefor |
US6747318B1 (en) * | 2001-12-13 | 2004-06-08 | Lsi Logic Corporation | Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides |
JP2003249827A (en) * | 2002-02-26 | 2003-09-05 | Nec Microsystems Ltd | Operational amplifier |
JP2004039720A (en) * | 2002-07-01 | 2004-02-05 | Seiko Instruments Inc | Semiconductor integrated circuit device |
-
2008
- 2008-08-28 JP JP2008219799A patent/JP5394680B2/en not_active Expired - Fee Related
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