JP2003249827A - Operational amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an operational amplifier which is highly accurate and can operate at a high speed. <P>SOLUTION: This amplifier comprises a supply voltage lowering circuit 10, a differential amplification circuit 20, a power terminal on the high-potential side 1, a power terminal on a low-potential side 2, a non-inversion input terminal 4, an inversion input terminal 5, and a non-inversion output terminal 6. Gate oxide films of N-channel MOS transistors 22 and 23 in the circuit 20 and gate oxide films of P-channel MOS transistors 24 and 25 are formed thinner than those of P-channel MOS transistors 12 and 13 in the circuit 10. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier, and more particularly to an operational amplifier that is highly accurate and can operate at high speed.

[0002]

2. Description of the Related Art Recently, in a communication device or a liquid crystal display device which requires a high-speed interface, a small amplitude signal is adopted in order to shorten the rise time and fall time of an input / output signal, and the noise immunity is increased. A differential signal is used to do this.

As a conventional example of a high-precision operational amplifier that handles a small-amplitude differential signal, a configuration shown in FIG. 7 disclosed in Japanese Patent No. 3112899 is known. As shown in FIG. 7, a conventional operational amplifier has a P-channel MOS transistor 114 whose source is connected to the high potential side power supply terminal 101 and whose drain and gate are connected to each other, and whose source is connected to the high potential side power supply terminal 101. Connected and gate is P channel M
A P-channel MOS transistor 115 connected to the gate of the OS transistor 114 and a P-channel M transistor
A P-channel MOS transistor 113 connected to the drain of the OS transistor 114 and having a gate connected to the drain of the P-channel MOS transistor 115, and a drain connected to the drain of the P-channel MOS transistor 113 and the inverting output terminal 107 and a gate connected to the bias terminal 103. Channel MOS transistor 11 connected to
1 and the drain is a P-channel MOS transistor 115
Of the N-channel MOS transistor 112, the drain of which is connected to the non-inverting output terminal 106 and the gate of which is connected to the bias terminal 103, and the drain of which is connected to the source of the N-channel MOS transistor 111 and the gate of which is connected to the non-inverting input terminal 104. N-channel MOS transistor 109 and drain has N-channel MOS transistor 1
N-channel MOS transistor 110 connected to the source of 12 and the gate thereof connected to the inverting input terminal 105, and one end commonly connected to the sources of the N-channel MOS transistor 109 and N-channel MOS transistor 110 and the other end of the low-potential-side power supply Current source 10 connected to terminal 102
8 and.

The gate oxide films of the P-channel MOS transistor 114 and the P-channel MOS transistor 115, which have the same film thickness, are formed thinner than the gate oxide film of the P-channel MOS transistor 113, and have the same film thickness. N-channel MOS transistor 109 and N-channel MOS transistor 110 have the same gate oxide film thickness.
It is formed thinner than the gate oxide films of the transistor 111 and the N-channel MOS transistor 112.

That is, the conventional operational amplifier shown in FIG.
N-channel MOS transistor 10 requiring high accuracy
9 and N-channel MOS transistor 110 pair and P
Channel MOS transistor 114 and P channel MO
The pair of S-transistors 115 has a thin gate oxide film M
The P-channel MOS transistor 113 and the pair of the N-channel MOS transistor 111 and the N-channel MOS transistor 112, which are composed of OS transistors and are required to withstand the breakdown voltage of the gate oxide film, are composed of MOS transistors having a thick gate oxide film. ,
We have realized a highly accurate operational amplifier with a small input offset voltage.

[0006]

However, in the conventional operational amplifier shown in FIG. 7, in order to secure the breakdown voltage, the N channel MOS transistor 111 and the N channel MOS transistor 112 are connected to each other as an N channel MOS transistor which is a differential pair. Transistor 109 and N-channel MOS transistor 11
Since it is configured to be cascade-connected to 0, N-channel MOS transistor 1
Since the output impedances of 11 and the N-channel MOS transistor 112 become high, there arises a problem that the driving capability for the load is lowered and the high speed operation cannot be performed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an operational amplifier having high accuracy and capable of operating at high speed.

[0008]

The operational amplifier of the present invention comprises:
A power supply voltage step-down circuit that receives a first power supply voltage and outputs a second power supply voltage that is lower than the first power supply voltage, and a differential amplifier circuit that uses the second power supply voltage as the power supply voltage. The gate oxide film of the transistor included in the differential amplifier circuit is thinner than the gate oxide film of the transistor included in the power supply voltage down converter.

Further, a power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential pair which uses the second power supply voltage as a power supply voltage. A differential amplifier circuit having a transistor, wherein the gate oxide film of the differential pair transistor is thinner than the gate oxide film of the transistor of the power supply voltage down converter.

Further, a power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential amplifier which uses the second power supply voltage as a power supply voltage. A circuit, wherein the power supply voltage step-down circuit includes a transistor that operates as a current source and a resistance means, and the transistor causes a predetermined current to flow from the first power supply voltage to the resistance means. A second power supply voltage is generated, and a gate oxide film of a transistor included in the differential amplifier circuit is thinner than a gate oxide film of the transistor.

Further, a power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential amplifier which uses the second power supply voltage as a power supply voltage. A circuit, wherein the power supply voltage step-down circuit has a source connected to a high-potential-side power supply terminal to which the first power supply voltage is input and a drain connected to an output terminal of the power supply voltage step-down circuit. Resistance means connected between the drain and a low-potential-side power supply terminal to which the reference potential of the first power supply voltage is input, and the differential amplifier circuit includes a gate oxide film of the transistor. The gate oxide film of the transistor is thin.

Further, a power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential amplifier which uses the second power supply voltage as a power supply voltage. A circuit, the power supply voltage down converter has a filter, outputs the second power supply voltage through the filter, and the differential amplification is performed from a gate oxide film of a transistor included in the power supply voltage down converter. The gate oxide film of the transistor included in the circuit is thin.

Further, a power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential pair which uses the second power supply voltage as a power supply voltage. A differential amplifier circuit having a transistor, wherein the power supply voltage step-down circuit has a filter, outputs the second power supply voltage through the filter, and gate oxidation of a transistor included in the power supply voltage step-down circuit The gate oxide film of the differential pair transistor is thinner than the film.

A power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential amplifier which uses the second power supply voltage as a power supply voltage. A power supply voltage step-down circuit, a transistor operating as a current source, a resistance means, and a capacitance means connected to the output terminal of the power supply voltage step-down circuit.
And a predetermined current is applied to the first transistor by the transistor.
The second power supply voltage is generated by flowing the power supply voltage from the power supply voltage to the resistance means, and the gate oxide film of the transistor included in the differential amplifier circuit is thinner than the gate oxide film of the transistor.

Further, a power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential amplifier which uses the second power supply voltage as a power supply voltage. A circuit, wherein the power supply voltage step-down circuit has a source connected to a high-potential-side power supply terminal to which the first power supply voltage is input and a drain connected to an output terminal of the power supply voltage step-down circuit. A resistance unit connected between the drain and a low-potential-side power supply terminal to which a reference potential of the first power supply voltage is input; and a capacitance unit connected to the output end, The gate oxide film of the transistor included in the differential amplifier circuit is thinner than the gate oxide film of the transistor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of an operational amplifier according to the first embodiment of the present invention. As shown in FIG. 1, the operational amplifier according to the first embodiment of the present invention includes a power supply voltage step-down circuit 10, a differential amplifier circuit 20, and a high potential side power supply terminal 1.
A low-potential-side power supply terminal 2, a non-inverting input terminal 4, an inverting input terminal 5, and a non-inverting output terminal 6.

The power supply voltage down converter 10 includes a current source 11 and
P channel MOS transistor 12 and P channel MO
An S-transistor 13 and a resistor 14 as a resistance means,
And a step-down output terminal 3.

The differential amplifier circuit 20 includes a current source 21, an N channel MOS transistor 22, an N channel MOS transistor 23, and a P channel MOS transistor 24.
And a P-channel MOS transistor 25.

In the power supply voltage step-down circuit 10, the source of the P channel MOS transistor 12 is connected to the high potential side power supply terminal 1, and the drain of the P channel MOS transistor 12 and the gate of the P channel MOS transistor 12 are connected to each other.

One end of the current source 11 is connected to the drain of the P-channel MOS transistor 12, and the other end of the current source 11 is connected to the low potential side power supply terminal 2.

The source of the P-channel MOS transistor 13 is connected to the high potential side power supply terminal 1,
The gate of transistor 13 is connected to the gate of P-channel MOS transistor 12.

One end of the resistor 14 is connected to the drain of the P-channel MOS transistor 13, and the other end of the resistor 14 is connected to the low potential side power supply terminal 2.

The drain of the P-channel MOS transistor 13 is connected to the step-down output terminal 3 as the output terminal of the power supply voltage step-down circuit 10.

In the differential amplifier circuit 20, the P channel M
The source of the OS transistor 24 is connected to the step-down output terminal 3, and the drain of the P-channel MOS transistor 24 and the gate of the P-channel MOS transistor 24 are connected to each other.

The source of the P channel MOS transistor 25 is connected to the step-down output terminal 3, and the gate of the P channel MOS transistor 25 is connected to the gate of the P channel MOS transistor 24.

The drain of N channel MOS transistor 22 is connected to the drain of P channel MOS transistor 24, and the gate of N channel MOS transistor 22 is connected to non-inverting input terminal 4.

The drain of N channel MOS transistor 23 is connected to the drain of P channel MOS transistor 25, and the gate of N channel MOS transistor 23 is connected to inverting input terminal 5.

The drain of the N-channel MOS transistor 23 is connected to the non-inverting output terminal 6.

The source of the N-channel MOS transistor 22 and the source of the N-channel MOS transistor 23 are connected to each other and connected to one end of the current source 21.
The other end of 1 is connected to the low potential side power supply terminal 2.

Gate oxide films of P-channel MOS transistor 12 and P-channel MOS transistor 13 included in power supply voltage step-down circuit 10 are formed to the same thickness.

N-channel MO of the differential amplifier circuit 20
Gate oxide films of the S-transistor 22 and the N-channel MOS transistor 23 are formed to the same thickness.

P channel MO included in the differential amplifier circuit 20
Gate oxide films of the S transistor 24 and the P channel MOS transistor 25 are formed to have the same thickness.

From the gate oxide films of the P-channel MOS transistor 12 and the P-channel MOS transistor 13 of the power supply voltage step-down circuit 10, the N-channel MOS transistor 22 and the N-channel M of the differential amplifier circuit 20 are formed.
The gate oxide film of the OS transistor 23 and the P channel M
The gate oxide films of the OS transistor 24 and the P-channel MOS transistor 25 are thinly formed.

Next, the operation of the power supply voltage down converter 10 will be described. The power supply voltage step-down circuit 10 steps down the first power supply voltage input to the high-potential-side power supply terminal 1 using the low-potential-side power supply terminal 2 as a reference potential and outputs the second power supply voltage lower than the first power-supply voltage.
The power supply voltage is output from the step-down output terminal 3 and the second power supply voltage is supplied as the power supply voltage of the differential amplifier circuit 20.

A P-channel MOS transistor 12 in which a predetermined constant current is current-mirror connected by the current source 11 is connected.
And the P-channel MOS transistor 13 folds back from the first power supply voltage, and its constant current flows from the first power supply voltage to the resistor 14 by the P-channel MOS transistor 13 operating as a current source, and both ends of the resistor 14, that is, step-down output. A second power supply voltage is generated at terminal 3.

In order to reduce the power consumption of the differential amplifier circuit 20 as much as possible, the second power supply voltage has a differential input signal applied between the non-inverting input terminal 4 and the inverting input terminal 5 and a non-inverting output terminal. The minimum voltage that can secure the dynamic range with the output signal generated in 6 is set.

P-channel MOS transistor 12 and P
In the gate oxide film of the channel MOS transistor 13,
When the power is turned on, the maximum voltage of about the first power supply voltage is applied, but it is generally known that the gate oxide film of the MOS transistor is destroyed by the electric field of about 5 V / 100 angstrom. If the first power supply voltage is 5V, 100 angstroms or more, and if the first power supply voltage is 3V, 60 angstroms or more, the P channel MOS transistor 12 and the P channel M
A gate oxide film of the OS transistor 13 is formed.

Next, the operation of the differential amplifier circuit 20 will be described. The differential input signal amplitude given between the non-inverting input terminal 4 and the inverting input terminal 5 is vi, and the output signal amplitude generated at the non-inverting output terminal 6 with the low potential side power supply terminal 2 as a reference potential is vo, N-channel MOS transistor 2
The mutual conductance of 2 and the mutual conductance of the N-channel MOS transistor 23 are equal to gm (23), the drain resistance of the N-channel MOS transistor 23 is rds (23), and the drain capacitance of the N-channel MOS transistor 23 is cds (23). And the drain resistance of the P-channel MOS transistor 25 is rds (2
5) and the drain capacitance of the P-channel MOS transistor 25 as cds (25), the small signal equivalent circuit of the differential amplifier circuit 20 can be approximated as shown in FIG. 2, and therefore the voltage gain Av is Av. = Vo ÷ vi = g
m (23) × rds (23) × rds (25) ÷ (rd
s (23) + rds (25) + jω (cds (23) +
cds (25)) × rds (23) × rds (25))
And the voltage gain Av becomes the transconductance gm (2
Proportional to 3).

The transconductance of a MOS transistor operating in the saturation region is proportional to the square root of the gate capacitance Cox per unit area, and the gate capacitance Cox per unit area is proportional to the reciprocal of the gate oxide film thickness tox. Is generally known.

Therefore, the mutual conductance gm (2
3) indicates the gate oxide film thickness tox (2 of the N-channel MOS transistor 22 and the N-channel MOS transistor 23.
Since it is proportional to the reciprocal of the square root of 3), the voltage gain Av is proportional to the reciprocal of the square root of the gate oxide film thickness tox (23).

From this, an N channel MOS forming a differential pair
Transistor 22 and N-channel MOS transistor 2
As the gate oxide film thickness tox (23) of 3 is formed thinner, the voltage gain Av becomes larger, and high-speed operation becomes possible.

FIG. 3 is an explanatory diagram of an example of actual measurement of the relative error voltage ΔVGS of the gate-source voltage when the gate oxide film thickness tox is changed as a parameter, and the relative error voltage ΔVGS represents a differential pair. It is a gate offset voltage when the drain currents of the two MOS transistors formed are balanced equally. Therefore, the relative error voltage ΔV
The smaller the GS, the more precise the signal becomes, and the higher the precision becomes.

It can be seen from FIG. 3 that, if the gate area is the same (gate length L × gate width W), the thinner the gate oxide film, the smaller the relative error voltage ΔVGS.

From this, an N channel MOS forming a differential pair
Transistor 22 and N-channel MOS transistor 2
The thinner the gate oxide film thickness tox (23) of No. 3, the more accurate the operation becomes possible.

Further, as described in Japanese Patent No. 3112899 cited in the description of the conventional operational amplifier shown in FIG. 7, the gate oxidation of the P-channel MOS transistor 24 and the P-channel MOS transistor 25, which are current mirrors, is performed. The thinner the film, the more accurately the mirror ratio becomes a current mirror, so that the N-channel MOS transistor 22 and the N-channel MOS transistor 23 are eventually connected.
By forming the pair of gate oxide films and the pair of gate oxide films of the P-channel MOS transistor 24 and the P-channel MOS transistor 25 thin, respectively, it is possible to operate with higher accuracy and at higher speed.

As described above, since the gate oxide film of the MOS transistor is destroyed by the electric field of about 5 V / 100 angstrom, the second power supply voltage supplied from the step-down output terminal 3 and the non-inverting input terminal are supplied. 4 and the inverting input terminal 5, a predetermined differential signal amplitude and a non-inverting output terminal 6 generated a predetermined output signal amplitude are taken into consideration.
N-channel MOS transistor 22 and N-channel MO
The pair of gate oxide films of the S transistor 23 and the pair of gate oxide films of the P channel MOS transistor 24 and the P channel MOS transistor 25 are formed as the minimum gate oxide film thickness which is not destroyed.

As described above, according to the operational amplifier of the first embodiment of the present invention, the power supply voltage step-down circuit 10 steps down the first power supply voltage input to the high potential side power supply terminal 1. By supplying the second power supply voltage lower than the first power supply voltage as the power supply voltage of the differential amplifier circuit 20,
Since the gate oxide film of the MOS transistor included in the differential amplifier circuit 20 can be formed thinner than the gate oxide film of the MOS transistor included in the power supply voltage step-down circuit 10, it is highly accurate and can operate at high speed. The effect that can be realized is obtained.

Next, FIG. 4 is a configuration diagram of an operational amplifier according to a second embodiment of the present invention. Second aspect of the present invention shown in FIG.
1 differs from the configuration of the operational amplifier of the first embodiment of the present invention shown in FIG. 1 in that the step-down output terminal 3 of the power supply voltage step-down circuit 10 shown in FIG.
Since only the part that is different from the power supply voltage step-down circuit 10a by including the capacitor 15 as the electrostatic capacitance means and the other components are the same, the calculation of the second embodiment of the present invention shown in FIG. The same components as those of the amplifier and the operational amplifier of the first embodiment of the present invention shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 4, the operational amplifier according to the second embodiment of the present invention includes a power supply voltage step-down circuit 10a, a differential amplifier circuit 20, a high potential side power supply terminal 1, and a low potential side power supply. A terminal 2, a non-inverting input terminal 4, an inverting input terminal 5, and a non-inverting output terminal 6 are provided.

The power supply voltage step-down circuit 10a includes a current source 11
A P-channel MOS transistor 12, a P-channel MOS transistor 13, a resistor 14, a step-down output terminal 3, and a capacitor 15.

One end of the capacitor 15 is connected to the step-down output terminal 3, and the other end of the capacitor 15 is connected to the low potential side power supply terminal 2.
Connected to.

The resistance component of the source / drain path of the P-channel MOS transistor 13 connected between the high-potential-side power supply terminal 1 and the step-down output terminal 3 and the resistor 14 and the capacitor 15 connected in parallel are used. A low pass filter is constructed.

Therefore, by outputting the second power supply voltage through this low-pass filter, the noise component contained in the first power supply voltage input to the high-potential-side power supply terminal 1 can be removed. The noise margin of the dynamic amplification circuit 20 increases.

As described above, according to the operational amplifier of the second embodiment of the present invention, it is possible to obtain the effect that it is possible to realize an operational amplifier having higher accuracy and capable of operating at high speed.

Next, FIG. 5 is a configuration diagram of an operational amplifier according to a third embodiment of the present invention. The third aspect of the present invention shown in FIG.
4 is different from the configuration of the operational amplifier of the second embodiment of the present invention shown in FIG. 4 in that the P-channel M in the differential amplifier circuit 20 shown in FIG.
The active load of the OS transistor 24 and the P-channel MOS transistor 25 is replaced with the resistance 26 and the resistance 27 to be changed to the differential amplifier circuit 20a, and only the portion in which the inverting output terminal 7 is further provided is provided. The other components are the same. Therefore, the same components as those of the operational amplifier according to the third embodiment of the present invention shown in FIG. 5 and the operational amplifier according to the second embodiment of the present invention shown in FIG. The description is omitted.

As shown in FIG. 5, the operational amplifier according to the third embodiment of the present invention includes a power supply voltage step-down circuit 10a, a differential amplifier circuit 20a, a high potential side power supply terminal 1, and a low potential side power supply. A terminal 2, a non-inverting input terminal 4, an inverting input terminal 5,
A non-inverting output terminal 6 and an inverting output terminal 7 are provided.

One end of the resistor 26 is connected to the step-down output terminal 3, and the other end of the resistor 26 is the N-channel MOS transistor 2
2 and the drain of the N-channel MOS transistor 22 is connected to the inverting output terminal 7.

One end of the resistor 27 is connected to the step-down output terminal 3, and the other end of the resistor 27 is the N-channel MOS transistor 2
3 drain.

The operational amplifier according to the present embodiment uses a CML (Cur) that handles an input / output differential signal level of about 800 mV.
The present invention can be applied to a rent mode logic type driver.

As described above, the operational amplifier according to the third embodiment of the present invention can be applied to a CML system driver, and can realize an operational amplifier with high precision and high speed operation. The effect of being able to do is obtained.

Next, FIG. 6 is a configuration diagram of an operational amplifier according to a fourth embodiment of the present invention. Fourth Embodiment of the Invention Shown in FIG.
4 is different from the configuration of the operational amplifier of the second embodiment of the present invention shown in FIG. 4 in that the P-channel M in the differential amplifier circuit 20 shown in FIG.
The active load of the OS transistor 24 and the P-channel MOS transistor 25 is the current source 28, the P-channel M
The differential amplifier circuit 20b is replaced with a differential pair including an OS transistor 29 and a P-channel MOS transistor 30.
Since only the portion provided with the inverting output terminal 7 and the other components are the same, the operational amplifier according to the fourth embodiment of the present invention shown in FIG. 6 and the present invention shown in FIG. The same components as those of the operational amplifier of the second embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 6, the operational amplifier according to the fourth embodiment of the present invention includes a power supply voltage step-down circuit 10a, a differential amplifier circuit 20b, a high potential side power supply terminal 1, and a low potential side power supply. A terminal 2, a non-inverting input terminal 4, an inverting input terminal 5,
A non-inverting output terminal 6 and an inverting output terminal 7 are provided.

The differential amplifier circuit 20b includes a current source 21 and N
Channel MOS transistor 22 and N channel MOS
Transistor 23, current source 28, P-channel MOS
Transistor 29 and P-channel MOS transistor 3
0 and.

The drain of P-channel MOS transistor 29 is connected to the drain of N-channel MOS transistor 22, the drain of N-channel MOS transistor 22 is connected to inverting output terminal 7, and the gate of P-channel MOS transistor 29 is an N-channel MOS transistor. 22 gates.

The drain of P channel MOS transistor 30 is connected to the drain of N channel MOS transistor 23, and the gate of P channel MOS transistor 30 is connected to the gate of N channel MOS transistor 23.

One end of the current source 28 is connected to the step-down output terminal 3, and the source of the P-channel MOS transistor 29 and P
The source of the channel MOS transistor 30 is connected to each other and to the other end of the current source 28.

P-channel MOS transistor 29 and P
The gate oxide films of the channel MOS transistors 30 are formed to have the same thickness, and the power supply voltage down converter 10
Is formed thinner than the gate oxide films of the P-channel MOS transistor 12 and the P-channel MOS transistor 13 included in.

The operational amplifier according to the present embodiment includes an N channel MOS transistor 22 and a P channel MOS transistor 29, and an N channel MOS transistor 23 and a P channel MOS transistor 23.
Since the channel MOS transistor 30 and the channel MOS transistor 30 respectively perform push-pull operation, the input / output differential signal level becomes 3
LVDS (Low Voltage) handling about 00 mV
It can be applied to a Differential Signaling type driver.

As described above, according to the operational amplifier of the fourth embodiment of the present invention, it is possible to apply the operational amplifier to an LVDS system driver and realize an operational amplifier with high precision and high speed operation. The effect of being able to do is obtained.

[0070]

The effect of the present invention is that it is possible to realize a highly accurate operational amplifier which can operate at high speed.

[0071]

[Brief description of drawings]

FIG. 1 is a configuration diagram of an operational amplifier according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a differential amplifier circuit.

FIG. 3 is an explanatory diagram of an actual measurement example of a relative error voltage ΔVGS of a gate-source voltage.

FIG. 4 is a configuration diagram of an operational amplifier according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of an operational amplifier according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of an operational amplifier according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional operational amplifier.

[Explanation of symbols]

1 High potential side power supply terminal 2 Low potential side power supply terminal 3 Step-down output terminal 4 Non-inverting input terminal 5 Inverting input terminal 6 Non-inverting output terminal 7 Inversion output terminal 10 Power supply voltage step-down circuit 10a Power supply voltage step-down circuit 11 current source 12 P-channel MOS transistor 13 P-channel MOS transistor 14 Resistance 15 capacitors 20 Differential amplifier circuit 20a differential amplifier circuit 20b differential amplifier circuit 21 Current source 22 N-channel MOS transistor 23 N-channel MOS transistor 24 P-channel MOS transistor 25 P-channel MOS transistor 26 Resistance 27 Resistance 28 Current source 29 P-channel MOS transistor 30 P-channel MOS transistor 101 High potential side power supply terminal 102 Low potential side power supply terminal 103 Bias terminal 104 Non-inverting input terminal 105 Inverting input terminal 106 Non-inverting output terminal 107 Inversion output terminal 108 current source 109 N-channel MOS transistor 110 N-channel MOS transistor 111 N-channel MOS transistor 112 N-channel MOS transistor 113 P-channel MOS transistor 114 P-channel MOS transistor 115 P-channel MOS transistor

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F048 AA00 AB10 AC03 AC10 BB16                 5J066 AA01 AA12 AA47 CA65 FA16                       HA10 HA17 HA25 HA29 KA05                       KA09 KA18 MA17 MA21 ND01                       ND14 ND22 ND23 PD02 TA02                 5J500 AA01 AA12 AA47 AC65 AF16                       AH10 AH17 AH25 AH29 AK05                       AK09 AK18 AM17 AM21 AT02                       DN01 DN14 DN22 DN23 DP02

Claims (8)

[Claims] 1. A power supply voltage step-down circuit that receives a first power supply voltage and outputs a second power supply voltage that is lower than the first power supply voltage, and a differential amplifier that uses the second power supply voltage as the power supply voltage. And a gate oxide film of a transistor included in the differential amplifier circuit is thinner than a gate oxide film of a transistor included in the power supply voltage down converter. 2. A power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential pair which uses the second power supply voltage as a power supply voltage. A differential amplifier circuit including a transistor, wherein the gate oxide film of the differential pair transistor is thinner than the gate oxide film of the transistor included in the power supply voltage down converter. 3. A power supply voltage step-down circuit that receives a first power supply voltage and outputs a second power supply voltage that is lower than the first power supply voltage, and a differential amplifier that uses the second power supply voltage as the power supply voltage. A circuit, wherein the power supply voltage step-down circuit includes a transistor that operates as a current source and a resistance means, and the transistor causes a predetermined current to flow from the first power supply voltage to the resistance means. An operational amplifier characterized in that a gate oxide film of a transistor included in the differential amplifier circuit is thinner than a gate oxide film of the transistor by generating a second power supply voltage. 4. A power supply voltage step-down circuit that receives a first power supply voltage and outputs a second power supply voltage that is lower than the first power supply voltage, and a differential amplifier that uses the second power supply voltage as the power supply voltage. A circuit, wherein the power supply voltage step-down circuit is the first
A transistor having a source connected to the high-potential-side power supply terminal to which the power supply voltage is input and a drain connected to the output terminal of the power supply voltage down converter, and a reference potential of the drain and the first power supply voltage are input. And a resistance means connected between the low potential side power supply terminal and the low potential side power supply terminal, wherein the gate oxide film of the transistor included in the differential amplifier circuit is thinner than the gate oxide film of the transistor. 5. A power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential amplifier which uses the second power supply voltage as a power supply voltage. A circuit, the power supply voltage down converter has a filter, outputs the second power supply voltage through the filter, and the differential amplification is performed from a gate oxide film of a transistor included in the power supply voltage down converter. An operational amplifier characterized in that a gate oxide film of a transistor included in a circuit is thin. 6. A power supply voltage step-down circuit which receives a first power supply voltage and outputs a second power supply voltage lower than the first power supply voltage, and a differential pair which uses the second power supply voltage as a power supply voltage. A differential amplifier circuit having a transistor, wherein the power supply voltage step-down circuit has a filter, outputs the second power supply voltage through the filter, and gate oxidation of a transistor included in the power supply voltage step-down circuit An operational amplifier characterized in that the gate oxide film of the differential pair transistor is thinner than the film. 7. A power supply voltage step-down circuit that receives a first power supply voltage and outputs a second power supply voltage that is lower than the first power supply voltage, and a differential amplifier that uses the second power supply voltage as the power supply voltage. A circuit, wherein the power supply voltage step-down circuit has a transistor that operates as a current source, a resistance means, and a capacitance means that is connected to an output terminal of the power supply voltage step-down circuit. A predetermined current is caused to flow from the first power supply voltage to the resistance means to generate the second power supply voltage, and the gate oxide film of the transistor included in the differential amplifier circuit is thinner than the gate oxide film of the transistor. Characteristic operational amplifier. 8. A power supply voltage step-down circuit that receives a first power supply voltage and outputs a second power supply voltage that is lower than the first power supply voltage, and a differential amplifier that uses the second power supply voltage as the power supply voltage. A circuit, wherein the power supply voltage step-down circuit is the first
A transistor having a source connected to the high-potential-side power supply terminal to which the power supply voltage is input and a drain connected to the output terminal of the power supply voltage down converter, and a reference potential of the drain and the first power supply voltage are input. A gate of a transistor included in the differential amplifier circuit, which includes a resistance unit connected to a low-potential-side power supply terminal and a capacitance unit connected to the output terminal, and a gate oxide film of the transistor. An operational amplifier characterized by a thin oxide film.