JPH09116349A - Operational amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the through rate of an operational amplifier without causing the extreme increase of power consumption nor deterioration of the small signal characteristic by turning on 5th or 6th transistor TR to supply the current flowing there to an output terminal when a potential difference is produced between a non-inverting input voltage and an inverting input voltage. SOLUTION: An operational amplifier having a non-inverting input terminal 3, an inverting input terminal 4 and an output terminal 5 consists of a differential input part 6, the 2nd and 3rd constant current sources Q4 and Q5, a cascode stage 7 and a current mirror 8 serving as an active load. The gate and the drain of a 4th TR Q12 are connected to the sources of TR Q6 and Q7 respectively, and the source of the TR Q12 is connected to a higher order power supply 1. The gate and the drain of a 6th TR Q13 are connected to the sources of the TR Q7 and Q6 respectively. Then the source of the TR Q13 is connected to the power supply 1. In such a constitution, the current consumption of the amplifier is never increased in a steady state even when the non-inverted input voltage Vin+ suddenly rises up to Vin+>>Vin-.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an operational amplifier.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration diagram of a conventional folded cascode type operational amplifier. Here, the case where the input differential transistor pair Q1, Q2 is an NMOS is shown. As shown in FIG. 4, the differential stage 6 includes a transistor pair Q1 and Q2 whose sources are coupled to each other, and a constant current source formed by a transistor Q3 whose gate biases the transistor pair to which a constant bias voltage Vb1 is applied. It The output current of the differential stage is P when the constant bias voltage Vb2 is applied to the gate.
The cascode stage 7 formed by the PMOS transistors Q6 and Q7, which is folded back by the constant current source formed by the MOS transistors Q4 and Q5 and has a constant bias voltage Vb3 applied to the gate, passes through the NMOS transistor.
It is poured into an active load by a current mirror 8 formed of transistors Q8 to Q11. Here, CL is a load capacitance.

[0003]

In the conventional folded cascode type operational amplifier as described above, the slew rate at the time of inputting a large signal is determined by the bias current of the differential stage 6, that is, the constant current by the transistor Q3. It is the source current Io. Here, the current value of the constant current source by the transistors Q4 and Q5 is also Io. In the steady state, that is, in the state where the virtual short is established, the currents flowing through the transistors Q1 and Q2 are both Io / 2.

Now, the input Vin + rises at a stretch and Vin + >> Vin-
Then, the transistor Q2 is cut off, and the bias current Io of the differential stage all flows through the transistor Q1. Therefore, the currents flowing through the transistors Q6 and Q7 of the cascode stage 7 are 0 and Io, respectively, and the load capacitance CL is charged by the current Io output through the transistor Q7. Therefore, the voltage change rate (slew rate) Sr of the output node is expressed by (Equation 1).

[0005]

(Equation 1)

On the contrary, the input Vin + suddenly drops and Vin + << Vi
If the state becomes n-, the transistor Q1 will be cut off, and the bias current Io of the differential stage will be completely reduced by the transistor Q2.
To flow to. Therefore, the currents flowing through the transistors Q6 and Q7 of the cascode stage 7 are Io and 0, respectively, but the current Io flowing through the transistor Q6 is equal to that of the transistor Q8.
The load capacitance CL is discharged with the current Io because it is current mirrored by the active load composed of ~ Q11. Therefore, the output node voltage change rate (slew rate)
Becomes Io / CL as when rising.

Therefore, in order to improve the slew rate, it is necessary to increase the bias current Io of the differential stage, but for that purpose, it is necessary to increase the current of the constant current source by the transistors Q4 and Q5. This causes a large increase in power. Further, if the bias current is increased, not only the power consumption is increased, but also the small signal characteristic is deteriorated. For example, the small signal voltage gain Av is represented by (Equation 2). Here, the output conductances g2, g5, g11 increase in proportion to the current, the output resistances rd7, rd9 decrease in inverse proportion to the current, and the mutual conductances gm1, gm7, gm9 increase in proportion to the current route. Therefore, small signal voltage gain Av
Will decrease with increasing current.

[0008]

(Equation 2)

The present invention has been made in view of the above problems, and an object of the present invention is to significantly improve the large signal characteristics of an operational amplifier without causing a large increase in power consumption and deterioration of small signal characteristics. .

[0010]

In order to achieve the above-mentioned object, a solution provided by the invention of claim 1 is a first polarity first and second transistor whose sources are connected to each other, and the first transistor. And a differential input section composed of a first constant current source composed of a transistor of the first polarity connected to the source of the second transistor, and second and third composed of a transistor of the second polarity. A constant current source, a cascode stage composed of third and fourth transistors of a second polarity having a predetermined bias voltage applied to its gate, and a current mirror composed of transistors of a first polarity, The drain of the first transistor, the second constant current source and the source of the third transistor are connected, the drain of the second transistor is connected to the third constant current source and the source of the fourth transistor, and the third To For an operational amplifier having a structure in which the drain of a transistor is connected to the input of the current mirror, and the drain of a fourth transistor is connected to the output of the current mirror, and the gate is connected to the source of the third transistor. And the drain is connected to the source or drain of the fourth transistor, the source is connected to the node of the second polarity and the gate is connected to the source of the fourth transistor, and the gate is connected to the source of the fourth transistor. And the drain is connected to the source or drain of the third transistor, and the source is connected to the node to which a predetermined voltage is applied. The sixth transistor of the second polarity is provided.

According to a second aspect of the present invention, a solution is provided in which a resistor is provided between the sources of the fifth transistor and the sixth transistor according to the first aspect and a node to which a predetermined voltage is applied. And

According to a third aspect of the present invention, a drain and a gate are connected between the sources of the fifth transistor and the sixth transistor according to claim 1 and a node to which a predetermined voltage is applied. The second polarity transistor is provided.

According to a fourth aspect of the present invention, there is provided a second polarity transistor in which a drain and a gate are connected between the source and the resistance of the fifth transistor and the sixth transistor according to the second aspect. Is provided.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION In the constitution of the invention of claim 1,
The gate of the first transistor serves as a non-inverting input terminal, the gate of the second transistor serves as an inverting input terminal, and the drain of the fourth transistor serves as an output terminal. Here, for example, the transistor of the first polarity is NMOS, the transistor of the second polarity is PMOS, and the voltages of the non-inverting input terminal, the inverting input terminal, and the output terminal are represented by Vin +, Vin-, and Vout. Also,
The current values of the first, second and third constant current sources are Io.

In a state where the non-inverting input voltage and the inverting input voltage are equal, that is, Vin + = Vin- is established, the current Io of the first constant current source is supplied to the first and second transistors.
Io / 2 flows one by one. The current value of the second and third constant current sources is Io
Therefore, a current of Io-Io / 2 = Io / 2 flows through both the third and fourth transistors. The gate voltages of the third and fourth transistors or the source voltages of the fifth and sixth transistors are set so that the fifth and sixth transistors are cut off in this state. Therefore, the power consumption does not change at all in the steady state where the virtual short is established. Now, assuming that the non-inverting input voltage Vin + rapidly rises and becomes Vin + >> Vin-, the second transistor is cut off, and the current Io of the first constant current source is all in the first transistor. It comes to flow. Therefore, the current flowing through the third transistor becomes Io-Io = 0, so that the current is cut off, and the source voltage of the third transistor, that is, the gate voltage of the fifth transistor rapidly drops. Therefore, the fifth transistor is turned on, and the current flowing through the fifth transistor is added to the current Io of the third constant current source and flown into the output terminal, so that the output voltage Vout rises rapidly. Conversely, if the non-inverting input voltage Vin + drops sharply and becomes Vin + << Vin-, the first transistor is cut off and the first transistor is cut off.
All of the current Io of the constant current source of (3) flows into the second transistor. Therefore, the current flowing through the fourth transistor becomes Io-Io = 0, so that the current is cut off, and the source voltage of the fourth transistor, that is, the gate voltage of the sixth transistor rapidly drops. Therefore, the sixth transistor is turned on, and the current flowing through the sixth transistor becomes the second
In addition to the current Io of the constant current source, the current is mirrored by the current mirror and drawn from the output terminal, so that the output voltage Vout falls rapidly. In this way, the slew rate can be significantly improved without increasing the current consumption in the steady state.

According to another aspect of the present invention, the gate of the first transistor serves as a non-inverting input terminal, the gate of the second transistor serves as an inverting input terminal, and the drain of the fourth transistor serves as an output terminal. Here, for example, the transistor of the first polarity is NMOS and the transistor of the second polarity is PM.
Let OS be the voltage at the non-inverting input terminal, inverting input terminal, and output terminal represented by Vin +, Vin-, and Vout. Further, the current value of the first, second, and third constant current sources is Io.

When the non-inverting input voltage and the inverting input voltage are equal, that is, Vin + = Vin- is established, the current Io of the first constant current source is applied to the first and second transistors.
Io / 2 flows one by one. The current value of the second and third constant current sources is Io
Therefore, a current of Io-Io / 2 = Io / 2 flows through both the third and fourth transistors. The gate voltages of the third and fourth transistors or the source voltages of the fifth and sixth transistors are set so that the fifth and sixth transistors are cut off in this state. Therefore, the power consumption does not change at all in the steady state where the virtual short is established. Now, assuming that the non-inverting input voltage Vin + rapidly rises and becomes Vin + >> Vin-, the second transistor is cut off, and the current Io of the first constant current source is all in the first transistor. It comes to flow. Therefore, the current flowing through the third transistor becomes Io-Io = 0, so that the current is cut off, and the source voltage of the third transistor, that is, the gate voltage of the fifth transistor rapidly drops. Therefore, the fifth transistor is turned on, and the current flowing through the fifth transistor is added to the current Io of the third constant current source and flown into the output terminal, so that the output voltage Vout rises rapidly, but When the current flowing through the transistor of No. 5 increases, the voltage generated across the first resistor increases and the gate of the fifth transistor
Since it works so as to reduce the source-to-source voltage and mitigate the increase in the current flowing through the fifth transistor, it is possible to prevent the occurrence of overshoot, ringing, etc. and obtain a stable output waveform. On the contrary, if the non-inverting input voltage Vin + drops sharply and becomes Vin + << Vin-, the first transistor is cut off, and the current Io of the first constant current source is all the second transistor. Comes to flow. For this reason,
Since the current flowing through the fourth transistor becomes Io-Io = 0, it is cut off, and the source voltage of the fourth transistor, that is, the gate voltage of the sixth transistor drops rapidly.
Therefore, the sixth transistor is turned on, the current flowing through the sixth transistor is added to the current Io of the second constant current source, and this current is further returned by the current mirror circuit and drawn from the output terminal. So the output voltage Vo
ut falls rapidly, but when the current flowing through the sixth transistor increases, the voltage generated across the second resistor increases, and the gate-source voltage of the sixth transistor decreases, so that the sixth transistor Since it works so as to mitigate the rapid increase in the current flowing through the capacitor, it is possible to prevent the occurrence of overshoot, ringing, etc. and obtain a stable output waveform. In this way, the slew rate can be significantly improved and a stable output waveform can be obtained without increasing the current consumption in the steady state.

With the configuration of the invention of claim 3 or 4, since the threshold voltage at which the fifth and sixth transistors turn on can be set, the gate voltage of the third transistor and the fourth transistor can be set. Regardless of this, the fifth and sixth transistors can be turned off in the steady state, and the same effects as the inventions of claims 1 and 2 can be obtained.

(Embodiment 1) First, Embodiment 1 according to the invention of claim 1 will be described. In the first embodiment, NMOS transistors are used for the first and second transistors Q1 and Q2.

The structure will be described with reference to FIG. 1. The sources of the transistors Q1 and Q2 are connected to each other, and they are connected to a first constant current source composed of a transistor Q3 whose gate is supplied with a bias voltage Vb1. These three transistors
The differential input section 6 is formed by Q1, Q2, and Q3. PMOS transistors Q4, Q5 with bias voltage Vb2 applied to their gates
Constitute a second constant current source and a third constant current source. A bias voltage Vb3 is applied to the gates of the third and fourth transistors Q6 and Q7 to form a cascode stage 7. The NMOS transistors Q8 to Q11 form a current mirror 8 as an active load. The drain of the transistor Q1, the drain of the transistor Q4, and the source of the transistor Q6 are connected, and the drain of the transistor Q2, the drain of the transistor Q5, and the source of the transistor Q7 are connected. The drains of the transistors Q6 and Q7 are connected to the input section and the output section of the current mirror 8, respectively.

By the differential input section 6 including the transistors Q1 to Q3, the second and third constant current sources including the transistors Q4 and Q5, the cascode stage 7 including the transistors Q6 and Q7, and the active load including the transistors Q8 to Q11. , The gate of transistor Q1 is the non-inverting input terminal 3, the transistor
A folded cascode type operational amplifier is constructed in which the gate of Q2 is the inverting input terminal 4 and the drain of the transistor Q7 is the output terminal 5.

The gate of the fifth transistor Q12 is connected to the source of the transistor Q6, the drain is connected to the source of the transistor Q7, and the source is connected to the high potential side power source 1. The sixth transistor, Q13
Has a gate connected to the source of the transistor Q7, a drain connected to the source of the transistor Q6, and a source connected to the high-potential-side power supply 1. Here, the voltages at the non-inverting input terminal, the inverting input terminal, and the output terminal are represented by Vin +, Vin-, and Vout, and the current values of the first, second, and third constant current sources are
Suppose it is set to Io.

In a state where the non-inverting input voltage and the inverting input voltage are equal, that is, a steady state in which Vin + = Vin- is established, the current Io of the transistor Q3 which is the first constant current source is
Io / 2 flows through the transistors Q1 and Q2. Since the current values of the transistors Q4 and Q5, which are the second and third constant current sources, are set to Io, the transistors Q6 and Q7 both have Io-Io.
/ 2 = Io / 2 current flows. The gate voltage Vb3 of the transistors Q6 and Q7 is normally set so that the transistors Q4 and Q5 operate near the minimum drain-source voltage Vdssat operating in the saturation region. Since this Vdssat is smaller than the threshold voltage of the normal transistor, the fifth and sixth transistors Q12 and Q13 are cut off in this state. Therefore, the power consumption does not change at all in the steady state where the virtual short is established.

Now, the non-inverting input voltage Vin + rises sharply
If Vin + >> Vin- is entered, the second transistor Q2 is cut off, and the current Io of the first constant current source by the transistor Q3 all flows to the first transistor Q1. Therefore, the current flowing through the third transistor Q6 becomes Io-Io = 0, so that the current is cut off, and the source voltage of the third transistor Q6, that is, the gate voltage of the fifth transistor Q12 drops rapidly. Therefore, the fifth transistor Q12 is turned on, and the current flowing through the transistor Q12 is added to the current Io of the third constant current source by the transistor Q5 and is flown into the output terminal, so that the output voltage Vout rises rapidly.

On the contrary, if the non-inverted input voltage Vin + suddenly drops and becomes Vin + << Vin-, the first transistor Q1 is cut off, and the current of the first constant current source by the transistor Q3 is cut off. All Io will flow into the second transistor Q2. Therefore, the current flowing through the fourth transistor Q7 becomes Io-Io = 0, so that the current is cut off and the source voltage of the fourth transistor Q7, that is, the sixth transistor Q13.
The gate voltage of the device drops rapidly. Therefore, the sixth transistor Q13 is turned on, the current flowing in the transistor Q13 is added to the current Io of the second constant current source by the transistor Q4, and this current is further mirrored by the current mirror composed of the transistors Q8 to Q11. Since it is drawn from the output terminal, the output voltage Vout falls rapidly.

As described above, the slew rate can be greatly improved without increasing the current consumption in the steady state. FIG. 5 shows a step response waveform when a voltage follower is configured by the conventional folded cascode operational amplifier shown in FIG. FIG.
FIG. 1 shows a step response waveform when a voltage follower is configured by the operational amplifier according to the first embodiment of the present invention shown in FIG. In both cases, the load capacitance CL is 5 pF. From FIGS. 5 and 6, it can be seen that the present invention significantly improves the rising and falling characteristics.

In this embodiment, the NMOS transistors are used as the input transistor pair Q1 and Q2, but the present invention is not limited to such a structure, and the same structure can be obtained even when the PMOS transistor is used. it can. In this case, the polarities of all the transistors in FIG. 1 may be exchanged, and the level of the power supply may be reversed.

(Second Embodiment) Next, a second embodiment according to the invention of claim 2 will be described. Also in the second embodiment, NMOS transistors are used for the first and second transistors Q1 and Q2.

The structure will be described with reference to FIG. 2. As in the case of the first embodiment, the sources of the transistors Q1 and Q2 are connected to each other, and the first constant voltage transistor Q3 having the gate to which the bias voltage Vb1 is applied is formed. It is connected to a current source.
The differential input section 6 is composed of these three transistors Q1, Q2, and Q3.
Are formed. The PMOS transistors Q4 and Q5 whose gates are supplied with the bias voltage Vb2 form a second constant current source and a third constant current source. A bias voltage Vb3 is applied to the gates of the third and fourth transistors Q6 and Q7 to form a cascode stage 7. The NMOS transistors Q8 to Q11 are the current mirror 8 as an active load.
Is composed.

With the transistors Q1 to Q11, the gate of the transistor Q1 is connected to the non-inverting input terminal 3 and the transistor Q2.
A folded cascode type operational amplifier having the inverting input terminal 4 as the gate of the transistor and the output terminal 5 as the drain of the transistor Q7 is configured.

The gate of the fifth transistor Q12 is connected to the source of the transistor Q6, the drain is connected to the source of the transistor Q7, and the source is the first resistor.
It is connected to the high-potential side power source 1 via R1. The gate of the sixth transistor Q13 is connected to the source of the transistor Q7, the drain is connected to the source of the transistor Q6, and the source is connected to the high-potential-side power supply 1 via the second resistor R2. Here, the voltages at the non-inverting input terminal, the inverting input terminal, and the output terminal are represented by Vin +, Vin-, and Vout, and the current values of the first, second, and third constant current sources are set to Io. And

In a state where the non-inverting input voltage and the inverting input voltage are equal, that is, a steady state in which Vin + = Vin- is established, the current Io of the transistor Q3 which is the first constant current source is
Io / 2 flows through the transistors Q1 and Q2. Since the current values of the transistors Q4 and Q5, which are the second and third constant current sources, are set to Io, the transistors Q6 and Q7 both have Io-Io.
/ 2 = Io / 2 current flows. The gate voltage Vb3 of the transistors Q6 and Q7 is normally set so that the transistors Q4 and Q5 operate near the minimum drain-source voltage Vdssat operating in the saturation region. Since this Vdssat is smaller than the threshold voltage of the normal transistor, the fifth and sixth transistors Q12 and Q13 are cut off in this state. Therefore, the power consumption does not change at all in the steady state where the virtual short is established.

Now, the non-inverting input voltage Vin + rises sharply
If Vin + >> Vin- is entered, the second transistor Q2 is cut off, and the current Io of the first constant current source by the transistor Q3 all flows to the first transistor Q1. Therefore, the current flowing through the third transistor Q6 becomes Io-Io = 0, so that the current is cut off, and the source voltage of the third transistor Q6, that is, the gate voltage of the fifth transistor Q12 drops rapidly. Therefore, the fifth transistor Q12 is turned on, and the current flowing in the transistor Q12 is added to the current Io of the third constant current source by the transistor Q5 and flows into the output terminal, so that the output voltage Vout rises rapidly, When the current flowing through the fifth transistor Q12 increases, the voltage generated across the first resistor R1 increases, and the gate-source voltage of the fifth transistor Q12 decreases to reduce the current flowing through the fifth transistor Q12. Since it works to mitigate the increase, it is possible to prevent the occurrence of overshoot, ringing, etc. and obtain a stable output waveform.

On the contrary, if the non-inverted input voltage Vin + suddenly drops and becomes Vin + << Vin-, the first transistor Q1 is cut off and the current of the first constant current source by the transistor Q3 is cut off. All Io will flow into the second transistor Q2. Therefore, the current flowing through the fourth transistor Q7 becomes Io-Io = 0, so that the current is cut off and the source voltage of the fourth transistor Q7, that is, the sixth transistor Q13.
The gate voltage of the device drops rapidly. Therefore, the sixth transistor Q13 is turned on, the current flowing in the transistor Q13 is added to the current Io of the second constant current source by the transistor Q4, and this current is further mirrored by the current mirror composed of the transistors Q8 to Q11. The output voltage Vout falls rapidly because it is drawn from the output terminal.
When the current flowing through the transistor Q13 of the sixth transistor Q13 increases, the voltage generated across the second resistor R2 increases, and the gate-source voltage of the sixth transistor Q13 decreases, and the current flowing through the sixth transistor Q13 rapidly increases. Since it works to mitigate the increase, it is possible to prevent the occurrence of overshoot, ringing, etc. and obtain a stable output waveform.

As described above, the slew rate can be greatly improved and a stable output waveform can be obtained without increasing the current consumption in the steady state.

In this embodiment, the NMOS transistors are used for the input transistor pair Q1 and Q2, but the present invention is not limited to such a structure, and the same structure can be obtained even when the PMOS transistor is used. it can. In this case, the polarities of all the transistors in FIG. 2 may be exchanged, and the level of the power supply may be reversed.

(Third Embodiment) Next, a third embodiment according to the invention of claim 3 will be described. Also in the third embodiment, NMOS transistors are used for the first and second transistors Q1 and Q2.

The structure will be described with reference to FIG. 3. As in the case of the first and second embodiments, the sources of the transistors Q1 and Q2 are connected to each other, and the first transistor Q3 has the gate supplied with the bias voltage Vb1. Connected to a constant current source. A differential input section 6 is formed by these three transistors Q1, Q2, Q3. The PMOS transistors Q4 and Q5 whose gates are supplied with the bias voltage Vb2 form a second constant current source and a third constant current source. A bias voltage Vb3 is applied to the gates of the third and fourth transistors Q6 and Q7.
Are provided to form the cascode stage 7. The NMOS transistors Q8 to Q11 form a current mirror 8 as an active load.

With the transistors Q1 to Q11, the gate of the transistor Q1 is connected to the non-inverting input terminal 3 and the transistor Q2.
A folded cascode type operational amplifier having the inverting input terminal 4 as the gate of the transistor and the output terminal 5 as the drain of the transistor Q7 is configured.

The gate of the fifth transistor Q12 is connected to the source of the transistor Q6, the drain thereof is connected to the source of the transistor Q7, and the source of the fifth transistor Q12 is connected through the seventh transistor Q14 whose drain and gate are connected to each other. It is connected to the power supply 1 on the potential side. The gate of the sixth transistor Q13 is connected to the source of the transistor Q7, the drain is connected to the source of the transistor Q6, and the source is connected to the high potential side power supply through the eighth transistor Q15 whose drain and gate are connected. Connected to 1.

As described above, by disposing the transistor whose drain and gate are connected between the sources of the fifth and sixth transistors and the high-potential-side power supply 1, the fifth and sixth transistors are provided. Since the threshold voltage to be turned on can be controlled, the fifth and sixth transistors can be turned off in the steady state regardless of the potential of the bias voltage Vb3, which is equivalent to those of the first and second embodiments. The effect can be obtained.

Although the fifth and sixth transistors Q14 and Q15 are provided in the first embodiment (FIG. 1) in this embodiment, the fifth and sixth transistors Q1 and Q1 are provided as shown in FIG.
It can be applied also when 4, Q15 is provided in Example 2 (FIG. 2),
Also in this case, the same effect as that of the third embodiment can be obtained.

[0043]

As described above, according to the operational amplifier of the first aspect of the present invention, in the steady state in which the virtual short circuit in which the non-inverting input voltage and the inverting input voltage are equal is established, the operational amplifier has a predetermined constant bias. When biased by a current and a potential difference is generated between the non-inverting input voltage and the inverting input voltage, one of the fifth and sixth transistors is turned on, and the current flowing in the transistor is flown into the output terminal. The slew rate can be significantly improved without significantly increasing the power consumption and degrading the small signal characteristics.

According to the operational amplifier of the present invention, the operational amplifier is biased with a predetermined constant bias current in a steady state where a virtual short circuit in which the non-inverting input voltage and the inverting input voltage are equal is established. When a potential difference occurs between the non-inverting input voltage and the inverting input voltage, one of the fifth and sixth transistors is turned on, and the current flowing in the transistor is flown into the output terminal, but the first resistor and the Since the sudden increase in the current can be alleviated by the action of the second resistor, the slew rate is greatly improved without causing a large increase in the power consumption and the deterioration of the small signal characteristic, and the overshoot and the ringing are caused. It is possible to obtain a stable output waveform by suppressing the occurrence of the above.

According to the operational amplifier of the third or fourth aspect of the invention, the threshold voltage at which the fifth and sixth transistors are turned on can be controlled.
Regardless of the gate voltages of the third transistor and the fourth transistor, the fifth and sixth transistors can be turned off in the steady state, and the same effect as that of the inventions of claims 1 and 2 can be obtained. it can.

[Brief description of the drawings]

FIG. 1 is an electrical wiring diagram of an operational amplifier according to a first embodiment of the present invention.

FIG. 2 is an electric wiring diagram of an operational amplifier according to a second embodiment of the present invention.

FIG. 3 is an electrical wiring diagram of an operational amplifier according to a third embodiment of the present invention.

FIG. 4 is an electrical wiring diagram of a conventional operational amplifier.

FIG. 5 is a step response waveform diagram when a voltage follower is configured with a conventional operational amplifier.

FIG. 6 is a step response waveform diagram when a voltage follower is configured by the operational amplifier according to the first embodiment of the present invention.

FIG. 7 is an electrical wiring diagram of an operational amplifier when the fifth and sixth transistors Q14 and Q15 are provided in FIG.

[Explanation of symbols]

 1 High-potential side power supply 2 Low-potential side power supply 3 Non-inverting input terminal 4 Inverting input terminal 5 Output terminal 6 Differential input section 7 Cascode stage 8 Current mirror

Claims (4)

[Claims] 1. A first of a first polarity whose sources are connected to each other.
And a second transistor, and a differential input section comprising a first constant current source composed of a transistor of the first polarity connected to the sources of the first and second transistors, and a transistor of the second polarity A cascode stage composed of second and third constant current sources composed of the above, a second polarity third and fourth transistor whose gate is supplied with a predetermined bias voltage, and a first polarity transistor. A configured current mirror, a drain of the first transistor, a second constant current source, and a third
The source of the second transistor is connected to the drain of the second transistor, the third constant current source is connected to the source of the fourth transistor, the drain of the third transistor is connected to the input part of the current mirror, An operational amplifier having a configuration in which the drain of the fourth transistor and the output of the current mirror are connected, the gate being connected to the source of the third transistor and the drain being connected to the source or drain of the fourth transistor. A fifth transistor having a second polarity whose source is connected to a node to which a predetermined voltage is applied, a gate connected to the source of the fourth transistor, and a drain connected to the source or drain of the third transistor And a source having a sixth transistor of a second polarity connected to a node to which a predetermined voltage is applied. Operational amplifier, characterized by. 2. The operational amplifier according to claim 1, wherein a resistor is provided between the sources of the fifth transistor and the sixth transistor and a node to which a predetermined voltage is applied. 3. Between the sources of the fifth transistor and the sixth transistor and a node to which a predetermined voltage is applied,
The operational amplifier according to claim 1, further comprising a transistor of a second polarity having a drain and a gate connected to each other. 4. The operation according to claim 2, wherein a transistor of the second polarity whose drain and gate are connected is provided between the source and the resistor of the fifth transistor and the sixth transistor. amplifier.