JP2010054691A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that applies a driving voltage to a load on the basis of stored data, and prevents a reduction in operating speed and increase in layout area. <P>SOLUTION: The semiconductor device 101 includes: a plurality of resistor storage elements M having electric resistance values corresponding to logical values of the stored data respectively, a read circuit 12 in which read currents flow through the plurality of resistor storage elements M, and a driving voltage generating circuit 11 which adds the read currents flowing through the respective resistor storage elements M, converts the added read current into the driving voltage, and applies it to the load. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that supplies a drive voltage to a load based on stored data.

  MRAM (Magnetic Random Access Memory) is a general term for a solid-state memory that stores data using the magnetization direction of a ferromagnetic material. In the MRAM, “1” and “0” correspond to whether the magnetization direction of the ferromagnetic material constituting the memory cell is parallel or antiparallel to a certain reference direction. In addition, a GMR element that utilizes a giant magnetoresistance effect (Giant Magneto Resistive effect) in reading data from a memory cell, and a magnetic tunnel effect (Tunneling Magneto Resistance effect: TMR) An MTJ (Magnetic Tunneling Junction) element or the like that utilizes the (resistive) effect) is used in the MRAM.

  The MTJ element is composed of a three-layer film of ferromagnetic layer / insulating layer / ferromagnetic layer, and a tunnel current flows through the insulating layer. The resistance value to the tunnel current changes according to the relationship between the magnetization directions of the two ferromagnetic layers.

  Here, as a method of reversing the magnetization direction of the ferromagnetic layer, there is known an external magnetization reversal method in which a current is passed in the vicinity of the memory cell to generate an external magnetic field and the magnetization direction of the ferromagnetic layer is reversed. (For example, refer nonpatent literature 1).

  As a method for reversing the magnetization direction of a ferromagnetic material, a spin injection magnetization reversal method is known (see, for example, Non-Patent Document 2). This is a method in which a current is directly applied to a memory cell to reverse the magnetization by the action of electrons' spin (direction). More specifically, this is a method of reversing the magnetization of the ferromagnetic layer by passing a current (hereinafter also referred to as a spin injection current) from one ferromagnetic layer of the TMR element to the other ferromagnetic layer. Since the spin injection current can have a smaller amount of current than the current for generating the external magnetic field, the spin injection magnetization reversal method can reduce the current consumption of the MRAM compared to the external magnetization reversal method.

By the way, an LCD driver that supplies a driving voltage to a light emitting element that irradiates light to a color filter in a display device (LCD: Liquid Crystal Display) has been developed. For example, Non-Patent Document 3 discloses a TFT driver that receives 8-bit data per pixel, generates a voltage of 256 gradations, and supplies the voltage to a TFT (Thin Film Transistor) color panel.
Takaharu Tsuji et al. "A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture", 2004 Symposium on VLSI Circuits Digest of Technical Papers pp.450-453 M. Hosomi et al. "A Novel Nonvolatile Memory with Spin torque Transfer Magnetization Switching: Spin-RAM", 2005 IEEE HD66351 (TFT Driver) 256-Grayscale TFT LCD Driver Catalog for XGA and SXGA, Renesas Technology Corporation, 2001.2

  In the LCD driver, an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) is generally used as a frame buffer for recording image data. In SRAM, data is stored by a cross-coupled inverter, and in DRAM, data is stored by storing electric charge in a capacitor. For this reason, since SRAM and DRAM output a voltage as stored data, the read stored data is a digital value. Then, it is necessary to convert storage data indicating the luminance of 256 gradations of the light emitting element into an analog value by a D / A (Digital to Analog) converter and supply it to the light emitting element as a driving voltage.

  Therefore, the conventional LCD driver has a problem that it takes both time to read stored data of the SRAM or DRAM and time to convert the stored data into an analog value by the D / A converter, and the operation speed is lowered. .

  In addition, in order to provide a D / A converter in a semiconductor device, a highly accurate resistance element is required, and there is a problem that a layout area needs to be increased in order to suppress variations in the resistance element.

  Therefore, an object of the present invention is to provide a semiconductor device capable of supplying a drive voltage to a load based on stored data and preventing a decrease in operation speed and an increase in layout area.

  According to the embodiment of the present invention, the drive voltage generation circuit adds the read currents flowing through the resistor memory elements, converts the added read current into a drive voltage, and supplies the drive voltage to the load.

  According to the embodiment of the present invention, data stored in the resistor memory element can be directly converted into an analog value without going through a digital value. Therefore, it is possible to supply the drive voltage to the load based on the stored data, and to prevent a reduction in operation speed and an increase in layout area.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

1 and 2 are diagrams showing a configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 1 and FIG. 2 representatively show a circuit corresponding to R (Red) of pixels in one vertical column of the LCD panel 201, and this circuit will be described below representatively. That is, in the semiconductor device 101, there are actually 3072 (= 1024 pixel columns × 3 colors (RGB)) circuits shown in FIGS.

  Referring to FIGS. 1 and 2, semiconductor device 101 is, for example, an LCD driver, and includes a memory array 10 including a plurality of memory cells MC arranged in a matrix, a drive voltage generation circuit 11, and a read circuit 12. , Write circuit 13, transistors TRF0-TRF7, read switching circuit RSEL, write switching circuits WSEL1, WSEL2, read switching control lines R, R_B, write switching control lines W, W_B, and write word lines WWL0-WWL767. Read word lines RWL0 to RWL767, write data lines D0 to D7, D_B0 to D_B7, bit lines BL0 to BL7, BLB0 to BLB7, and a write selection line WCSL0. Note that the semiconductor device 101 actually includes write selection lines WCSL0 to WCSL3071. The drive voltage generation circuit 11 includes current mirror circuits CM0 to CM7 and a current / voltage conversion circuit 21. The current / voltage conversion circuit 21 includes an operational amplifier and a resistor. Memory cell MC includes a TMR element (magnetoresistive element) M and a cell transistor TRC.

  Hereinafter, the rows and columns of the plurality of memory cells MC arranged in a matrix are also referred to as memory cell rows and memory cell columns, respectively.

  In addition, each of the write word lines WWL0 to WWL767 may be referred to as a write word line WWL. In addition, each of the read word lines RWL0 to RWL767 may be referred to as a read word line RWL. In addition, each of the write data lines D0 to D7 may be referred to as a write data line D. In addition, each of the bit lines BL0 to BL7 may be referred to as a bit line BL. In addition, each of the bit lines BLB0 to BLB7 may be referred to as a bit line BLB. In addition, each of write selection lines WCSL0 to WCSL3071 may be referred to as write selection line WCSL. In addition, each of the transistors TRF0 to TRF7 may be referred to as a transistor TRF. In addition, each of the current mirror circuits CM0 to CM7 may be referred to as a current mirror circuit CM.

  The memory cells belonging to the memory cell column are connected in parallel via the bit lines BL and BLB. In addition, the memory cell columns are connected in parallel via current mirror circuits CM0 to CM7 in the drive voltage generation circuit 11.

  FIG. 3 is a plan view showing the configuration of the memory cell in the semiconductor device according to the embodiment of the present invention. 4 is a cross-sectional view showing a cross section taken along line III-III of FIG. 3 of the memory cell in the semiconductor device according to the embodiment of the present invention.

  3 and 4, from the top layer, bit line BL, TMR element M, strap, two contacts, and active layer P of semiconductor substrate B are arranged in this order. The write word line WWL is arranged substantially orthogonal to the bit line BL. The read word line RWL is arranged substantially in parallel with the write word line WWL.

  Referring to FIGS. 1 and 2 again, the semiconductor device 101 receives 8-bit image data per pixel, generates an analog voltage of 256 gradations, and generates driving voltages R0-R1023, G0-G1023, and B0- B1023 is supplied to the LCD panel 201.

  The LCD panel 201 causes the light emitting elements corresponding to the pixels on the designated line to emit light with a luminance corresponding to the level of the drive voltage received from the semiconductor device 101.

  The memory array 10 shown in FIGS. 1 and 2 is used as a frame buffer, and stores 8-bit image data for 768 pixels of the LCD panel 201.

  The TMR element M has an electrical resistance value corresponding to the logical value of the stored data. That is, the electrical resistance value of the TMR element M changes according to the magnetization direction corresponding to the logical value of the stored data.

  The transistor TRC is provided corresponding to the TMR element M, and is connected in series with the corresponding TMR element M.

  The transistors TRF7 to TRF0 are turned on by a voltage supplied from the reference voltage line Vref. A constant voltage represented by “gate voltage of transistors TRF7-TRF0” − (minus) “threshold voltage” is applied to the TMR element M.

  The read circuit 12 passes a read current through the TMR element M of each memory cell column.

  The drive voltage generation circuit 11 weights and adds the read current flowing through the TMR element M of each memory cell column, converts the added read current into a drive voltage (analog signal), and supplies the drive voltage to the load.

  More specifically, the current mirror circuits CM0 to CM7 are provided corresponding to the memory cell columns, and weight the read current flowing through the corresponding memory cell columns. The current / voltage conversion circuit 21 converts the current weighted by the current mirror circuits CM0 to CM7 into a voltage.

  Write word line WWL is provided corresponding to the memory cell row. The read word line RWL is provided substantially in parallel between the write word line WWL and the ground potential corresponding to the memory cell row, and is coupled to the control electrode of the corresponding transistor TRC.

  Bit lines BL0 to BL7 and BLB0 to BLB7 are provided corresponding to the memory cell columns, are substantially orthogonal to the write word line WWL, and are electrically insulated from the write word line WWL.

  When writing data, the write circuit 13 selects at least one of the plurality of write word lines WWL and supplies a write current to the selected write word line WWL. This generates a data write magnetic field that affects the magnetization of the TMR element M belonging to the memory cell row corresponding to the selected write word line WWL.

  The write circuit 13 selects at least one of the plurality of bit lines BL and writes a write current to the selected bit line BL when writing data. As a result, a data write magnetic field acting on the magnetization of the TMR element M belonging to the memory cell column corresponding to the selected bit line BL is generated.

  Here, the write circuit 13 outputs complementary data as write data to the write data lines D0-D7 and D_B0-D_B7.

  Further, when reading the image data stored in the memory cell MC, the read circuit 12 selects the read word line RWL corresponding to the read target memory cell MC and drives it to a logic high level, and reads the read target memory. A bit line BL or BLB corresponding to the cell MC is selected and a constant voltage is applied. As a result, a read current corresponding to the logical value of the stored data is passed through the TMR element having a resistance value corresponding to the logical value of the stored data.

  Here, the resistance value of the TMR element becomes the minimum value Rmin or the maximum value Rmax according to the logical value of the stored data. Rmax = Rmin + ΔR. The current value of the read current becomes the minimum value Imin or the maximum value Imax depending on the logical value of the stored data. Imax = Imin + ΔI.

  The current mirror circuits CM7 to CM0 are 8 times, 4 times, 2 times, 1 times, 1/2 times, 1/4 times, and 1/8 times the 8-bit read current flowing through the transistors TRF7 to TRF0, respectively. , 1/16 times the weight. Then, the weighted read current is added and supplied to the current / voltage conversion circuit 21. The numbers written beside the transistors in the current mirror circuits CM7 to CM0 shown in FIG. 1 represent the transistor size ratio. That is, the size ratios of the input transistors and the output transistors of the current mirror circuits CM7 to CM0 are 1: 8, 1: 4, 1: 2, 1: 1, 1: 1/2, 1: 1/4, 1: 1/8, 1: 1/16.

  The current / voltage conversion circuit 21 converts the read current supplied from the current mirror circuits CM7 to CM0 into a drive voltage R0 and supplies it to a light emitting element (not shown) in the LCD panel 201.

  The read circuit 12 corresponds to at least one of the write word line WWL and the bit line BL in which no write current flows when the write circuit 13 passes a write current to the corresponding write word line WWL and the corresponding bit line BL. A read current is passed through the TMR element M.

  That is, when the read switching control line R is driven to a logic high level and the read switching control line R_B is driven to a logic low level, the transistor whose gate is connected to the read switching control line R in the read switching circuit RSEL. Is turned on, and the transistor whose gate is connected to the read switching control line R_B is turned off. Then, bit lines BL0-BL7 and transistors TRF0-TRF7 are electrically connected to each other, and a constant voltage is supplied to TMR elements M connected to bit lines BL0-BL7.

  In this case, in the write switching circuits WSEL1 and WSEL2, the output buffers connected to the bit lines BLB0 to BLB7 are enabled, and the output buffers connected to the bit lines BL0 to BL7 are disabled.

  Further, when the write switching control line W is driven to the logic low level and the write switching control line W_B is driven to the logic high level, the write data from the write data lines D0 to D7 is transmitted in the write switching circuit WSEL1. The signal is transmitted to the output buffer connected to lines BLB0 to BLB7, and the logic low level is transmitted to the output buffer connected to bit lines BL0 to BL7. In the write switching circuit WSEL2, the write data from the write data lines D_B0 to D_B7 is transmitted to the output buffer connected to the bit lines BLB0 to BLB7, and the output buffer connected to the bit lines BL0 to BL7 has a logic low level. Is transmitted. As a result, a write current flows through the bit lines BLB0 to BLB7 in directions corresponding to the logical values of the write data.

  On the other hand, when the read switching control line R is driven to a logic low level and the read switching control line R_B is driven to a logic high level, the transistor whose gate is connected to the read switching control line R in the read switching circuit RSEL. Is turned off, and the transistor whose gate is connected to the read switching control line R_B is turned on. Then, bit lines BLB0-BLB7 and transistors TRF0-TRF7 are electrically connected to each other, and a constant voltage is supplied to TMR element M connected to bit lines BLB0-BLB7.

  In this case, in the write switching circuits WSEL1 and WSEL2, the output buffers connected to the bit lines BLB0 to BLB7 are respectively disabled, and the output buffers connected to the bit lines BL0 to BL7 are respectively enabled.

  Further, when the write switching control line W is driven to a logic high level and the write switching control line W_B is driven to a logic low level, the write data from the write data lines D0 to D7 is transmitted in the write switching circuit WSEL1. The signal is transmitted to the output buffer connected to the lines BL0 to BL7, and the logic low level is transmitted to the output buffer connected to the bit lines BLB0 to BLB7. In the write switching circuit WSEL2, write data from the write data lines D_B0 to D_B7 is transmitted to the output buffer connected to the bit lines BL0 to BL7, and the output buffer connected to the bit lines BLB0 to BLB7 has a logic low level. Is transmitted. As a result, a write current flows through the bit lines BLB0 to BLB7 in directions corresponding to the logical values of the write data.

  FIG. 5 is a waveform diagram showing the operation of the semiconductor device according to the embodiment of the present invention. In FIG. 5, the numbers RWL and WWL indicate the numbers of the selected read word line RWL and write word line WWL. The numbers and alphabets of the WCSL indicate which drive voltage corresponding to which color of which pixel column of the LCD panel 201 is supplied to the LCD panel 201.

  Referring to FIG. 5, since it is necessary to always output a driving voltage corresponding to a pixel row to be displayed on LCD panel 201 to LCD panel 201, read word lines RWL0 to RWL767 are sequentially selected.

  Here, rewriting of the image data stored in the memory array 10 is performed every time the image is changed. For example, it is necessary to rewrite a normal television image at a frequency of 60 Hz.

  Therefore, in the semiconductor device 101, two sets of memory cell columns are provided for one pixel column of the LCD panel 201 so that output of the image data to the LCD panel 201 and rewriting of the image data to the memory array 10 are performed in parallel. Is provided. For example, when pixel data is written in the memory cell columns corresponding to the bit lines BLB0 to BLB7, the pixel data is read from the memory cell columns corresponding to the bit lines BL0 to BL7.

  That is, in the semiconductor device 101, the read circuit 12 alternately drives the read switching control lines R and R_B to a selected state, that is, one of the read switching control lines R and R_B becomes a logic high level at a certain timing. To.

  Then, the writing circuit 13 writes image data to the memory cell MC from which image data is not read. For example, when the read switching control line R is driven to a logic high level and the read switching control line R_B is driven to a logic low level, the write circuit 13 drives the write switching control line W to a logic low level, The write switching control line W_B is driven to a logic high level.

  The write circuit 13 selects a write word line WWL corresponding to a memory cell row different from the selected read word line RWL. For example, the write circuit 13 selects the write word line WWL767 when the read word line RWL0 is selected.

  Note that it is desirable to write data in all the memory cells corresponding to one write word line WWL by sequentially switching the write selection lines WCSL0 to WCSL3071 while a certain write word line WWL is selected.

  In the semiconductor device according to the embodiment of the present invention, a resistor memory element such as a TMR element used for an MRAM or the like is used as a memory element of a frame buffer. Then, the currents flowing through the TMR elements of each memory cell column are added, and a drive voltage, that is, an analog signal corresponding to the added current value is output to the LCD panel 201. With such a configuration, data stored in the TMR element can be directly converted into an analog value without going through a digital value. For this reason, unlike the conventional case where SRAM and DRAM are used as a frame buffer, it is not necessary to convert stored data into an analog value by a D / A converter and supply it to a light emitting element as a drive voltage. Accordingly, it is possible to prevent a decrease in operating speed and an increase in layout area.

  In the semiconductor device according to the embodiment of the present invention, a TMR element is used as a storage element for storing image data. Thereby, it is possible to obtain a resistance element with less variation suitable for operation compared to other resistance elements.

  For example, when a voltage of 0.3 V is applied to the resistance element to pass a current of about 10 uA, the resistance value of the resistance element is preferably about 30 kΩ. In this case, as described in Non-Patent Document 1, the size of the TMR element can be reduced. Also, FIG. As described in FIG. 6, it is relatively easy to set the resistance variation σ of the TMR element to about several percent. Therefore, in the semiconductor device according to the embodiment of the present invention, the layout area can be reduced and a highly accurate analog value can be output.

  Further, although the semiconductor device according to the embodiment of the present invention is an LCD driver including a frame buffer, the present invention is not limited to this. If the circuit that generates the analog signal by adding the current flowing through the resistance element is provided in place of the D / A converter, the operation speed can be prevented from being lowered and the layout area can be reduced even in the configuration without the frame buffer. The effect of reduction is obtained.

  In the semiconductor device according to the embodiment of the present invention, the magnetoresistive element is used as the memory element of the memory cell. However, the present invention is not limited to this. A configuration using another resistive memory element such as a phase change memory element with no number of rewrites may be used.

  Further, although the semiconductor device according to the embodiment of the present invention is an LCD driver, the present invention is not limited to this. It may be a driver that supplies a driving voltage to a plasma panel display and an organic EL (Organic Electro-Luminescence) display that require a similar driver.

  Further, when a microprocessor is provided on a semiconductor substrate and an LCD driver is provided as one of the interfaces of the microprocessor, the present invention can be applied by using a magnetoresistive element instead of the SRAM in the microprocessor. Is possible.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the structure of the semiconductor device which concerns on embodiment of this invention. 1 is a plan view showing a configuration of a memory cell in a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a III-III cross section in FIG. 3 of the memory cell in the semiconductor device according to the embodiment of the present invention. It is a wave form diagram showing operation of a semiconductor device concerning an embodiment of the invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Memory array, 11 Drive voltage generation circuit, 12 Read circuit, 13 Write circuit, 21 Current / voltage conversion circuit, 101 Semiconductor device, MC memory cell, TRF0-TRF7 transistor, RSEL read switching circuit, WSEL1, WSEL2 Write switching circuit, R, R_B Read switching control line, W, W_B Write switching control line, WWL0-WWL767 Write word line, RWL0-RWL767 Read word line, lines D0-D7, D_B0-D_B7 Write data lines, BL0-BL7, BLB0-BLB7 bits Line, WCSL0-WCSL3071 write selection line, CM0-CM7 current mirror circuit, MTMR element (magnetoresistance element), TRC cell transistor, B semiconductor substrate, P active layer

Claims (1)

A plurality of resistive storage elements each having an electrical resistance value corresponding to the logical value of the stored data;
A read circuit for flowing a read current through each of the plurality of resistor memory elements;
A semiconductor device comprising: a drive voltage generation circuit that adds a read current flowing through each of the resistor memory elements, converts the added read current into a drive voltage, and supplies the drive voltage to a load.

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