JP2010042958A - Method for producing group iii-v nitride semiconductor substrate - Google Patents

Method for producing group iii-v nitride semiconductor substrate Download PDF

Info

Publication number
JP2010042958A
JP2010042958A JP2008208022A JP2008208022A JP2010042958A JP 2010042958 A JP2010042958 A JP 2010042958A JP 2008208022 A JP2008208022 A JP 2008208022A JP 2008208022 A JP2008208022 A JP 2008208022A JP 2010042958 A JP2010042958 A JP 2010042958A
Authority
JP
Japan
Prior art keywords
substrate
nitride semiconductor
group iii
crystal
heterogeneous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008208022A
Other languages
Japanese (ja)
Other versions
JP4998407B2 (en
Inventor
Takeshi Ikeda
健 池田
Takeshi Meguro
健 目黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2008208022A priority Critical patent/JP4998407B2/en
Publication of JP2010042958A publication Critical patent/JP2010042958A/en
Application granted granted Critical
Publication of JP4998407B2 publication Critical patent/JP4998407B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Led Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for producing a group III-V nitride semiconductor substrate reducing the distribution of inclination of crystal axes within the face of the group III-V nitride semiconductor substrate. <P>SOLUTION: The method for producing a group III-V nitride semiconductor substrate includes heteroepitaxially growing a group III-V nitride semiconductor crystal on the following heterogeneous substrate 1. In the heterogeneous substrate 1, an inclination angle α of a crystal axis (a) of a crystal face as a reference of the heterogeneous substrate 1 with respect to the normal line (n) of the heterogeneous substrate surface 1a, and an inclination angle η of the crystal axis (a) at a position P of 20 mm distant in the radial direction from the center O of the heterogeneous substrate 1 with respect to the normal line (n) of the heterogeneous substrate surface 1a satisfy a relationship of 0.02°<¾η-α¾, as well as a crystal axis (a) at each point within the substrate surface 1a inclines outward in the radial direction of the heterogeneous substrate 1 with respect to the normal line (n) of the substrate surface 1a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、異種基板上にIII−V族窒化物系半導体結晶をヘテロエピタキシャル成長さ
せてIII−V族窒化物系半導体基板を得るIII−V族窒化物系半導体基板の製造方法に関する。
The present invention relates to a method for manufacturing a group III-V nitride semiconductor substrate in which a group III-V nitride semiconductor substrate is obtained by heteroepitaxial growth of a group III-V nitride semiconductor crystal on a different substrate.

窒化ガリウム(GaN)、窒化インジウムガリウム(InGaN)、窒化ガリウムアルミニウム(GaAlN)等の窒化物系半導体材料は、禁制帯幅が充分大きく、バンド間遷移も直接遷移型であるため、短波長発光素子への適用が盛んに検討されている。また、電子の飽和ドリフト速度が大きいこと、ヘテロ接合による2次元キャリアガスの利用が可能なこと等から、電子素子への応用も期待されている。   Nitride-based semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), and gallium aluminum nitride (GaAlN) have a sufficiently large forbidden band and a direct transition type between bands. Application to is actively studied. In addition, application to electronic devices is also expected due to the high saturation drift velocity of electrons and the use of a two-dimensional carrier gas by heterojunction.

既に世の中に広く普及しているシリコン(Si)や砒化ガリウム(GaAs)等は、それぞれSi基板、GaAs基板といった同種の材料からなる基板の上に、デバイスを作るためのエピタキシャル成長層を、ホモエピタキシャル成長させて使用されている。同種基板上のホモエピタキシャル成長では、成長の初期からステップフローモードで結晶成長が進行するため、結晶欠陥の発生が少なく、平坦なエピタキシャル成長表面が得られやすい。   Silicon (Si) and gallium arsenide (GaAs), which are already widely used in the world, are homoepitaxially grown on a substrate made of the same kind of material such as a Si substrate and a GaAs substrate, respectively. Have been used. In homoepitaxial growth on the same kind of substrate, crystal growth proceeds in the step flow mode from the initial stage of growth, so that there are few crystal defects and a flat epitaxial growth surface is easily obtained.

一方、窒化物系半導体は、バルク結晶成長が難しく、最近ようやく実用に耐えるレベルのGaN自立基板が開発され使われ始めた段階にあるが、現在、広く実用化されているGaN成長用の基板はサファイア基板である。このサファイア基板の上に、有機金属気相成長法(MOVPE法)や分子線気相成長法(MBE法)、ハイドライド気相成長法(HVPE法)等の気相成長法で、いったんGaNをヘテロエピタキシャル成長させ、その上に連続で、あるいは別の成長炉でデバイスを作るための窒化物系半導体のエピタキシャル層を成長させる方法が一般に用いられている。   Nitride-based semiconductors, on the other hand, are difficult to grow bulk crystals. Recently, GaN free-standing substrates of a level that can withstand practical use have recently been developed and are in use. It is a sapphire substrate. On this sapphire substrate, GaN is once heterogeneous by vapor phase growth methods such as metalorganic vapor phase epitaxy (MOVPE), molecular beam vapor phase epitaxy (MBE), and hydride vapor phase epitaxy (HVPE). A method is generally used in which an epitaxial layer of a nitride-based semiconductor is grown for epitaxial growth and a device is formed continuously or in another growth furnace.

サファイア基板は、GaNと格子定数が大きく異なるため、サファイア基板上に直接GaNを成長させたのでは単結晶膜を成長させることができない。このため、サファイア基板上に一旦500℃程度の低温でAlNやGaNのバッファ層を成長させ、この低温成長バッファ層で格子の歪みを緩和させてから、その上にGaNを成長させる方法が考案された。この低温成長窒化物層をバッファ層として用いることで、GaNの単結晶エピタキシャル成長は可能になった。
しかし、この方法でも、やはりサファイア基板と低温成長バッファ層との結晶格子のずれは如何ともし難く、成長の開始当初は前述のステップフローモードではなく、3次元島状成長モードで結晶成長が進行する。このため、こうして得られたGaNは、10〜1010cm−2もの転位密度を有している。この欠陥は、GaN系デバイス、特にLD(レーザダイオード)や紫外発光のLED(発光ダイオード)を製作する上で障害となる。
Since the lattice constant of sapphire substrate is significantly different from that of GaN, a single crystal film cannot be grown by directly growing GaN on the sapphire substrate. For this reason, a method has been devised in which a buffer layer of AlN or GaN is once grown on a sapphire substrate at a low temperature of about 500 ° C., and lattice distortion is relaxed by this low temperature growth buffer layer, and then GaN is grown thereon. It was. Using this low-temperature grown nitride layer as a buffer layer, GaN single crystal epitaxial growth has become possible.
However, even with this method, it is difficult to shift the crystal lattice between the sapphire substrate and the low-temperature growth buffer layer. At the beginning of the growth, the crystal growth proceeds in the three-dimensional island growth mode instead of the above-described step flow mode. To do. For this reason, the GaN thus obtained has a dislocation density of 10 9 to 10 10 cm −2 . This defect becomes an obstacle in manufacturing GaN-based devices, particularly LD (laser diode) and ultraviolet LED (light emitting diode).

近年、サファイアとGaNの格子定数差に起因して発生する欠陥の密度を低減する方法として、ELO(Epitaxially Lateral Overgrowth)や、FIELO、ペンデオエピタキシーといった成長技術が報告された。これらの成長技術は、サファイア等の基板上に成長させたGaN上に、SiO等でパターニングされたマスクを形成し、マスクの窓部からさらにGaN結晶を選択的に成長させて、マスク上をGaNがラテラル成長で覆うようにすることで、下地結晶からの転位の伝播を防ぐものである。これらの成長技術の開発により、GaN中の転位密度は10cm−2台程度にまで、飛躍的に低減させることができるようになった。 In recent years, growth techniques such as ELO (Epitaxially Lateral Overgrowth), FIELO, and pendeo epitaxy have been reported as methods for reducing the density of defects generated due to the difference in lattice constant between sapphire and GaN. In these growth techniques, a mask patterned with SiO 2 or the like is formed on GaN grown on a substrate such as sapphire, and further a GaN crystal is selectively grown from the window portion of the mask. By covering GaN with lateral growth, the propagation of dislocations from the underlying crystal is prevented. With the development of these growth techniques, the dislocation density in GaN can be drastically reduced to about 10 7 cm −2 .

更に、サファイア基板等の異種基板上に、転位密度を低減したGaN層を厚くエピタキシャル成長させ、成長後に下地基板から剥離して、GaN層を自立したGaN基板として用いる方法が、特許文献1、その他に種々提案されている。
特開2000−22212号公報
Further, Patent Document 1 discloses a method in which a GaN layer having a reduced dislocation density is epitaxially grown thickly on a dissimilar substrate such as a sapphire substrate, and the GaN layer is peeled off from the base substrate after growth and used as a self-supporting GaN substrate. Various proposals have been made.
JP 2000-22212 A

しかしながら、上述した従来方法で作製したGaN基板には、次のような解決すべき課題が残されていた。   However, the following problems to be solved remain in the GaN substrate manufactured by the conventional method described above.

既に述べたように、GaNの自立基板を作製するためのGaN結晶は、一度は格子定数の大きく異なるサファイア基板やGaAs基板といった異種基板上にヘテロエピタキシャル成長させられる。異種基板上に成長したGaN結晶は、下地基板となる前記異種基板との格子定数差や線膨張係数差に起因する反りが生じる。この反りは、下地基板を除去したGaN自立基板においても、顕著に観察されることが知られている。結晶成長中に既に反りが生じ始め、反った形のまま成長する場合もあるし、歪を内在したまま成長し、下地基板を除去することによって反りを生じることもある。
例えば、特許文献1では、下地基板にGaAs基板を用いて作製したGaN自立基板において、上方に凸の反りが生じる例が図示されている(特許文献1の図11、図15)。GaN基板が反っている場合、その反りに対応するように、GaN基板の結晶軸も面内で分布を持つ。このことは、特許文献1の図15を用いた説明でも指摘されている。
As described above, a GaN crystal for producing a GaN free-standing substrate is once heteroepitaxially grown on a heterogeneous substrate such as a sapphire substrate or a GaAs substrate having greatly different lattice constants. A GaN crystal grown on a heterogeneous substrate is warped due to a lattice constant difference or a linear expansion coefficient difference from the heterogeneous substrate serving as a base substrate. It is known that this warp is observed remarkably even in a GaN free-standing substrate from which the base substrate is removed. Warping has already begun to occur during crystal growth, and it may grow in a warped shape, or it may be warped by growing under the presence of strain and removing the underlying substrate.
For example, Patent Document 1 illustrates an example in which a convex warpage occurs in a GaN free-standing substrate manufactured using a GaAs substrate as a base substrate (FIGS. 11 and 15 of Patent Document 1). When the GaN substrate is warped, the crystal axis of the GaN substrate has a distribution in the plane so as to correspond to the warp. This is pointed out in the description using FIG.

GaNの自立基板は、他の半導体材料基板と同様に、表面に鏡面研磨が施された形で市販されていることが多く、見た目には平坦なGaN基板である。平坦なGaN基板であっても、研磨前の元のGaN基板が反っていると、GaN基板の結晶軸の傾きに分布が生じる原因となる。   A GaN free-standing substrate is often marketed in the form of mirror polishing on the surface, like other semiconductor material substrates, and is a flat GaN substrate in appearance. Even if it is a flat GaN substrate, if the original GaN substrate before polishing is warped, it causes a distribution in the inclination of the crystal axis of the GaN substrate.

次に、基板Wの反りによる結晶軸の傾き分布について説明する。
図8は、基板Wの結晶軸の傾きの方向をあらわすパラメータを定義するための説明図である。基板Wの表面(おもて面)S上のある任意の点Aにおいて、表面Sに対し、表面Sに最も近い低指数面(基準となる結晶面)fがある傾きを持っていたとする。このとき、低指数面fの結晶軸(結晶軸の方向)aの傾きは、表面Sの法線nに対して、表面Sに最も近い低指数面fの法線ベクトルVがどちらにどれだけ傾いているかを調べればよい。これは、X線回折測定によって、容易に知ることができる。研磨前の元の基板がどちらに反っていたかを知るには、この基板の表面Sに最も近い低指数面fの法線ベクトルVを表面Sに投影したときにできるベクトルVが、基板の面内でどちらを向いているかを見れば分かる。
Next, the inclination distribution of the crystal axis due to the warp of the substrate W will be described.
FIG. 8 is an explanatory diagram for defining parameters representing the direction of the inclination of the crystal axis of the substrate W. In FIG. It is assumed that at a certain point A on the surface (front surface) S of the substrate W, the surface S has a certain slope with a low index surface (reference crystal plane) f closest to the surface S. At this time, the inclination of the crystal axis (direction of the crystal axis) a of the low index plane f indicates how much the normal vector V of the low index plane f closest to the surface S is relative to the normal line n of the surface S. Find out if it is tilted. This can be easily known by X-ray diffraction measurement. In order to know which side the original substrate before polishing is warped, the vector V S generated when the normal vector V of the low index plane f closest to the surface S of this substrate is projected onto the surface S You can see if you are facing in the plane.

図9に、表面Sが凹の反りを持っていたGaN自立基板W(図中、鎖線で示す)の表裏面を平坦に研磨加工した後のGaN自立基板Wを示す。図9(1)は断面図であり、図9(2)は基板表面側から見た平面図である。
表面Sが凹の反りを持った研磨前の元のGaN自立基板Wでは、表面Sの各位置の法線は互いに平行ではなく、表面S上方の一点(ないし所定領域)に収束するような分布を持ち、結晶軸aも同様な分布を持つ。従って、研磨加工後のGaN自立基板Wの結晶軸aは、図9(1)に示すように、GaN自立基板W上方の一点(ないし所定領域)に収束するような分布を持つ。これを、上記ベクトルVを用いて表示したのが図9(2)であり、基板W面内のベクトルVは、いずれも基板Wの中心付近の特定部位へと向かって収束するような分布となり、且つベクトルVの大きさは、基板Wの中心側では小さく、基板Wの外周側になるほど大きくなる。
Figure 9 shows a freestanding GaN substrate W 1 after the surface S 0 is flat polished front and back surfaces of the GaN free-standing substrate W 0 had a concave warp (shown by a chain line). FIG. 9A is a cross-sectional view, and FIG. 9B is a plan view seen from the substrate surface side.
In the surface S 0 is the original GaN free-standing substrate W before polishing with a concave warpage 0 convergence, rather than the normal of the position of the surface S 0 parallel to one another, the surface S 0 above the one point (or a predetermined area) The crystal axis a has a similar distribution. Accordingly, the crystal axis a of the GaN free-standing substrate W 1 after polishing, as shown in FIG. 9 (1), having a distribution as to converge to the GaN free-standing substrate W 1 above the one point (or a predetermined region). This was displayed by using the vector V S is 9 (2), the vector V S in the substrate W 1 side are both converge toward to a specific site near the center of the substrate W 1 It becomes such a distribution, and the magnitude of the vector V S is smaller at the center of the substrate W 1, the larger becomes the outer periphery of the substrate W 1.

図9に示すような結晶軸の傾きの分布を持ったGaN基板上に、AlGaN混晶系のエピタキシャル層を成長すると、結晶軸の傾き分布に起因する面内の発光波長バラツキが生じ、歩留り低下の原因となっていた。これは、従来のSiやGaAsといった半導体材料では見られなかった問題であり、異種基板上にヘテロエピタキシャル成長させた厚膜層を基板として用いている、III−V族窒化物系半導体材料に特有の問題であると言える。   When an AlGaN mixed crystal epitaxial layer is grown on a GaN substrate having a crystal axis tilt distribution as shown in FIG. 9, in-plane emission wavelength variation caused by the crystal axis tilt distribution occurs, resulting in a decrease in yield. It was the cause. This is a problem that has not been seen in conventional semiconductor materials such as Si and GaAs, and is unique to III-V nitride semiconductor materials that use a thick film layer heteroepitaxially grown on a heterogeneous substrate as a substrate. It can be said that it is a problem.

本発明の目的は、上記課題を解決し、異種基板上に成長させて得られたIII−V族窒化
物系半導体基板が反っても、III−V族窒化物系半導体基板の面内の結晶軸の傾きの分布
を低減することができるIII−V族窒化物系半導体基板の製造方法を提供することにある
The object of the present invention is to solve the above-mentioned problems and to achieve in-plane crystals of a group III-V nitride semiconductor substrate even if the group III-V nitride semiconductor substrate obtained by growing on a different substrate is warped. An object of the present invention is to provide a method for manufacturing a group III-V nitride semiconductor substrate capable of reducing the distribution of the inclination of the axis.

本発明の第1の態様は、異種基板の中心における、前記異種基板表面の法線に対して前記異種基板の基準となる結晶面の結晶軸が傾斜している角度αと、その傾斜方向に前記異種基板の中心から半径方向に20mmの位置における、前記異種基板表面の法線に対して前記結晶軸が傾斜している角度ηとの関係が、0.02°<|η−α|であり、且つ、前
記異種基板面内の各点において前記異種基板表面の法線に対し前記結晶軸が前記異種基板の半径方向の外側に傾斜している異種基板を用い、前記異種基板上にIII−V族窒化物系
半導体結晶をヘテロエピタキシャル成長させることを特徴とするIII−V族窒化物系半導
体基板の製造方法である。
In the first aspect of the present invention, an angle α at which a crystal axis of a crystal plane serving as a reference of the heterogeneous substrate is inclined with respect to a normal line of the surface of the heterogeneous substrate at the center of the heterogeneous substrate, and an inclination direction thereof The relationship with the angle η at which the crystal axis is inclined with respect to the normal of the surface of the different substrate at a position 20 mm in the radial direction from the center of the different substrate is 0.02 ° <| η−α |. And using a heterogeneous substrate in which the crystal axis is inclined outward in the radial direction of the heterogeneous substrate with respect to the normal of the heterogeneous substrate surface at each point in the heterogeneous substrate surface, and III on the heterogeneous substrate A method for producing a group III-V nitride semiconductor substrate comprising heteroepitaxially growing a group V nitride semiconductor crystal.

前記III−V族窒化物系半導体基板は、六方晶系が好ましく、また、六方晶系で且つ基
板表面に最も近い低指数面をC面とするのがより好ましい。さらに、そのC面は、III族
面とするのが好ましい。或いは、前記III−V族窒化物系半導体基板は、六方晶系であり
、且つ基板表面に最も近い低指数面がA面、M面又はR面のいずれかとしてもよい。
前記III−V族窒化物系半導体基板の表面は、鏡面研磨加工が施されていることが好ま
しい。
The group III-V nitride semiconductor substrate is preferably hexagonal, and more preferably the C-plane is a low index plane that is hexagonal and closest to the substrate surface. Further, the C plane is preferably a group III plane. Alternatively, the group III-V nitride semiconductor substrate may be hexagonal and the low index plane closest to the substrate surface may be any one of the A plane, M plane, and R plane.
The surface of the group III-V nitride semiconductor substrate is preferably mirror-polished.

本発明の第2の態様は、第1の態様に記載のIII−V族窒化物系半導体基板の製造方法
を用いて、前記異種基板上に前記III−V族窒化物系半導体結晶をヘテロエピタキシャル
成長させた後、前記異種基板を除去することにより前記III−V族窒化物系半導体基板を
得ることを特徴とするIII−V族窒化物系半導体基板の製造方法である。
In a second aspect of the present invention, the group III-V nitride semiconductor crystal is heteroepitaxially grown on the heterogeneous substrate using the method for manufacturing a group III-V nitride semiconductor substrate according to the first aspect. Then, the heterogeneous substrate is removed to obtain the III-V group nitride semiconductor substrate, thereby producing a group III-V nitride semiconductor substrate.

本発明によれば、異種基板に所定の結晶軸の分布を与えることにより、異種基板上に成長させて得られるIII−V族窒化物系半導体基板が反っても、この反りよるIII−V族窒化物系半導体基板の面内の結晶軸の傾きの分布を低減することができる。従って、得られたIII−V族窒化物系半導体基板を用いて作製されるデバイスの面内特性のバラツキを低減
でき、大幅に歩留まりを向上できる。
According to the present invention, even if a group III-V nitride semiconductor substrate obtained by growing on a heterogeneous substrate is warped by giving a distribution of a predetermined crystal axis to the heterogeneous substrate, the III-V group caused by this warp. The distribution of the inclination of the crystal axis in the plane of the nitride semiconductor substrate can be reduced. Therefore, variations in in-plane characteristics of devices manufactured using the obtained group III-V nitride semiconductor substrate can be reduced, and the yield can be greatly improved.

以下に、本発明に係るIII−V族窒化物系半導体基板の製造方法の実施形態を図面を用
いて説明する。
Embodiments of a method for producing a group III-V nitride semiconductor substrate according to the present invention will be described below with reference to the drawings.

図1は、本実施形態で用いる異種基板を示す図である。図1(1)は異種基板の結晶軸分布を説明するための説明図、図1(2)は異種基板の結晶軸分布を示す断面図、図1(3)は図1(2)の異種基板を表面側から見た結晶軸分布を示す平面図である。   FIG. 1 is a diagram showing a heterogeneous substrate used in the present embodiment. 1A is an explanatory diagram for explaining the crystal axis distribution of a heterogeneous substrate, FIG. 1B is a cross-sectional view showing the crystal axis distribution of the heterogeneous substrate, and FIG. 1C is a heterogeneity of FIG. It is a top view which shows the crystal axis distribution which looked at the board | substrate from the surface side.

この異種基板1は、図1に示すように、表面(おもて面)1a及び裏面1bが平坦で且
つ互いに平行な、平板状の円形の基板(ウェハ)である。
異種基板1の基準となる結晶面の結晶軸aは、異種基板1の中心Oにおいて、表面1aの法線nに対して異種基板1の基準となる結晶面の結晶軸aが角度αだけ傾斜している。また、基板中心Oで結晶軸aが角度αだけ傾斜して傾斜方向に、異種基板1の中心Oから半径方向に20mmの位置において、表面1aの法線nに対して結晶軸aが角度ηだけ傾斜している。角度αと角度ηとの関係は、η−αの絶対値である|η−α|が0.02°
よりも大きく、|η−α|>0.02°となっている。
異種基板1の基準となる結晶面は、例えば、サファイア基板のような六方晶系の場合には、C面((0001)面)、A面((11−20)面)、M面((10−10)面)、R面((−1012)面)などである。
As shown in FIG. 1, the heterogeneous substrate 1 is a flat circular substrate (wafer) whose front surface (front surface) 1a and rear surface 1b are flat and parallel to each other.
The crystal axis a of the crystal plane serving as the reference of the heterogeneous substrate 1 is tilted by the angle α at the center O of the heterogeneous substrate 1 with respect to the normal n of the surface 1a. is doing. Further, the crystal axis a is inclined at an angle α at the substrate center O in the inclined direction, and at a position 20 mm in the radial direction from the center O of the heterogeneous substrate 1, the crystal axis a is at an angle η with respect to the normal n of the surface 1 a. Just tilted. The relationship between the angle α and the angle η is such that | η−α |, which is the absolute value of η−α, is 0.02 °.
It is larger, and | η−α |> 0.02 °.
For example, in the case of a hexagonal crystal system such as a sapphire substrate, the crystal plane serving as a reference for the heterogeneous substrate 1 is a C plane ((0001) plane), A plane ((11-20) plane), M plane ((( 10-10) plane), R plane ((-1012) plane), and the like.

更に、異種基板1面内の各点において、表面1aの法線nに対し結晶軸aが異種基板1の半径方向の外側に傾斜している。即ち、図1(2)に示すように、異種基板1の面内の各点における結晶軸aが、異種基板1の下方の一点(ないし所定領域)に収束するような分布を持つ。また、図1(3)は異種基板1の結晶軸aの傾きの面内分布を示したもので、図8で定義した、基準となる結晶面の法線ベクトルVを表面1a上に投影したベクトルVを用いて表示している。図1(3)に示すように、異種基板1面内のベクトルVは、いずれも基板1の中心付近の特定部位から基板1外周側へと発散するような分布であり、且つベクトルVの大きさは、基板1の中心部では小さく、基板1の外周側になるほど大きい。 Furthermore, at each point in the surface of the heterogeneous substrate 1, the crystal axis a is inclined outward in the radial direction of the heterogeneous substrate 1 with respect to the normal line n of the surface 1 a. That is, as shown in FIG. 1 (2), the crystal axis a at each point in the plane of the heterogeneous substrate 1 has a distribution that converges to one point (or a predetermined region) below the heterogeneous substrate 1. FIG. 1 (3) shows the in-plane distribution of the inclination of the crystal axis a of the heterogeneous substrate 1, and the normal vector V of the crystal plane as a reference defined in FIG. 8 is projected onto the surface 1a. The vector V S is used for display. As shown in FIG. 1 (3), the vectors V S in the surface of the heterogeneous substrate 1 are all distributed so as to diverge from a specific portion near the center of the substrate 1 to the outer peripheral side of the substrate 1, and the vector V S. Is smaller at the center of the substrate 1 and is larger toward the outer peripheral side of the substrate 1.

異種基板1面内の結晶軸aの傾きの方向は、X線回折測定により求めることができる。具体的には、結晶を回折面に対して垂直な軸の周りに回転させながら、X線の回折ピークを測定する。すると、結晶軸aが傾いている場合、ピーク位置がシフトして観測される。この回折ピークが、結晶のどの方向に対して最も大きくシフトするかを見れば、結晶軸aの傾き方向が判別できる。異種基板1の面内の複数の点で、結晶軸aの傾きを測定すれば、傾きの分布も容易に判別が可能である。   The direction of the inclination of the crystal axis a in the surface of the heterogeneous substrate 1 can be obtained by X-ray diffraction measurement. Specifically, an X-ray diffraction peak is measured while rotating the crystal around an axis perpendicular to the diffraction plane. Then, when the crystal axis a is inclined, the peak position is shifted and observed. The inclination direction of the crystal axis a can be determined by looking at which direction of the crystal the diffraction peak is shifted most greatly. If the inclination of the crystal axis a is measured at a plurality of points in the plane of the heterogeneous substrate 1, the distribution of the inclination can be easily discriminated.

一般に、サファイア基板等の異種基板上にGaN等のIII−V族窒化物系半導体層を成
長させた場合に、III−V族窒化物系半導体層の表裏面の欠陥密度差に起因した内部応力
により、分離されたIII−V族窒化物系半導体層の表面は凹状に反ってしまう。このため
、III−V族窒化物系半導体層の表裏面を研磨して平坦なIII−V族窒化物系半導体基板を作製すると、研磨加工後の基板の結晶軸は、図9(1)に示すような基板の中心付近の特定部位へと傾いた分布、或いは図9(2)に示すような基板面上のベクトルVを用いて表現すると、いずれも基板の中心付近の特定部位へと向かって収束するような分布となる。
Generally, when a group III-V nitride semiconductor layer such as GaN is grown on a heterogeneous substrate such as a sapphire substrate, internal stress caused by a difference in defect density between the front and back surfaces of the group III-V nitride semiconductor layer As a result, the surface of the separated group III-V nitride semiconductor layer is warped in a concave shape. For this reason, when the front and back surfaces of the group III-V nitride semiconductor layer are polished to produce a flat group III-V nitride semiconductor substrate, the crystal axis of the polished substrate is shown in FIG. When expressed using a distribution inclined to a specific portion near the center of the substrate as shown in FIG. 9B or a vector V S on the substrate surface as shown in FIG. The distribution converges toward the target.

異種基板上にエピタキシャル成長される窒化物半導体層は異種基板の結晶軸の分布を引き継ぐので、本実施形態の異種基板1では、上記0.02°<|η−α|の関係を満たし
、且つ異種基板1の面内の各点において異種基板1の表面1aの法線nに対し結晶軸aが異種基板1の半径方向の外側に傾斜している異種基板1を用い、即ち、上記反りによるIII−V族窒化物系半導体基板の結晶軸の半径方向の内側への傾斜角分布とは逆方向の傾斜
角分布を持つ異種基板1を用いて、反りによって生じるIII−V族窒化物系半導体基板の
結晶軸の傾きの分布を相殺して低減している。
このため、本実施形態の製造方法で得られるIII−V族窒化物系半導体基板の面内の結
晶軸の傾きの分布・バラツキは小さく、このIII−V族窒化物系半導体基板を用いて作製
されるデバイス、例えば発光素子にあっては、エピタキシャル層の結晶軸の傾き分布に起因する面内の発光波長のバラツキを低減でき、発光素子の歩留まりを大幅に向上できる。
Since the nitride semiconductor layer epitaxially grown on the heterogeneous substrate inherits the distribution of crystal axes of the heterogeneous substrate, the heterogeneous substrate 1 of the present embodiment satisfies the relationship of 0.02 << η-α | A heterogeneous substrate 1 in which the crystal axis a is inclined outward in the radial direction of the heterogeneous substrate 1 with respect to the normal line n of the surface 1a of the heterogeneous substrate 1 at each point in the plane of the substrate 1 is used. A group III-V nitride semiconductor substrate generated by warping using a heterogeneous substrate 1 having a tilt angle distribution in a direction opposite to the tilt angle distribution inward in the radial direction of the crystal axis of the group V nitride semiconductor substrate The distribution of the tilt of the crystal axis is offset and reduced.
For this reason, the distribution and variation of the in-plane crystal axis inclination of the group III-V nitride semiconductor substrate obtained by the manufacturing method of the present embodiment is small, and this group III-V nitride semiconductor substrate is used for the production. In a device to be used, for example, a light emitting element, variation in the in-plane emission wavelength due to the tilt distribution of the crystal axis of the epitaxial layer can be reduced, and the yield of the light emitting element can be greatly improved.

異種基板1の中心Oにおける結晶軸aの傾斜角度αと、中心Oから半径方向に20mm
の位置における結晶軸aの傾斜角度ηとの関係を、|η−α|>0.02°としたのは、
|η−α|が0.02°以下では、上記傾斜角分布による相殺効果が十分に得られないか
らである。
The inclination angle α of the crystal axis a at the center O of the heterogeneous substrate 1 and 20 mm in the radial direction from the center O
The relationship between the inclination angle η of the crystal axis a at the position of η is set to | η−α |> 0.02 °.
This is because if | η−α | is 0.02 ° or less, the canceling effect by the inclination angle distribution cannot be sufficiently obtained.

図2に、本発明に用いられる異種基板の他の実施形態を示す。
この実施形態の異種基板1は、図2に示すように、裏面1bは平坦で、平坦な裏面1bに対して表面1aが凹面上に形成されており、異種基板1の中心部が薄く、異種基板1の外周側になるほど厚くなっている。異種基板1内の基準となる結晶面の結晶軸aは、平坦な裏面1bに垂直な方向にほぼ一様に揃っている。このため、異種基板1の中心部では表面1aの法線nと結晶軸aとはほぼ一致し、基板中心部から離れるほど表面1aの法線nに対する結晶軸aの半径方向の外側への傾斜角が大きくなっている。図2の凹面状の表面1aの異種基板1を撓めて表面1aを平坦にしたときの、表面1aの結晶軸aの傾き分布は、図1(2)の異種基板1と同様になり、図1の異種基板1と同等の相殺効果が得られる。なお、異種基板1の裏面1bは必ずしも平坦でなくともよい。
FIG. 2 shows another embodiment of the heterogeneous substrate used in the present invention.
As shown in FIG. 2, the heterogeneous substrate 1 of this embodiment has a flat back surface 1b, a front surface 1a formed on the concave surface of the flat back surface 1b, a thin central portion of the heterogeneous substrate 1, The thickness increases toward the outer peripheral side of the substrate 1. The crystal axes a of the crystal plane serving as a reference in the heterogeneous substrate 1 are almost uniformly aligned in a direction perpendicular to the flat back surface 1b. For this reason, the normal line n of the surface 1a and the crystal axis a substantially coincide with each other at the center of the heterogeneous substrate 1, and the crystal axis a tilts outward in the radial direction with respect to the normal n of the surface 1a as the distance from the center of the substrate increases. The corner is large. When the heterogeneous substrate 1 having the concave surface 1a in FIG. 2 is bent to flatten the surface 1a, the inclination distribution of the crystal axis a of the surface 1a is the same as that of the heterogeneous substrate 1 in FIG. An offset effect equivalent to that of the different substrate 1 of FIG. 1 is obtained. Note that the back surface 1b of the heterogeneous substrate 1 is not necessarily flat.

図2の異種基板1の作製は、例えば、平坦な表面を有する異種基板に外力を加え、異種基板を湾曲させて表面を所定曲率の凸面状にした状態で、表面を平面状に研磨などした後、外力を開放することにより得られる。   2 is produced, for example, by applying an external force to the heterogeneous substrate having a flat surface and curving the heterogeneous substrate so that the surface has a convex shape with a predetermined curvature. Later, it is obtained by releasing the external force.

なお、異種基板は、サファイア基板に限らず、GaAs、SiC、ZnC、AlN、GaN等を用いることができる。また、III−V族窒化物系半導体基板には、GaN基板、
AlN基板等が挙げられる。
また、上記実施形態では、異種基板上にIII−V族窒化物系半導体層を成長させた場合
に、分離したIII−V族窒化物系半導体層の表面が凹面状に反ってしまう場合について説
明したが、本発明は、分離したIII−V族窒化物系半導体層の表面が凸面状に反ってしま
うが場合にも応用できる。具体的には、0.02°<|η−α|の関係を満たし、且つ異
種基板1の面内の各点において異種基板1の表面1aの法線nに対し結晶軸aが異種基板1の半径方向の内側に傾斜している異種基板1を用いることにより、反りによって発生するIII−V族窒化物系半導体基板の結晶軸の傾きの分布を相殺して低減することが可能で
ある。
The heterogeneous substrate is not limited to the sapphire substrate, and GaAs, SiC, ZnC, AlN, GaN, or the like can be used. In addition, the III-V group nitride semiconductor substrate includes a GaN substrate,
An AlN substrate etc. are mentioned.
In the above embodiment, the case where the surface of the separated group III-V nitride semiconductor layer is warped in a concave shape when the group III-V nitride semiconductor layer is grown on a different substrate is described. However, the present invention can also be applied to the case where the surface of the separated group III-V nitride-based semiconductor layer is warped convexly. Specifically, the relation of 0.02 << η−α | is satisfied, and the crystal axis a is different from the normal line n of the surface 1a of the heterogeneous substrate 1 at each point in the plane of the heterogeneous substrate 1. By using the dissimilar substrate 1 inclined inward in the radial direction, it is possible to offset and reduce the distribution of the inclination of the crystal axis of the group III-V nitride semiconductor substrate caused by warping.

次に、本発明の実施例を説明する。
ボイド形成剥離法(Void-assisted Separation Method:VAS法)を用いて、自立し
たGaN基板を作製した。基板の作製手順および条件は、以下の通りである。
Next, examples of the present invention will be described.
A self-supporting GaN substrate was produced using a void-assisted separation method (VAS method). The substrate manufacturing procedure and conditions are as follows.

まず、GaN成長用の下地基板である異種基板として、市販の直径2インチの単結晶サファイアC面基板を10枚準備した。これらサファイアC面基板の結晶軸(C軸)の傾き分布は、図3(a)に示すように、面内でほぼ均一であった。これら10枚の単結晶サファイアC面基板に対し、図1に示したように、基板の中心及び中心から20mm離れたオフ方向の位置にて、基板表面の法線に対する結晶軸(C軸)の傾斜角を測定した。測定結果を表1に示す。|η−α|は0.02°以下であり、基板表面の面内の結晶軸の傾き分
布には、特定傾きの分布は見られなかった。また、サファイア基板表面の中心位置と中心から半径r=20mmの位置との表面の高さの差を反り量(μm)として表1に示す。なお、表1において(表2、表3でも同じ)、基板表面を上にしたときに上方に凸の反りが生じている場合には凸、凹の反りが生じている場合には凹とし、凸、凹の次の数値は反り量の大きさを表している。例えば、試料番号No.1で「凸4」は、基板表面を上にしたと
きに上方に凸の反りを有し、基板中心から20mm離れたオフ方向の位置にて反り量が4μmであることを表している。
First, ten commercially available single-crystal sapphire C-plane substrates having a diameter of 2 inches were prepared as different substrates, which are base substrates for GaN growth. The inclination distribution of the crystal axis (C axis) of these sapphire C-plane substrates was almost uniform in the plane as shown in FIG. With respect to these ten single crystal sapphire C-plane substrates, as shown in FIG. 1, the crystal axis (C axis) with respect to the normal of the substrate surface is located at the center of the substrate and in the off-direction position 20 mm away from the center. The tilt angle was measured. The measurement results are shown in Table 1. | Η−α | is 0.02 ° or less, and no distribution of specific inclination was found in the inclination distribution of crystal axes in the plane of the substrate surface. Table 1 shows the difference in surface height between the center position of the surface of the sapphire substrate and the position of radius r = 20 mm from the center as the amount of warp (μm). In Table 1 (the same applies to Tables 2 and 3), if a convex warp is generated upward when the substrate surface is turned up, it is convex, and if a concave warp occurs, it is concave. The next numerical values of convex and concave represent the amount of warpage. For example, in sample number No. 1, “convex 4” has a convex warp upward when the substrate surface is up, and the warpage amount is 4 μm at a position in the off direction 20 mm away from the substrate center. Represents.

Figure 2010042958
Figure 2010042958

試料番号No.1〜No.5の5枚のサファイア基板を比較例(従来例)のサファイア基板(異種基板)とした。また、試料番号No.6〜No.10の5枚のサファイア基板に対して次に述べる加工を施して、実施例のサファイア基板(異種基板)とした。試料番号No.6〜No.10のサファイア基板に加工した後の、実施例のサファイア基板の試料番号をそれぞれNo.11〜No.15とする。   Five sapphire substrates of sample numbers No. 1 to No. 5 were used as sapphire substrates (different types of substrates) of a comparative example (conventional example). Further, the following processing was performed on the five sapphire substrates of sample numbers No. 6 to No. 10 to obtain sapphire substrates (heterogeneous substrates) of the examples. The sample numbers of the sapphire substrates of the examples after being processed into the sapphire substrates of sample numbers No. 6 to No. 10 are No. 11 to No. 15, respectively.

試料番号No.6〜No.10の5枚のサファイア基板10に施した加工を、図3を用いて説明する。
加工には、図3(a)に示すような球面状の凸面部3を有するセラミックプレート2を用いた。セラミックプレート2の凸面部3が、その中心Oから半径r=20mmの距離Pにおいて、d=10、20、30、40、50μmだけ曲がった一定曲率を持った5種類のセラミックプレート2を準備した。
これら5種類のセラミックプレート2の凸面部3に、ワックスを用いて、試料番号No.
6〜No.10のサファイア基板10の裏面10bをそれぞれ貼り付けた(図3(b))。
次に、セラミックプレート2の凸面部3に対応して、反りが生じたサファイア基板10の表面10aを平坦化した。まず、ダイヤモンド砥粒径が約15μmの砥石を用いて研削した。次に、定盤表面が螺旋溝に加工された錫定盤に、砥粒径3μmのダイヤモンド砥粒スラリを供給しながら定盤を回転させて研磨した。最後に、研磨布を貼り付けた定盤に、コロイダルシリカスラリを供給しながら定盤を回転させてポリッシュを行い、加工歪のない平坦な表面10aに加工した(図3(c))。
次にワックスを温め、セラミックプレー卜2からサファイア基板10を取り外した後、洗浄した(図3(d))。サファイア基板10をセラミックプレー卜2から取り外すと、セラミックプレー卜2の凸面部3に貼り付けられ、弾性変形されていたサファイア基板10が元の状態に戻り、裏面10bは平坦になり、研削加工等された表面10aは凹面状となった。これらサファイア基板10の結晶軸aの傾き分布は、加工前の同様に、裏面10bに垂直で面内でほぼ均一であった。こうして、試料番号No.11〜No.15の実施例のサファイア基板10を作製した。これら実施例のサファイア基板10は、図2に示す上記実施形態の基板1と同様な結晶軸分布を持つことになる。
Processing applied to the five sapphire substrates 10 of sample numbers No. 6 to No. 10 will be described with reference to FIG.
For processing, a ceramic plate 2 having a spherical convex surface portion 3 as shown in FIG. Five types of ceramic plates 2 having a constant curvature in which the convex surface portion 3 of the ceramic plate 2 was bent by d = 10, 20, 30, 40, 50 μm at a distance P of radius r = 20 mm from the center O were prepared. .
Using the wax on the convex surface portion 3 of these five types of ceramic plates 2, the sample number No.
The back surfaces 10b of the sapphire substrates 10 of No. 6 to No. 10 were pasted (FIG. 3B).
Next, the surface 10a of the sapphire substrate 10 where the warp occurred was flattened corresponding to the convex surface portion 3 of the ceramic plate 2. First, grinding was performed using a grindstone having a diamond abrasive grain size of about 15 μm. Next, the platen was polished by rotating the platen while supplying a diamond abrasive slurry having an abrasive particle size of 3 μm to a tin platen whose surface was processed into a spiral groove. Finally, polishing was performed by rotating the surface plate while supplying the colloidal silica slurry to the surface plate to which the polishing cloth was pasted, and processed into a flat surface 10a having no processing distortion (FIG. 3C).
Next, the wax was heated and the sapphire substrate 10 was removed from the ceramic plate 2 and then washed (FIG. 3D). When the sapphire substrate 10 is removed from the ceramic plate 2, the sapphire substrate 10 that has been affixed to the convex surface portion 3 of the ceramic plate 2 and has been elastically deformed returns to its original state, the back surface 10 b becomes flat, and grinding processing, etc. The finished surface 10a became concave. The inclination distribution of the crystal axis a of these sapphire substrates 10 was almost uniform in the plane perpendicular to the back surface 10b as before the processing. In this way, the sapphire substrate 10 of the sample numbers No. 11 to No. 15 was produced. The sapphire substrate 10 of these examples has the same crystal axis distribution as the substrate 1 of the above embodiment shown in FIG.

上記加工を施した実施例のサファイア基板10に対して、上述した試料番号No.1〜No.10のサファイア基板10と同様に、基板の中心及び中心から20mm離れたオフ方向の位置にて、基板表面10aの法線に対する結晶軸の傾斜角を測定した。測定結果を表2に示す。表面10aの法線に対するC面結晶軸の傾き分布は、図1(3)に示すように、基
板中心からの距離rが大きくなるほど、基板外周向きに大きくなる分布を持っていた。また、サファイア基板10のr=20mmの位置の反り量も表2に示す。
For the sapphire substrate 10 of the embodiment subjected to the above processing, similarly to the sapphire substrate 10 of the sample numbers No. 1 to No. 10 described above, at the position in the off direction that is 20 mm away from the center and the center of the substrate, The tilt angle of the crystal axis with respect to the normal line of the substrate surface 10a was measured. The measurement results are shown in Table 2. As shown in FIG. 1C, the inclination distribution of the C-plane crystal axis with respect to the normal of the surface 10a has a distribution that increases toward the outer periphery of the substrate as the distance r from the substrate center increases. Table 2 also shows the amount of warpage of the sapphire substrate 10 at the position of r = 20 mm.

Figure 2010042958
Figure 2010042958

次に、試料番号No.1〜No.5の比較例の単結晶サファイア基板、および試料番号No.1
1〜No.15の実施例の単結晶サファイア基板の計10枚について、VAS法により、図
4に示すように、GaNの自立基板を製造した。
Next, single-crystal sapphire substrates of comparative examples of sample numbers No. 1 to No. 5, and sample number No. 1
A total of 10 single crystal sapphire substrates of Examples 1 to No. 15 were manufactured by a VAS method as shown in FIG.

上記のようにして、サファイア基板10を用意し(工程(a))、用意したサファイア基板10上に、MOVPE法で、TMG(トリメチルガリウム)とNH(アンモニア)を原料として、アンドープGaN層11を300nm成長した(工程(b))。このGaNエピタキシャル基板上に、Ti薄膜12を20nm蒸着し(工程(c))、これを電気炉に入れて、NHを20%混合したH(水素)の気流中で、1050℃で20分間の熱処理を施し、Ti薄膜12を網目状のTiN膜14に変化させると同時に、GaN層11にボイド(空隙)を形成してボイド形成GaN層13とした(工程(d))。 The sapphire substrate 10 is prepared as described above (step (a)), and the undoped GaN layer 11 is formed on the prepared sapphire substrate 10 using TMG (trimethylgallium) and NH 3 (ammonia) as raw materials by the MOVPE method. Was grown by 300 nm (step (b)). On this GaN epitaxial substrate, a Ti thin film 12 is deposited to a thickness of 20 nm (step (c)), and this is placed in an electric furnace, and in an air stream of H 2 (hydrogen) mixed with 20% NH 3 at 1050 ° C. A heat treatment for 5 minutes was performed to change the Ti thin film 12 into a mesh-like TiN film 14, and at the same time, voids (voids) were formed in the GaN layer 11 to form a void-formed GaN layer 13 (step (d)).

これをHVPE炉に入れ、その上にGaN層15を850μm堆積した(工程(e))。HVPE成長に用いた原料は、NHとGaCl(塩化ガリウム)で、キャリアガスとしてNとHの混合ガスを用いた。成長条件は、常圧、基板温度1040℃である。GaN層15は成長終了後の降温過程においてボイド形成GaN層13を境にサファイア基板10から剥離した(工程(f))。剥離したGaN層15は、表面(おもて面)が(0001)Ga面である。 This was put in an HVPE furnace, and a GaN layer 15 was deposited thereon at 850 μm (step (e)). The raw materials used for the HVPE growth were NH 3 and GaCl (gallium chloride), and a mixed gas of N 2 and H 2 was used as a carrier gas. The growth conditions are normal pressure and a substrate temperature of 1040 ° C. The GaN layer 15 was peeled from the sapphire substrate 10 with the void-formed GaN layer 13 as a boundary in the temperature lowering process after the growth was completed (step (f)). The peeled GaN layer 15 has a (0001) Ga surface on the surface (front surface).

剥離したGaN層15をGaN自立基板16とした(工程(g))。得られたGaN自立基板16の表面(おもて面)であるGa面は、すべて凹面の形状であった(裏面は全て凸面)。また、半径r=20mm位置の反り量を測定した所、表3の結果が得られた。   The peeled GaN layer 15 was used as a GaN free-standing substrate 16 (step (g)). The Ga surface which is the front surface (front surface) of the obtained GaN free-standing substrate 16 was all concave (the back surface was all convex). Further, when the amount of warpage at the position of radius r = 20 mm was measured, the results shown in Table 3 were obtained.

Figure 2010042958
Figure 2010042958

得られたGaN自立基板16を、その表面と裏面を鏡面研磨し、厚さ400μmのGaN基板17に仕上げた。10枚のGaN基板17は、いずれも透明で、平坦な鏡面を持っており、その表面粗さは表面段差計を用いて500μm範囲をスキヤンした時のRa(算術平均粗さ)の値がすべて10nm以下となっていた。   The obtained GaN free-standing substrate 16 was mirror-polished on the front surface and the back surface to finish a GaN substrate 17 having a thickness of 400 μm. The 10 GaN substrates 17 are all transparent and have a flat mirror surface, and the surface roughness is all Ra (arithmetic mean roughness) values when scanning the 500 μm range using a surface step meter. It was 10 nm or less.

こうして作製したGaN自立基板17の、表面に対するC軸の傾き方向を調べるため、すべてのGaN基板にX線回折測定を行った。測定は、図5に黒丸で示す5点である。測定点は、基板の中央位置(1点)と、基板の中央位置を基点に基板の<1−100>方向に平行な方向に20mm離れた位置(2点)と、基板の中央位置を基点に基板の<1−100>方向に垂直な方向に20mm離れた位置(2点)との、合計5点を測定した。各点で測定されたC軸の傾きのベクトルを、基板表面に投影したときのベクトル(V)の向き、即ちC軸の傾きの方向が、基板面内でどのように分布しているかを調べた。その結果、すべてのGaN基板で、図9(2)に示すような、C軸の傾きの方向がGaN基板の内側の特定の領域に向かって収束するような分布が見られたが、面内のC軸の傾きのバラツキ(5点の測定結果において、C軸の最大傾き値と最小傾き値との差で示す)に相違が見られた。その結果を上記表3に示す。 In order to examine the inclination direction of the C axis with respect to the surface of the GaN free-standing substrate 17 thus manufactured, X-ray diffraction measurement was performed on all GaN substrates. The measurement is 5 points indicated by black circles in FIG. The measurement points are the center position (1 point) of the substrate, the position 20 points away from the center position of the substrate in the direction parallel to the <1-100> direction of the substrate (2 points), and the center position of the substrate. A total of 5 points were measured, including a position (2 points) 20 mm away in the direction perpendicular to the <1-100> direction of the substrate. The distribution of the direction of the vector (V S ) when the vector of the C-axis inclination measured at each point is projected onto the substrate surface, that is, the direction of the C-axis inclination is distributed in the substrate plane. Examined. As a result, a distribution in which the direction of the C-axis inclination converges toward a specific region inside the GaN substrate as shown in FIG. There was a difference in the variation in the inclination of the C axis (indicated by the difference between the maximum inclination value and the minimum inclination value of the C axis in the five-point measurement results). The results are shown in Table 3 above.

以上の結果から、実施例のサファイア基板を用いて作製したGaN基板では、GaN基板の成長で生じる反りに起因する結晶軸の傾きを、下地基板となるサファイア基板に逆方向の結晶軸の傾き分布を持たせることにより相殺でき、平坦加工した後のGaN基板面内の結晶軸の傾きのバラツキが、低減することを確認できた。   From the above results, in the GaN substrate manufactured using the sapphire substrate of the example, the inclination of the crystal axis due to the warp caused by the growth of the GaN substrate is different from the inclination distribution of the crystal axis in the direction opposite to the sapphire substrate as the base substrate. It was confirmed that the variation in the tilt of the crystal axis in the GaN substrate surface after flattening was reduced.

因みに、上記条件で作製した実施例の自立したGaN基板17の転位密度を測定したところ、基板中心及び中心からr=20mmの上下左右方向の面内5点(図5と同一)の分布が(3±0.9)×10cm−2と、基板面内全域にわたって均一に低転位化できて
いることが確認できた。即ち、本発明にかかる結晶軸の傾きの分布規定が、GaN基板の欠陥密度を悪くする要因にはなっていないことを確認した。
Incidentally, when the dislocation density of the self-supporting GaN substrate 17 of the example manufactured under the above conditions was measured, the distribution of 5 points in the plane in the vertical and horizontal directions r = 20 mm from the center (the same as FIG. 5) is ( 3 ± 0.9) × 10 6 cm −2, and it was confirmed that low dislocations were uniformly reduced over the entire surface of the substrate. That is, it was confirmed that the distribution regulation of the crystal axis inclination according to the present invention is not a factor that deteriorates the defect density of the GaN substrate.

このGaN基板17上に、減圧MOVPE法を用いて、図6に示す構造のLED用エピタキシャル層を成長した。成長した層は、GaN基板12側から順に、Siドープn型GaNバッファ層18、Siドープn型Al0.15GaNクラッド層19、3周期のIn
GaN−MQW(多重量子井戸)層20、Mgドープp型Al0.15GaNクラッド層
21である。エピタキシャル層18〜21の合計の厚さは、100μm以下である。
An epitaxial layer for LED having a structure shown in FIG. 6 was grown on the GaN substrate 17 by using a reduced pressure MOVPE method. The grown layers are, in order from the GaN substrate 12 side, a Si-doped n-type GaN buffer layer 18, a Si-doped n-type Al 0.15 GaN cladding layer 19, and three periods of In
A GaN-MQW (multiple quantum well) layer 20 and an Mg-doped p-type Al 0.15 GaN cladding layer 21. The total thickness of the epitaxial layers 18 to 21 is 100 μm or less.

10枚のGaN基板17のすべてに同一のLED構造のエピタキシャル層を成長し、LED用エピタキシャルウェハを作製し、ホトルミネッセンス測定で、面内の発光波長バラツキを調べた。その結果を図7に示す。
実施例のサファイア基板(試料番号No.11〜No.15)を用いて作製したGaN基板17上に形成したLEDエピタキシャル層では、比較例の市販品のサファイア基板(試料番号No.1〜No.5)を用いて作製したGaN基板17上に形成したLEDエピタキシャル層に比べ、面内の発光波長バラツキを大幅に低減することができた。
Epitaxial layers having the same LED structure were grown on all ten GaN substrates 17 to produce LED epitaxial wafers, and in-plane emission wavelength variations were examined by photoluminescence measurement. The result is shown in FIG.
In the LED epitaxial layer formed on the GaN substrate 17 produced using the sapphire substrate of the example (sample numbers No. 11 to No. 15), a commercially available sapphire substrate of the comparative example (sample numbers No. 1 to No. 1). Compared with the LED epitaxial layer formed on the GaN substrate 17 produced using 5), the in-plane emission wavelength variation could be greatly reduced.

図1は、本発明の一実施形態で用いた異種基板を示すもので、図1(1)は異種基板の結晶軸分布を説明するための説明図、図1(2)は異種基板の結晶軸分布を示す断面図、図1(3)は図1(2)の異種基板を表面側から見た結晶軸分布を示す平面図である。FIG. 1 shows a heterogeneous substrate used in one embodiment of the present invention. FIG. 1 (1) is an explanatory diagram for explaining the crystal axis distribution of the heterogeneous substrate, and FIG. 1 (2) is a crystal of the heterogeneous substrate. FIG. 1C is a cross-sectional view showing the axis distribution, and FIG. 1C is a plan view showing the crystal axis distribution when the heterogeneous substrate of FIG. 本発明の他の実施形態で用いた異種基板を示す断面図である。It is sectional drawing which shows the dissimilar board | substrate used in other embodiment of this invention. 本発明の実施例のサファイア基板(異種基板)の作製方法を示す工程図である。It is process drawing which shows the preparation methods of the sapphire substrate (heterogeneous substrate) of the Example of this invention. 実施例および比較例のサファイア基板上に、VAS法によりGaN自立基板を製造する工程を示す工程図である。It is process drawing which shows the process of manufacturing a GaN self-supporting board | substrate by the VAS method on the sapphire board | substrate of an Example and a comparative example. GaN自立基板の表面に対するC軸の傾き方向を調べるために、X線回折測定により測定した測定点を示すGaN自立基板の平面図である。FIG. 4 is a plan view of a GaN free-standing substrate showing measurement points measured by X-ray diffraction measurement in order to examine the inclination direction of the C axis with respect to the surface of the GaN free-standing substrate. GaN基板上に、LED構造のエピタキシャル成長層を積層したLED用エピタキシャルウェハの構造を示す断面図である。It is sectional drawing which shows the structure of the epitaxial wafer for LED which laminated | stacked the epitaxial growth layer of LED structure on the GaN substrate. 図6のLED用エピタキシャルウェハに対して、ホトルミネッセンス測定で基板面内の発光波長のバラツキを測定した結果を示すグラフである。It is a graph which shows the result of having measured the variation in the light emission wavelength in a substrate surface by the photoluminescence measurement with respect to the epitaxial wafer for LED of FIG. 基板Wの反りによる結晶軸の傾き分布を表すパラメータを定義するための説明図である。FIG. 5 is an explanatory diagram for defining a parameter representing a tilt distribution of crystal axes due to warpage of a substrate W. 表面が凹の反りを持っていたGaN自立基板の表裏面を平坦に研磨加工した後のGaN自立基板を示すもので、図9(1)はGaN自立基板の結晶軸分布を示す断面図であり、図9(2)はGaN自立基板の表面側から見たの結晶軸分布を示す平面図である。FIG. 9 (1) is a cross-sectional view showing the crystal axis distribution of the GaN free-standing substrate after the front and back surfaces of the GaN free-standing substrate having a concave warpage are polished flatly. FIG. 9B is a plan view showing the crystal axis distribution as viewed from the surface side of the GaN free-standing substrate.

符号の説明Explanation of symbols

1 異種基板
1a 表面
1b 裏面
2 セラミックプレート
3 凸面部
10 サファイアC面基板(サファイア基板)
10a 表面
10b 裏面
16 GaN自立基板(GaN基板)
17 GaN自立基板(GaN基板)
a 結晶軸
n 表面の法線
O 基板表面の中心
α 傾斜した角度
η 傾斜した角度
V 法線ベクトル
法線ベクトルを表面上に投影したベクトル
W 基板
表面が凹の反りを持ったGaN自立基板
の表裏面を平坦に研磨加工した後のGaN自立基板
DESCRIPTION OF SYMBOLS 1 Different board | substrate 1a Front surface 1b Back surface 2 Ceramic plate 3 Convex part 10 Sapphire C surface board (sapphire substrate)
10a Front surface 10b Back surface 16 GaN free-standing substrate (GaN substrate)
17 GaN free-standing substrate (GaN substrate)
a crystal axis n surface normal O center of substrate surface α tilted angle η tilted angle V normal vector V S normal vector projected onto the surface W substrate W 0 GaN with concave warpage Free-standing substrate GaN free-standing substrate after polishing the front and back surfaces of W 1 W 0 flatly

Claims (7)

異種基板の中心における、前記異種基板表面の法線に対して前記異種基板の基準となる結晶面の結晶軸が傾斜している角度αと、その傾斜方向に前記異種基板の中心から半径方向に20mmの位置における、前記異種基板表面の法線に対して前記結晶軸が傾斜している角度ηとの関係が、0.02°<|η−α|であり、且つ、前記異種基板面内の各点に
おいて前記異種基板表面の法線に対し前記結晶軸が前記異種基板の半径方向の外側に傾斜している異種基板を用い、
前記異種基板上にIII−V族窒化物系半導体結晶をヘテロエピタキシャル成長させるこ
とを特徴とするIII−V族窒化物系半導体基板の製造方法。
The angle α at which the crystal axis of the crystal plane serving as the reference of the heterogeneous substrate is inclined with respect to the normal line of the surface of the heterogeneous substrate at the center of the heterogeneous substrate, and the tilt direction in the radial direction The relationship with the angle η at which the crystal axis is inclined with respect to the normal of the surface of the different substrate at a position of 20 mm is 0.02 ° <| η−α | Using a heterogeneous substrate in which the crystal axis is inclined outward in the radial direction of the heterogeneous substrate with respect to the normal of the surface of the heterogeneous substrate at each point of
A method for producing a group III-V nitride semiconductor substrate comprising heteroepitaxially growing a group III-V nitride semiconductor crystal on the heterogeneous substrate.
前記III−V族窒化物系半導体結晶は、六方晶系であることを特徴とする請求項1に記
載のIII−V族窒化物系半導体基板の製造方法。
The method for producing a group III-V nitride semiconductor substrate according to claim 1, wherein the group III-V nitride semiconductor crystal is a hexagonal crystal.
前記III−V族窒化物系半導体結晶は、六方晶系であり、且つ前記III−V族窒化物系半導体基板の表面に最も近い低指数面がC面であることを特徴とする請求項1に記載のIII
−V族窒化物系半導体基板の製造方法。
2. The III-V nitride semiconductor crystal is hexagonal and the low index plane closest to the surface of the III-V nitride semiconductor substrate is a C-plane. Described in III
A method for manufacturing a group V nitride semiconductor substrate.
前記III−V族窒化物系半導体結晶は、六方晶系であり、且つ前記III−V族窒化物系半導体基板の表面に最も近い低指数面がC面のIII族面であることを特徴とする請求項1に
記載のIII−V族窒化物系半導体基板の製造方法。
The group III-V nitride semiconductor crystal is hexagonal, and the low index plane closest to the surface of the group III-V nitride semiconductor substrate is a C-plane group III surface. A method for producing a group III-V nitride semiconductor substrate according to claim 1.
前記III−V族窒化物系半導体結晶は、六方晶系であり、且つIII−V族窒化物系半導体基板の表面に最も近い低指数面がA面、M面又はR面のいずれかであることを特徴とする請求項1に記載のIII−V族窒化物系半導体基板の製造方法。   The group III-V nitride semiconductor crystal is hexagonal and the low index plane closest to the surface of the group III-V nitride semiconductor substrate is any one of the A plane, M plane, and R plane. The method for producing a group III-V nitride semiconductor substrate according to claim 1. 前記III−V族窒化物系半導体基板の表面は、鏡面研磨加工が施されていることを特徴
とする請求項1〜5のいずれかに記載のIII−V族窒化物系半導体基板の製造方法。
6. The method for producing a group III-V nitride semiconductor substrate according to claim 1, wherein the surface of the group III-V nitride semiconductor substrate is mirror-polished. .
請求項1〜6のいずれかに記載のIII−V族窒化物系半導体基板の製造方法を用いて、
前記異種基板上に前記III−V族窒化物系半導体結晶をヘテロエピタキシャル成長させた
後、前記異種基板を除去することにより前記III−V族窒化物系半導体基板を得ることを
特徴とするIII−V族窒化物系半導体基板の製造方法。
Using the method for producing a group III-V nitride semiconductor substrate according to any one of claims 1 to 6,
The group III-V nitride semiconductor substrate is obtained by heteroepitaxially growing the group III-V nitride semiconductor crystal on the heterogeneous substrate and then removing the heterogeneous substrate. A method for manufacturing a group nitride semiconductor substrate.
JP2008208022A 2008-08-12 2008-08-12 Method for manufacturing group III-V nitride semiconductor substrate Expired - Fee Related JP4998407B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008208022A JP4998407B2 (en) 2008-08-12 2008-08-12 Method for manufacturing group III-V nitride semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008208022A JP4998407B2 (en) 2008-08-12 2008-08-12 Method for manufacturing group III-V nitride semiconductor substrate

Publications (2)

Publication Number Publication Date
JP2010042958A true JP2010042958A (en) 2010-02-25
JP4998407B2 JP4998407B2 (en) 2012-08-15

Family

ID=42014672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008208022A Expired - Fee Related JP4998407B2 (en) 2008-08-12 2008-08-12 Method for manufacturing group III-V nitride semiconductor substrate

Country Status (1)

Country Link
JP (1) JP4998407B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013094171A1 (en) * 2011-12-22 2015-04-27 キヤノンアネルバ株式会社 Method for forming SrRuO3 film

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022212A (en) * 1998-06-30 2000-01-21 Sumitomo Electric Ind Ltd GaN SINGLE CRYSTAL SUBSTRATE AND ITS MANUFACTURE
JP2005161535A (en) * 2003-11-28 2005-06-23 Kyocera Mita Corp Multifunctional printer, printing method, and printing program
JP2005340747A (en) * 2003-11-04 2005-12-08 Hitachi Cable Ltd Iii-v group nitride series semiconductor substrate and manufacturing method of the same, iii-v group nitride series semiconductor device, iii-v group nitride series semiconductor substrate lot
JP2006151805A (en) * 2006-02-07 2006-06-15 Sumitomo Electric Ind Ltd GaN SINGLE CRYSTAL SUBSTRATE, METHOD FOR MANUFACTURING GaN SINGLE CRYSTAL SUBSTRATE, LIGHT EMITTING ELEMENT FORMED ON GaN SINGLE CRYSTAL SUBSTRATE, AND METHOD FOR MANUFACTURING THE SAME
JP2007161535A (en) * 2005-12-14 2007-06-28 Sumitomo Electric Ind Ltd Method for manufacturing semiconductor crystal substrate
JP2007161534A (en) * 2005-12-14 2007-06-28 Sumitomo Electric Ind Ltd Method for manufacturing nitride semiconductor crystal substrate
JP2007294518A (en) * 2006-04-21 2007-11-08 Hitachi Cable Ltd Nitride semiconductor substrate and its manufacturing method and epitaxial substrate for nitride semiconductor light-emitting device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022212A (en) * 1998-06-30 2000-01-21 Sumitomo Electric Ind Ltd GaN SINGLE CRYSTAL SUBSTRATE AND ITS MANUFACTURE
JP2005340747A (en) * 2003-11-04 2005-12-08 Hitachi Cable Ltd Iii-v group nitride series semiconductor substrate and manufacturing method of the same, iii-v group nitride series semiconductor device, iii-v group nitride series semiconductor substrate lot
JP2005161535A (en) * 2003-11-28 2005-06-23 Kyocera Mita Corp Multifunctional printer, printing method, and printing program
JP2007161535A (en) * 2005-12-14 2007-06-28 Sumitomo Electric Ind Ltd Method for manufacturing semiconductor crystal substrate
JP2007161534A (en) * 2005-12-14 2007-06-28 Sumitomo Electric Ind Ltd Method for manufacturing nitride semiconductor crystal substrate
JP2006151805A (en) * 2006-02-07 2006-06-15 Sumitomo Electric Ind Ltd GaN SINGLE CRYSTAL SUBSTRATE, METHOD FOR MANUFACTURING GaN SINGLE CRYSTAL SUBSTRATE, LIGHT EMITTING ELEMENT FORMED ON GaN SINGLE CRYSTAL SUBSTRATE, AND METHOD FOR MANUFACTURING THE SAME
JP2007294518A (en) * 2006-04-21 2007-11-08 Hitachi Cable Ltd Nitride semiconductor substrate and its manufacturing method and epitaxial substrate for nitride semiconductor light-emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013094171A1 (en) * 2011-12-22 2015-04-27 キヤノンアネルバ株式会社 Method for forming SrRuO3 film

Also Published As

Publication number Publication date
JP4998407B2 (en) 2012-08-15

Similar Documents

Publication Publication Date Title
JP4691911B2 (en) III-V nitride semiconductor free-standing substrate manufacturing method
JP6067801B2 (en) Finely graded gallium nitride substrate for high quality homoepitaxy
JP4581490B2 (en) III-V group nitride semiconductor free-standing substrate manufacturing method and III-V group nitride semiconductor manufacturing method
JP4696935B2 (en) III-V nitride semiconductor substrate and III-V nitride light emitting device
US7622791B2 (en) III-V group nitride system semiconductor substrate
JP4380294B2 (en) Group III-V nitride semiconductor substrate
KR20110088483A (en) Method of manufacturing single-crystal gan substrate, and single-crystal gan substrate
JP5051455B2 (en) Method of manufacturing nitride semiconductor substrate for epitaxial growth
JP2008044818A (en) Group iii-v nitride-based semiconductor substrate and group iii-v nitride-based light-emitting element
JP4333466B2 (en) Manufacturing method of semiconductor substrate and manufacturing method of free-standing substrate
JP6704387B2 (en) Substrate for growing nitride semiconductor, method of manufacturing the same, semiconductor device, and method of manufacturing the same
WO2020158571A1 (en) Nitride semiconductor substrate, laminated structure, and method for manufacturing nitride semiconductor substrate
JP4952616B2 (en) Manufacturing method of nitride semiconductor substrate
JP2005340747A (en) Iii-v group nitride series semiconductor substrate and manufacturing method of the same, iii-v group nitride series semiconductor device, iii-v group nitride series semiconductor substrate lot
JP5120285B2 (en) III-V nitride semiconductor free-standing substrate manufacturing method
JP4165030B2 (en) Method for manufacturing single substrate made of nitride semiconductor
TWI753134B (en) Group iii nitride semiconductor substrate
JP4998407B2 (en) Method for manufacturing group III-V nitride semiconductor substrate
JP2011037704A (en) Method for manufacturing group iii nitride crystal substrate
JP2006306722A (en) MANUFACTURING METHOD OF GaN SINGLE CRYSTAL SUBSTRATE, AND GaN SINGLE CRYSTAL SUBSTRATE
JP5488562B2 (en) Manufacturing method of nitride semiconductor substrate
JP2007063121A (en) METHOD FOR MANUFACTURING GaN SELF-STANDING SUBSTRATE, GaN SELF-STANDING SUBSTRATE, AND BLUE LED
JP6595677B1 (en) Nitride semiconductor substrate manufacturing method, nitride semiconductor substrate, and laminated structure
JP2011211046A (en) Nitride semiconductor self-supporting substrate
JP2010168277A (en) Semiconductor light emitting device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101015

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111011

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111018

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111125

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120417

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120430

R150 Certificate of patent or registration of utility model

Ref document number: 4998407

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150525

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees