JP2010041680A - Class-d amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a class-D amplifier which can actualize high-speed switching, with high accuracy and to attain low cost and size reduction of apparatus. <P>SOLUTION: In the class-D amplifier, there are provided timing adjusting circuits 32, 33 that have a pulse width of square waves supplied from a pulse transformer 26 to the gates of lower-side power transistors (Q14) 29, (Q15) 30 in a full bridge circuit narrower than pulse widths of square waves that are provided to gates of upper-side power transistors (Q12) 27, (Q13) 28 in the full-bridge circuit. The timing adjusting circuits 32, 33 are each activated, when there is an audio signal and is deactivated, when there is no audio signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a class D amplifying apparatus used for an amplitude modulation transmitter, and more particularly to a class D amplifying apparatus that realizes high-accuracy high-speed switching and can be downsized at low cost.

Conventionally, a class D amplifying apparatus is used in a transmitter using an amplitude modulation method based on digital modulation control.
[Amplitude modulation transmitter: Fig. 3]
A general amplitude modulation transmitter having a class D amplifier will be described with reference to FIG. FIG. 3 is a configuration diagram of a general amplitude modulation transmitter including a class D amplifier.
As shown in FIG. 3, a general amplitude modulation transmitter is used for digital broadcasting or the like, and includes an A / D converter 1, an encoder 2, a plurality of big step PAs (power amplifiers) 3, A plurality of binary steps PA 4, a carrier wave oscillator (OSC) 5, an FET driver IC 6, an output synthesis unit (synthesis transformer) 7, a band pass filter (BPF) 8, and a first power supply 9 are configured.

Each component will be described.
The A / D converter 1 converts an input modulation signal (sound) into a digital signal having a plurality of bits (for example, 12 bits).
The encoder 2 converts the signal into a signal for switching (on / off control) a big step PA3 and a binary step PA4 described later.

The big step PA (equal output power amplifier) 3 is composed of a FET (Field Effect Transistor) and is a high frequency amplifier that amplifies an input signal. As the big step PA3, there are N amplifiers PA1 to PAN (N = 26 in this case).
Binary step PA (binary power amplifier) 4 is an amplifier having the same structure as the big step PA3, as the binary step ^{PA4, 1 / 2PA~1 / 2 n} n pieces (n = 8 in this example) of PA There are amplifiers.
Each big step PA3 and each binary step PA4 are class D amplifiers that perform class D operation.

The carrier wave oscillator 5 is a high frequency oscillator that generates a carrier wave signal (rectangular wave) having a frequency f0.
The FET driver IC 6 is provided in one-to-one correspondence with each big step PA 3 and each binary step PA 4, and controls on / off of the corresponding big step PA 3 or binary step PA 4 based on the signal from the encoder 2. The big step PA3 or the binary step PA4 is operated in the class D by using the carrier wave signal from the carrier wave oscillator 5.

The output synthesizer 7 synthesizes and outputs output signals from the plurality of big steps PA3 and binary steps PA4.
A portion composed of a plurality of big steps PA3, binary steps PA4, and output synthesizer 7 is referred to as a class D amplifier.
The BPF 8 attenuates unnecessary high frequency components from the signal synthesized by the output synthesis unit 7.
The first power source 9 is a power source that supplies power to the class D amplifier.

The operation of a general amplitude modulation transmitter having the above configuration will be described.
In the transmitter, an audio signal which is a signal to be transmitted is converted into a 12-bit digital signal by the A / D converter 1, and a predetermined bit on the MSB (Most Significant Bit) side and an LSB (Least Significant) are converted by the encoder 2. Bit) side predetermined bits are extracted.

  The predetermined bits on the MSB side are respectively output to the FET driver ICs 6 corresponding to the 26 big step PA3, and the big step PA3 is controlled to be turned on / off by the FET driver IC6 and performs an amplification operation.

  Similarly, a predetermined bit on the LSB side is output to an FET driver IC 6 corresponding to eight binary steps PA4, and the binary step PA4 is ON / OFF controlled by the FET driver IC6 and is based on a fine information portion in the digital audio signal. Make corrections.

  The carrier wave (carrier) of the frequency f0 output from the carrier wave oscillator 5 is supplied to each big step PA3 and binary step PA4 via each FET driver IC6, and drives the big step PA3 and binary step PA4.

The outputs of each big step PA3 and binary step PA4 are output to the output combining unit 7 and combined, and unnecessary high frequency components are removed by the BPF 8 and output from the antenna. The output power is determined by the number of big steps PA3, the winding ratio of the synthesis transformer of the output synthesis unit 7, and the voltage of the first power supply 9.
In this way, the operation of a general amplitude modulation transmitter is performed.

[Conventional class D amplifier: Fig. 4]
Next, the configuration and operation of a conventional class D amplifier used for the big step PA3 and binary step PA4 of the amplitude modulation transmitter will be described with reference to FIG. FIG. 4 is a configuration diagram of a conventional class D amplifier.
As shown in FIG. 4, the conventional class D amplifier includes FET driver ICs 11a, 11b, 11c, and 11d, transistors (Q1) 12, (Q2) 13, (Q7) 19 to (Q9) 21, and a pulse transformer 14. And high power transistors (Q3) 15 to (Q6) 18, and the voltage of the first power supply 22 is applied to the high power transistors (Q3) 15 to (Q6) 18. The transistors (Q1) 12 to (Q9) 21 are all formed of FETs.
In FIG. 4, (A), (B), (C), and (D) in the figure are connected to the same reference numerals.

The FET driver IC 11a receives the carrier signal and drives the transistor (Q1) 12. Turns on when the carrier signal is high and turns off when the carrier signal is low.
Further, the FET driver IC 11c receives an audio signal and drives the transistor (Q7) 19. When an audio signal is input, the transistor (Q7) 19 is turned on to obtain an amplifier output.

Further, an inverting circuit is provided in front of the FET driver IC 11b, and the carrier wave signal is inverted and input to the FET driver IC 11b.
Further, an inverting circuit is provided in front of the FET driver IC 11d, and the audio signal is inverted and input to the FET driver IC 11d.

  The FET driver ICs 11a, 11b, 11c, and 11d are included in the FET driver IC 6 shown in FIG. 3. The FET driver IC 11a receives the carrier signal and drives the transistor (Q1) 12, and the FET driver IC 11b The transistor (Q2) 13 is driven in response to the input of the inverted signal of the carrier wave.

  The FET driver IC 11c receives the input of the audio signal and drives the transistor (Q7) 19, and the FET driver IC 11d receives the input of the inverted signal of the audio signal and drives the transistors (Q8) 20 and (Q9) 21. It is.

  The pulse transformer 14 amplifies a digital signal, and is composed of four secondary side parts 14a to 14d. The pulse transformers 14a and 14d output a rectangular wave when the transistor (Q1) 12 is turned on, Reference numerals 14b and 14c output rectangular waves when the transistor (Q2) 13 is turned on.

  The high power transistors (Q3) 15, (Q4) 16, (Q5) 17, and (Q6) 18 are composed of large FETs that can withstand the high voltage (about 180 to 200 V) of the first power supply 22, and switch the amplifier. I do.

  The transistor (Q7) 19 is an FET for controlling on / off of the amplifier output. Since the voltage of the first power supply 22 is not applied to the transistor (Q7) 19, the transistor (Q7) 19 is composed of a low power FET that operates at 0 to 10 V, and is small in size and capable of high-speed switching operation.

  Transistors (Q8) 20 and (Q9) 21 are low-power FFTs similar to those of the transistor (Q7) 19, and are turned on when the audio signal is turned off, and the GND on the secondary side of the pulse transformer is changed. By floating, charges accumulated during the on-state can be quickly dropped to GND, and the amplifier can be turned on / off at high speed.

When an audio signal is input, the transistor (Q7) 19 is turned on via the FFT driver IC 11c, and the gate of the high power transistor (Q3) 15 or (Q5) 17 is turned on to turn on the amplifier. .
As described with reference to FIG. 3, the hypertransistors (Q3) 15 and (Q5) 17 are repeatedly turned on / off at opposite timings. Is output.

The operation of the class D amplifier having the above configuration will be described.
A carrier wave f0 from the carrier wave oscillator 5 is inputted to the FET driver IC 11a, and a signal having an opposite phase to the carrier wave f0 is inputted to the FET driver IC 11b and outputted as gate signals of the transistors (Q1) 12 and (Q2) 13.

  The transistor (Q1) 12 and the transistor (Q2) 13 perform on / off operations alternately according to the input gate signal. As a result, by performing a push-pull operation around the primary side midpoint of the pulse transformer 14, the switching operation of the high power transistors (Q3) 15, (Q4) 16, (Q5) 17, and (Q6) 18 is performed. Then, the class D amplification operation is performed with the combination of ON / OFF, and the amplifier output is output to the serial addition combining unit (corresponding to “output combining unit 7” in FIG. 3).

  Specifically, a rectangular wave signal having the same phase as the carrier wave signal is output from the pulse transformers 14a and 14d in accordance with the on / off state of the transistor (Q1) 12, and the high power transistor (Q3) 15 and the high power transistor ( Q6) It is input to the gate of 18. That is, when the transistor (Q1) 12 is on, the high power transistors (Q3) 15 and (Q6) 18 are on.

  Similarly, a rectangular wave signal having a phase opposite to that of the carrier wave signal is output from the pulse transformers 14b and 14c according to ON / OFF of the transistor (Q2) 13, and the high-power transistors (Q5) 17 and (Q4) 16 Input to the gate. That is, when the transistor (Q2) 13 is on, the high power transistors (Q5) 17 and (Q4) 16 are on.

  That is, when the high power transistors (Q3) 15, (Q6) 18 are on, the high power transistors (Q5) 17, (Q4) 16 are off, and the high power transistors (Q3) 15, (Q6) 18 are off. When is turned off, the high power transistors (Q5) 17, (Q4) 16 are turned on.

  As the audio signal is turned on / off, the transistor (Q7) 19 is turned on when the audio signal is on, and the gates of the high power transistors (Q3) 15, and (Q5) 17 are connected to the GND side via diodes. And a rectangular wave signal is applied to the pulse transformers 14a and 14b, and a rectangular wave signal is also applied to the gates of the power transistors (Q4) 16 and (Q6) 18 for output (amplifier output). Is output to the serial addition synthesis unit.

The output when the hypertransistors (Q3) 15 and (Q6) 18 are turned on and the output when the power transistors (Q5) 17 and (Q4) 16 are turned on are alternately supplied to the serial addition synthesis unit. Is output.
When the audio signal is off, the transistors (Q8) 20 and (Q9) 21 are turned on, so that the remaining charge can be removed at high speed.

[Switching characteristics: Fig. 5]
Here, the switching characteristics of the class D amplifier will be described with reference to FIG. FIG. 5 is an explanatory diagram showing the switching characteristics of a conventional class D amplifier.
In the digital amplitude modulation type transmitter described above, a single wave is formed by a class D amplifier that combines a plurality of class D amplifiers. Therefore, in order to obtain a high-quality output signal, each class D amplifier is used. Uniformity and high-speed switching are important factors.

  For example, as shown in FIG. 5, when the rise and fall switching of the class D amplifier is slow, spikes (zags) and glitches (dents) are generated depending on the timing, resulting in deterioration of the S / N ratio and spurious. There is a risk of deterioration of characteristics such as deterioration.

  Therefore, in the class D amplifier shown in FIG. 4, in order to realize high-speed switching, the signal input to the secondary side gate of the pulse transformer 14 is dropped to GND by the transistor (Q7) 19, and the signal is separated. Further, by turning on / off the transistors (Q8) 20 and (Q9) 21, the GND on the secondary side of the pulse transformer 14 is forcibly floated, and the gate-source potential is made the same potential, thereby increasing the speed of extracting charges. The method is to create an off state.

In addition, as a prior art regarding an amplitude modulation transmitter, there is JP-A 2004-201123 “Amplitude modulation transmitter” (applicant: Hitachi Kokusai Electric Inc., inventor: Atsushi Hisamatsu) published on July 15, 2004. .
This prior art includes a first amplification unit that amplifies the amplitude of the amplified signal based on the first magnification signal, a second amplification unit that amplifies the amplitude of the amplified signal based on the second magnification signal, And an amplitude modulation transmitter comprising: a drive unit that drives an output signal of the second amplifying unit; and a combining unit that combines the outputs of the first and second amplifying units and outputs the resultant signal as an output signal. The distortion due to the rise / fall time difference at the time of switching is reduced.

JP 2004-201123 A

  However, in the class D amplifier constituting the conventional class D amplifier, the configuration shown in FIG. 4 is adopted in order to realize high-speed switching. However, in order to increase the speed of extracting charges, an FET transistor is added. Therefore, there is a problem that the configuration becomes slightly complicated.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a class D amplifying device that realizes high-precision high-speed switching, can be made inexpensive, and can be downsized.

  The present invention for solving the above-described problems of the conventional example includes a class D amplifier including a plurality of full-bridge amplifiers and a synthesizer that synthesizes outputs from the plurality of amplifiers in series. First transistor that is turned on / off according to the carrier signal of the carrier, an inverting circuit that generates a signal having an opposite phase to the carrier signal, and a second transistor that is turned on / off according to the signal having the opposite phase of the carrier signal generated by the inverting circuit A pulse transformer that performs a push-pull operation around the primary side midpoint by turning on and off the first and second transistors, and outputs a rectangular wave of the same phase or antiphase to the carrier signal from the secondary side, and a pulse A third and a fourth transistor which are turned on / off with a rectangular wave having the same phase to a carrier wave signal output from the secondary side of the transformer, and constitute a full-bridge type; 5th and 6th transistors constituting a full bridge type by turning on / off a carrier wave signal output from the secondary side of the pulse transformer with a rectangular wave having an opposite phase, and 3rd to 6th constituting a bridge type It is turned on / off depending on the power supply that applies voltage to the transistor and the presence / absence of an audio signal, the rectangular wave input to the gate of the fifth transistor is input, and the pulse width of the rectangular wave is adjusted to be adjusted. The first timing adjustment circuit that outputs the rectangular wave to the gate of the sixth transistor, and the on / off operation according to the presence or absence of the audio signal, the rectangular wave that is input to the gate of the third transistor is input, And a second timing adjustment circuit that performs adjustment to narrow the pulse width and outputs the adjusted rectangular wave to the gate of the fourth transistor.

  According to the present invention, in a class D amplification device including a plurality of full-bridge amplifiers and a combiner that serially combines outputs from the plurality of amplifiers, the first transistor in the amplifier is in accordance with a carrier signal from an oscillator. ON / OFF, the inverting circuit generates a signal having the opposite phase of the carrier signal, the second transistor is turned ON / OFF according to the signal having the opposite phase of the carrier signal generated by the inverting circuit, and the pulse transformer A third transistor that forms a full-bridge type by performing push-pull operation around the primary side midpoint by turning on / off the second transistor and outputting a rectangular wave of the same phase or opposite phase to the carrier signal from the secondary side And the fourth transistor is turned on / off by a rectangular wave having the same phase to the carrier wave signal output from the secondary side of the pulse transformer, and forms a full bridge type. The transistor and the sixth transistor are turned on / off with a rectangular wave having an opposite phase to the carrier signal output from the secondary side of the pulse transformer, and the power supply applies a voltage to the third to sixth transistors constituting the bridge type, The first timing adjustment circuit is turned on / off depending on the presence / absence of an audio signal, a rectangular wave input to the gate of the fifth transistor is input, adjustment is performed to narrow the pulse width of the rectangular wave, and the adjusted rectangular wave Is output to the gate of the sixth transistor, the second timing adjustment circuit is turned on / off depending on the presence or absence of an audio signal, the rectangular wave input to the gate of the third transistor is input, and the pulse width of the rectangular wave is The narrowing adjustment is performed, and the adjusted rectangular wave is output to the gate of the fourth transistor, realizing high-accuracy high-speed switching, and reducing the size of the device at low cost. There is an effect that can be bet.

Embodiments of the present invention will be described with reference to the drawings.
[Outline of the embodiment]
In the class D amplifying device according to the embodiment of the present invention, in the amplifier, a rectangular wave input from the pulse transformer to the gate of the lower transistor in the full bridge circuit is input to the gate of the upper transistor in the full bridge circuit. A timing adjustment circuit that makes the pulse width narrower than the rectangular wave is provided so that the timing adjustment circuit operates when there is an audio signal and stops when there is no audio signal. The corresponding lower transistors can be prevented from being simultaneously turned on and short-circuited, high-speed switching with high accuracy can be realized, and the device can be reduced in size at a low cost.

  The class D amplification device (this amplification device) according to the present embodiment is used in the general amplitude modulation transmitter shown in FIG. 3, and the configuration of the amplitude modulation transmitter itself is the same as that in FIG. . The class D amplifying apparatus according to the present embodiment includes 26 big step PAs and 8 binary step PAs as in the conventional apparatus shown in FIG. The configuration of the class D amplifier of the binary step PA4 is different from the conventional one.

[Class D amplifier: Fig. 1]
A configuration of a class D amplifier (the present amplifier) used as a big step PA or a binary step PA constituting the present amplification device will be described with reference to FIG. FIG. 1 is a configuration diagram of a class D amplifier constituting the class D amplifier according to the embodiment of the present invention.
As shown in FIG. 1, the basic configuration of the class D amplifier according to the present embodiment includes FET driver ICs 23a and 23b, transistors (Q10) 24 and (Q11) 25, a pulse transformer 26, a high power transistor ( Q12) 27 to (Q15) 30, a first timing adjustment circuit 32, and a second timing adjustment circuit 33. The high power transistors (Q12) 27 to (Q15) 30 have a voltage of the first power supply 31. Is applied. Transistors (Q10) 24 to (Q15) 30 are all formed of FETs.
Further, an inverting circuit (NOT circuit) is provided in the preceding stage of the FET driver IC 23b, and a carrier signal is inverted and a signal having an opposite phase is input to the FET driver IC 23b.

  In the claims, the first transistor is the transistor (Q10) 24, the second transistor is the transistor (Q11) 25, the third transistor is the high power transistor (Q12) 27, and the fourth transistor is the high transistor. The power transistor (Q15) 30, the fifth transistor corresponds to the high power transistor (Q13) 28, and the sixth transistor corresponds to the high power transistor (Q14) 29.

  The schematic device configuration includes transistors (Q10) 24 and (Q11) 25, FET driver ICs 23a and 23b for driving the transistors, and a pulse transformer for a full bridge type SEPP (Single Ended Push-Pull) class D amplifier. 26, high power transistors (Q12) 27 to (Q15) 30, and a first power supply 31.

  The FET driver ICs 23a and 23b are included in the FET driver IC 6 of FIG. 3. The FET driver IC 23a receives the carrier wave signal and drives the transistor (Q10) 24, and the FET driver IC 23b inverts the carrier wave signal. The transistor (Q11) 25 is driven in response to the input of the opposite phase signal.

  The pulse transformer 26 amplifies a digital signal, and is composed of two secondary side parts 26a and 26b. The pulse transformer 26a outputs a rectangular wave when the transistor (Q10) 24 is turned on, and the pulse transformer 26b Outputs a rectangular wave when the transistor (Q11) 25 is turned on.

  The high power transistors (Q12) 27, (Q13) 28, (Q14) 29, (Q15) 30 are composed of large FETs that can withstand the high voltage (about 180 to 200 V) of the first power supply 31, and switch the amplifier. I do.

  That is, the pulse transformer 24 is operated only in the upper part of the full bridge circuit composed of the transistors (Q12) 27 to (Q15) 30, and the lower part of the full bridge circuit is connected to the first timing adjustment circuit 32 and the second timing. It is driven by the adjustment circuit 33.

  The first timing adjustment circuit 32 branches from the terminal of the pulse transformer 26b from which a rectangular wave having an opposite phase is output to the gate of the power transistor (Q13) 28, and the rectangular wave is input from the input terminal to generate an audio signal. When a signal is input, an amplifier-on control signal (PA ON) is input, and when an audio signal is not input, an amplifier-off control signal (PA OFF) is input from the output control terminal, and a rectangular wave whose rectangular pulse width is adjusted is output. The power is output from the terminal to the power transistor (Q14) 29.

  The second timing adjustment circuit 33 branches from the terminal of the pulse transformer 26a where the in-phase rectangular wave is output to the gate of the power transistor (Q12) 27, the rectangular wave is input from the input terminal, and the audio signal An amplifier-on control signal (PA ON) is input at the time of input, and an amplifier-off control signal (PA OFF) is input from the output control terminal when no audio signal is input, and a rectangular wave with an adjusted pulse width of the rectangular wave is output terminal. To the power transistor (Q15) 30.

Here, for the power transistors (Q12) 27, (Q15) 30 and the power transistors (Q13) 28, (Q14) 29, the on / off timing is important. When the rectangular waves partially overlap, Since this portion is short-circuited, current flows by this amount, resulting in poor efficiency.
Thus, by providing the first and second timing adjustment circuits, the pulse width of the rectangular wave input to the gates of the power transistors (Q14) 29 and (Q15) 30 is adjusted so that the rectangular waves do not overlap.
Specific configurations of the first and second timing adjustment circuits 32 and 33 will be described later.

The two lines derived from the line connecting the high power transistor (Q12) 27 and the high power transistor (Q14) 29 and the line connecting the high power transistor (Q13) 28 and the high power transistor (Q15) 30. The line outputs an output signal through the transformer.
Note that serial addition synthesis is performed by the transformer.

[Timing adjustment circuit: Fig. 2]
Next, the configuration of the first and second timing adjustment circuits will be described with reference to FIG. FIG. 2 is a configuration diagram of the timing adjustment circuit.
As shown in FIG. 2, the timing adjustment circuit has a configuration in which a CR delay circuit including a capacitor C and a variable resistor R, a Schmitt trigger IC, and an FET driver IC are provided between an input terminal and an output terminal. It has become.

The delay circuit delays the rising edge of the rectangular wave input from the input terminal.
The Schmitt trigger IC is a flip-flop that has two threshold levels, an upper limit value and a lower limit value, with respect to an input voltage, and the state changes depending on whether the threshold voltage is higher or lower than these values. The Schmitt trigger IC has a role of forming an input waveform into a clean rectangular wave. In FIG. 2, two ICs corresponding to the upper limit value and the lower limit value are connected in series.

  The FET driver IC drives the power transistor (Q14) 29 or (Q15) 30, provides a rectangular wave to the gate of the power transistor, further includes an ENABLE terminal, and an audio signal ON (PA ON) at the output control terminal. When EN is input, the ENABLE terminal is turned on to enable operation, and when an audio signal OFF (PA OFF) is input, the ENABLE terminal is turned off and does not operate.

Then, the rectangular wave output from the output terminal is a rectangular wave with a narrow pulse width in which the rise of the pulse is delayed as compared with the rectangular wave input to the input terminal.
Thereby, the rectangular waves provided to the gates of the power transistors (Q12) 27 and (Q14) 29 do not overlap in a high (H) state, and a short circuit can be prevented. Further, the rectangular waves provided to the gates of the power transistors (Q13) 28 and (Q15) 30 do not overlap in a high (H) state, and a short circuit can be prevented.
The pulse width may not only delay the rise of the pulse, but also make the pulse fall earlier and narrow it.

[Operation]
The carrier signal input from the oscillator (OSC) is input to the FET driver IC 23a, and the carrier signal is input to the FET driver IC 23b through an inverting circuit.
The output from the FET driver IC 23a and the output from the FET driver IC 23b are input to the gates of the transistor (Q10) 24 and the transistor (Q11) 25 as gate input signals having opposite phases.

  The transistor (Q10) 24 and the transistor (Q11) 25 alternately perform on and off operations in accordance with gate input signals that are sequentially input. As a result, a push-pull operation is performed around the center of the primary side of the pulse transformer 26.

A rectangular wave amplified from the secondary side 26 a of the pulse transformer 26 is input to the gate of the power transistor (Q 12) 27 and the input terminal of the second timing adjustment circuit 33.
The second timing adjustment circuit 33 receives an amplifier on / off (PA ON / OFF) signal, and enters an operation state when the amplifier is on (when an audio signal is input), and outputs a rectangular wave whose pulse width is adjusted. .

  When no audio signal is input, the amplifier on / off signal is turned off and the first and second timing adjustment circuits 32 and 33 and the power transistors (Q14) 29 and (Q15) 30 are stopped to save power. I am trying.

An anti-phase rectangular wave amplified from the secondary side 26 b of the pulse transformer 26 is input to the gate of the power transistor (Q 13) 28 and the input terminal of the first timing adjustment circuit 32.
The first timing adjustment circuit 32 inputs an amplifier on / off (PA ON / OFF) signal, and enters an operating state when the amplifier is on (when an audio signal is input), and outputs a rectangular wave whose pulse width is adjusted. .

  A combination of ON / OFF operations by switching power transistors (Q12) 27 to (Q15) 30 on the secondary side of the transformer by repeating ON / OFF operations in the transistor (Q10) 24 and the transistor (Q11) 25. To perform class D amplification.

  The combination of the on / off operation is such that the power transistors (Q12) 27 and (Q15) 30 perform substantially the same operation, and the power transistors (Q13) 28 and (Q14) 29 perform substantially the same operation.

  Specifically, a rectangular wave whose pulse width is adjusted by the timing adjustment circuits 32 and 33 is input to the power transistors (Q14) 29 and (Q15) 30. The rectangular wave has a narrow pulse width that does not overlap with the rectangular waves input to the power transistors (Q12) 27 and (Q13) 28 at a high level.

  As a result, the power transistors (Q12) 27 and (Q14) 29 can be prevented from being simultaneously turned on and short-circuited, and the power transistors (Q13) 28 and (Q15) 30 can be prevented from being simultaneously turned on and short-circuited. .

  If the power transistors (Q12) 27 and (Q15) 30 are on, the power transistors (Q13) 28 and (Q14) 29 are off, and the power transistors (Q12) 27 and (Q15) 30 are off. In this case, the power transistors (Q13) 28 and (Q14) 29 are on.

  In addition, the power amplifier (PA) output on / off (PA ON / OFF), that is, the control to turn on while the audio signal is input and to turn off when the audio signal is not input is The operation of the first and second timing adjustment circuits 32 and 33 is stopped, and the input signals to the power transistors (Q14) 29 and (Q15) 30 below the full bridge are supplied from the first and second timing adjustment circuits 32 and 33. Do not to do so.

[Effect of the embodiment]
According to the class D amplifier according to the embodiment of the present invention, the transistors (Q10) 24 and (Q11) 25 that repeat ON / OFF in opposite phases based on the carrier wave signal, and the intermediate on the primary side by the ON / OFF thereof. A pulse transformer 26 that performs a push-pull operation around a point, and a power transistor (Q12) that turns on / off with a rectangular wave of the same phase to a carrier signal output from the secondary side of the pulse transformer 26 to form a full bridge type 27, (Q15) 30, and power transistors (Q13) 28, (Q14) 29 that form a full-bridge type by turning on / off the carrier wave signal output from the secondary side of the pulse transformer with a rectangular wave having an opposite phase. It is turned on / off depending on the presence or absence of an audio signal, and adjustment is performed to narrow the pulse width of the rectangular wave input to the gate of the power transistor (Q13) 28. The first timing adjustment circuit 32 that outputs to the gate of the word transistor (Q14) 29 and the ON / OFF state depending on the presence / absence of an audio signal, thereby narrowing the pulse width of the rectangular wave input to the gate of the power transistor (Q12) 27 Since the second timing adjustment circuit 33 that adjusts and outputs to the gate of the power transistor (Q15) 30 is provided, it is possible to realize high-speed switching with high accuracy and to reduce the size of the device at low cost. There is an effect that can be done.

  The present invention is suitable for a class D amplifying device that realizes high-speed switching with high accuracy, can be made inexpensive, and can be downsized.

It is a block diagram of the class D amplifier which comprises the class D amplifier which concerns on embodiment of this invention. It is a block diagram of a timing adjustment circuit. It is a block diagram of the general amplitude modulation transmitter provided with the class D amplifier. It is a block diagram of the conventional class D amplifier. It is explanatory drawing which shows the switching characteristic of the conventional class D amplifier.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... A / D converter, 2 ... Encoder, 3 ... Big step PA, 4 ... Binary step PA, 5 ... Carrier wave oscillator, 6 ... FET driver IC, 7 ... Output composition part, 8 ... Band pass filter, 9 ... First 1 power supply, 11 ... FET driver IC, 12 ... transistor, 14 ... pulse transformer, 15-18 ... power transistor, 19-21 ... transistor, 22 ... first power supply, 23 ... FET driver IC, 24 ... transistor, 26 ... pulse Transformers 27-30 Power transistors 31 First power supply

Claims (1)

In a class D amplification device comprising a plurality of full-bridge amplifiers and a synthesizer that synthesizes outputs from the plurality of amplifiers in series,
The amplifier is
A first transistor that turns on and off in accordance with a carrier signal from an oscillator;
An inverting circuit for generating a signal having a phase opposite to that of the carrier wave signal;
A second transistor that is turned on / off in accordance with a signal having an opposite phase to the carrier signal generated by the inverting circuit;
A pulse transformer that performs a push-pull operation around the primary side by turning on and off the first and second transistors, and outputs a rectangular wave of the same phase or opposite phase to the carrier signal from the secondary side;
A third transistor and a fourth transistor which are turned on / off with a rectangular wave having the same phase to the carrier wave signal output from the secondary side of the pulse transformer, and constitute a full bridge type;
A fifth transistor and a sixth transistor which are turned on / off with a rectangular wave having an opposite phase to the carrier wave signal output from the secondary side of the pulse transformer, and constitute a full-bridge type;
A power source for applying a voltage to the third to sixth transistors constituting a bridge type;
It is turned on / off depending on the presence / absence of an audio signal, a rectangular wave input to the gate of the fifth transistor is input, adjustment is performed to narrow the pulse width of the rectangular wave, and the adjusted rectangular wave is converted to the sixth wave. A first timing adjustment circuit for outputting to the gate of the transistor;
It is turned on / off depending on the presence / absence of an audio signal, a rectangular wave input to the gate of the third transistor is input, adjustment is performed to narrow the pulse width of the rectangular wave, and the adjusted rectangular wave is converted to the fourth wave And a second timing adjusting circuit for outputting to the gate of the transistor.

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