JP2010021716A - Class d amplifier device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a class D amplifier device which achieves quick and uniform switching and can be made compact. <P>SOLUTION: The class D amplifier device includes: a pulse transformer 24 which performs push-pull operation with a middle point on the primary side as the center by turning-on/off transistors Q10 and Q11; power transistors Q12 and Q13 which perform switching by the pulse transformer; a timing adjustment means 30 which adjusts output timing of a carrier signal for the portion of the time of the push-pull operation; an inverting circuit 35 and an AND circuit 37 which generate the anti-phase signal of the carrier signal from the timing adjustment means 30 in the case of input of a sound signal; a transistor Q14 which is turned on/off by a rectangular wave having a phase opposite to the carrier signal from the timing adjustment means 30, which is output from the AND circuit 37; and a transistor Q15 which is turned on/off by a rectangular wave having the same phase as the carrier signal from the timing adjustment means 30. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a class D amplifying apparatus used for an amplitude modulation transmitter, and more particularly to a class D amplifying apparatus capable of realizing high-speed and uniform switching and miniaturizing the apparatus.

Conventionally, a class D amplifying apparatus is used in a transmitter using an amplitude modulation method based on digital modulation control.
[Amplitude modulation transmitter: Fig. 2]
A general amplitude modulation transmitter including a class D amplifier will be described with reference to FIG. FIG. 2 is a configuration diagram of a general amplitude modulation transmitter including a class D amplifier.
As shown in FIG. 2, a general amplitude modulation transmitter is used for digital broadcasting or the like, and includes an A / D converter 1, an encoder 2, a plurality of big step PAs (power amplifiers) 3, A plurality of binary steps PA 4, a carrier wave oscillator (OSC) 5, an FET driver IC 6, an output synthesis unit (synthesis transformer) 7, a band pass filter (BPF) 8, and a first power supply 9 are configured.

Each component will be described.
The A / D converter 1 converts an input modulation signal (sound) into a digital signal having a plurality of bits (for example, 12 bits).
The encoder 2 converts the signal into a signal for switching (on / off control) a big step PA3 and a binary step PA4 described later.

The big step PA (equal output power amplifier) 3 is composed of a FET (Field Effect Transistor) and is a high frequency amplifier that amplifies an input signal. As the big step PA3, there are N amplifiers PA1 to PAN (N = 26 in this case).
Binary step PA (binary power amplifier) 4 is an amplifier having the same structure as the big step PA3, as the binary step ^{PA4, 1 / 2PA~1 / 2 n} n pieces (n = 8 in this example) of PA There are amplifiers.
Each big step PA3 and each binary step PA4 are class D amplifiers that perform class D operation.

The carrier wave oscillator 5 is a high frequency oscillator that generates a carrier wave signal (rectangular wave) having a frequency f0.
The FET driver IC 6 is provided in one-to-one correspondence with each big step PA 3 and each binary step PA 4, and controls on / off of the corresponding big step PA 3 or binary step PA 4 based on the signal from the encoder 2. The big step PA3 or the binary step PA4 is operated in the class D by using the carrier wave signal from the carrier wave oscillator 5.

The output synthesizer 7 synthesizes and outputs output signals from the plurality of big steps PA3 and binary steps PA4.
A portion composed of a plurality of big steps PA3, binary steps PA4, and output synthesizer 7 is referred to as a class D amplifier.
The BPF 8 attenuates unnecessary high frequency components from the signal synthesized by the output synthesis unit 7.
The first power source 9 is a power source that supplies power to the class D amplifier.

The operation of a general amplitude modulation transmitter having the above configuration will be described.
In the transmitter, an audio signal which is a signal to be transmitted is converted into a 12-bit digital signal by the A / D converter 1, and a predetermined bit on the MSB (Most Significant Bit) side and an LSB (Least Significant) are converted by the encoder 2. Bit) side predetermined bits are extracted.

  The predetermined bits on the MSB side are respectively output to the FET driver ICs 6 corresponding to the 26 big step PA3, and the big step PA3 is controlled to be turned on / off by the FET driver IC6 and performs an amplification operation.

  Similarly, a predetermined bit on the LSB side is output to an FET driver IC 6 corresponding to eight binary steps PA4, and the binary step PA4 is ON / OFF controlled by the FET driver IC6 and is based on a fine information portion in the digital audio signal. Make corrections.

  The carrier wave (carrier) of the frequency f0 output from the carrier wave oscillator 5 is supplied to each big step PA3 and binary step PA4 via each FET driver IC6, and drives the big step PA3 and binary step PA4.

The outputs of each big step PA3 and binary step PA4 are output to the output combining unit 7 and combined, and unnecessary high frequency components are removed by the BPF 8 and output from the antenna. The output power is determined by the number of big steps PA3, the winding ratio of the synthesis transformer of the output synthesis unit 7, and the voltage of the first power supply 9.
In this way, the operation of a general amplitude modulation transmitter is performed.

[Conventional class D amplifier: Fig. 3]
Next, the configuration and operation of a conventional class D amplifier used for the big step PA3 and binary step PA4 of the amplitude modulation transmitter will be described with reference to FIG. FIG. 3 is a configuration diagram of a conventional class D amplifier.
As shown in FIG. 3, the conventional class D amplifier includes FET driver ICs 11a, 11b, and 11c, transistors Q1 and Q2, a pulse transformer 14, and high power transistors Q3 to Q7. The voltage of the first power supply 20 is applied to Q7. The transistors Q1 to Q7 are all formed of FETs.
Further, an inverting circuit is provided in front of the FET driver IC 11b, and the carrier wave signal is inverted and input to the FET driver IC 11b.

  The FET driver ICs 11a, 11b, and 11c are included in the FET driver IC 6 of FIG. 2. The FET driver IC 11a receives the carrier wave signal to drive the transistor Q1, and the FET driver IC 11b receives the inverted signal of the carrier wave. The transistor Q2 is driven in response to the input.

  Further, the FET driver IC 11c drives the transistor Q7 upon receiving an audio signal. When an audio signal is input, the transistor Q7 is turned on to obtain an amplifier output.

The pulse transformer 14 amplifies a digital signal, and is composed of four secondary side portions 14a to 14d. The pulse transformers 14a and 14d output a rectangular wave when the transistor Q1 is turned on, and 14b and 14c. Is to output a rectangular wave when the transistor Q2 is turned on.
The high power transistors Q3, Q4, Q5, and Q6 are composed of large FETs that can withstand the high voltage (about 180 to 200 V) of the first power supply 20, and perform switching of the amplifier.
The transistor Q7 enables high-speed switching operation in the above switching.

The operation of the class D amplifier having the above configuration will be described.
A carrier wave f0 from the carrier wave oscillator 5 is inputted to the FET driver IC 11a, and a signal having a phase opposite to that of the carrier wave f0 is inputted to the FET driver IC 11b and outputted as gate signals of the transistors Q1 and Q2. The transistors Q1 and Q2 alternately perform on / off operations according to the input gate signal. Thereby, the switching operation of the high power transistors Q3, Q4, Q5, and Q6 is performed, the class D amplification operation is performed by the combination of ON / OFF, and the amplifier output is connected to the series addition combining unit (“output combining unit 7” in FIG. Output).

  Specifically, a rectangular wave signal having the same phase as the carrier wave signal is output from the pulse transformers 14a and 14d and input to the gates of the high power transistor Q3 and the high power transistor Q6. That is, when the transistor Q1 is on, the high power transistors Q3 and Q6 are on.

  Similarly, a rectangular wave signal having a phase opposite to that of the carrier wave signal is output from the pulse transformers 14b and 14c and input to the gates of the high power transistors Q5 and Q4. That is, when the transistor Q2 is on, the high power transistors Q5 and Q4 are on.

  When the audio signal is turned on, the transistor Q7 is turned on, and the amplifier output is output to the serial addition / synthesis unit.

[Switching characteristics: Fig. 4]
Here, the switching characteristics of the class D amplifier will be described with reference to FIG. FIG. 4 is an explanatory diagram showing the switching characteristics of a conventional class D amplifier.
In the digital amplitude modulation type transmitter described above, a single wave is formed by a class D amplifier that combines a plurality of class D amplifiers. Therefore, in order to obtain a high-quality output signal, each class D amplifier is used. Uniformity and high-speed switching are important factors.

  For example, as shown in FIG. 4, when the rise and fall switching of the class D amplifier is slow, spikes (zag) and glitches (dents) occur due to timing, resulting in deterioration of S / N ratio and spurious. There is a risk of deterioration of characteristics such as deterioration.

  Therefore, in the class D amplifier shown in FIG. 3, in order to realize high-speed switching, a transistor Q7 is provided on the source side of the high power transistors Q5 and Q6, GND is forcibly floated, and the gate-source has the same potential. This is a method for creating an off-state.

In addition, as a prior art regarding an amplitude modulation transmitter, there is JP-A 2004-201123 “Amplitude modulation transmitter” (applicant: Hitachi Kokusai Electric Inc., inventor: Atsushi Hisamatsu) published on July 15, 2004. .
This prior art includes a first amplification unit that amplifies the amplitude of the amplified signal based on the first magnification signal, a second amplification unit that amplifies the amplitude of the amplified signal based on the second magnification signal, And an amplitude modulation transmitter comprising: a drive unit that drives an output signal of the second amplifying unit; and a combining unit that combines the outputs of the first and second amplifying units and outputs the resultant signal as an output signal. The distortion due to the rise / fall time difference at the time of switching is reduced.

JP 2004-201123 A

  However, in the class D amplifier constituting the conventional class D amplifier, the transistor Q7 is provided on the source side of the transistors Q5 and Q6 in FIG. 3 in order to realize high-speed switching. Since it is applied, it is necessary to configure a large high-power transistor having a breakdown voltage equivalent to that of the high-power transistors Q3 to Q6, and further, it must be provided for each big step PA3 and binary step PA4. In addition, there is a problem that the heat radiation from Q7 may adversely affect the characteristics of the output signal.

  Furthermore, there is a problem that the larger the FET is, the larger the on-resistance and input capacitance of the FET are, and due to these variations, the delicate timing of switching tends to occur, and the higher the frequency, the more prominent.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a class D amplification device that realizes high-speed switching with high accuracy and can reduce the size of the device.

  The present invention for solving the above-described problems of the conventional example includes a class D amplifier including a plurality of full-bridge amplifiers and a synthesizer that synthesizes outputs from the plurality of amplifiers in series. First transistor that is turned on / off according to the carrier signal of the carrier, an inverting circuit that generates a signal having an opposite phase to the carrier signal, and a second transistor that is turned on / off according to the signal having the opposite phase of the carrier signal generated by the inverting circuit A pulse transformer that performs a push-pull operation around the primary side midpoint by turning on and off the first and second transistors, and outputs a rectangular wave of the same phase or antiphase to the carrier signal from the secondary side, and a pulse A third transistor that forms a full bridge by turning on / off the carrier wave signal output from the secondary side of the transformer with a rectangular wave having the same phase, and the secondary of the pulse transformer The output signal is adjusted by the time of the push-pull operation in the pulse transformer for the carrier signal from the oscillator, which is turned on / off with a square wave of opposite phase to the carrier signal output from A timing adjustment unit, a logic circuit that generates a signal having an opposite phase to the carrier signal from the timing adjustment unit when an audio signal is input, and a carrier signal from the timing adjustment unit that is generated by the logic circuit. It is characterized by having a fifth transistor that is turned on / off by a rectangular wave having an antiphase and a sixth transistor that is turned on / off by a rectangular wave having the same phase as the carrier wave signal from the timing adjusting means.

  According to the present invention, in a class D amplification device including a plurality of full-bridge amplifiers and a combiner that serially combines outputs from the plurality of amplifiers, the first transistor in the amplifier is in accordance with a carrier signal from an oscillator. ON / OFF, the inverting circuit generates a signal having the opposite phase of the carrier signal, the second transistor is turned ON / OFF according to the signal having the opposite phase of the carrier signal generated by the inverting circuit, and the pulse transformer is connected to the first and first pulse transformers. Push-pull operation is performed around the primary side midpoint by turning on and off the second transistor, a rectangular wave with the same phase or opposite phase is output from the secondary side to the carrier wave signal, and the third transistor is the secondary of the pulse transformer The carrier wave signal output from the side is turned on / off with a rectangular wave of the same phase to form a full bridge type, and the fourth transistor is output from the secondary side of the pulse transformer. The carrier wave signal is turned on / off with an antiphase rectangular wave to form a full bridge type, and the timing adjustment means adjusts the output timing of the carrier wave signal from the oscillator by the time of the push-pull operation in the pulse transformer, and the logic circuit When the audio signal is input, an antiphase signal is generated for the carrier signal from the timing adjustment means, and the fifth transistor is generated by the logic circuit. It is turned on / off by a rectangular wave, and the sixth transistor is turned on / off by a rectangular wave having the same phase as the carrier wave signal from the timing adjustment means, realizing high-precision high-speed switching and miniaturizing the device. There is an effect that can.

Embodiments of the present invention will be described with reference to the drawings.
[Outline of the embodiment]
In the class D amplifier according to the embodiment of the present invention, the amplifier uses only the upper pulse transistor of the full bridge circuit and the lower transistor is directly driven by a general-purpose FET driver IC. Thus, switching characteristics equivalent to or higher than those of the conventional method can be realized, and safety can be obtained at low cost.

  In particular, in the class D amplification device according to the embodiment of the present invention, the timing adjustment means adjusts the switching timing corresponding to the upper and lower transistors of the full bridge circuit. The amplifier is controlled to be turned off when no audio signal is input.

  The class D amplification device (the present amplification device) according to the present embodiment is used for the general amplitude modulation transmitter shown in FIG. 2, and the configuration of the amplitude modulation transmitter itself is the same as FIG. . The class D amplifying device according to the present embodiment includes 26 big step PAs and 8 binary step PAs as in the conventional device shown in FIG. The configuration of the class D amplifier of the binary step PA4 is different from the conventional one.

[Class D amplifier: Fig. 1]
A configuration of a class D amplifier (the present amplifier) used as a big step PA or a binary step PA constituting the present amplification device will be described with reference to FIG. FIG. 1 is a configuration diagram of a class D amplifier constituting the class D amplifier according to the embodiment of the present invention.
As shown in FIG. 1, the basic configuration of the class D amplifier according to the present embodiment includes FET driver ICs 21a, 21b, 21c, 21d, transistors Q10 (22), Q11 (23), a pulse transformer 24, The high power transistors Q12 (25) to Q15 (28) are configured, and the voltage of the first power supply 29 is applied to the high power transistors Q12 to Q15. Transistors Q10 to Q15 are all formed of FETs.
Further, an inverting circuit (NOT circuit) is provided in front of the FET driver IC 21b, and a carrier signal is inverted and a signal having an opposite phase is input to the FET driver IC 21b.

  The schematic device configuration includes transistors Q10 and Q11, FET driver ICs 21a and 21b for driving the transistors Q, a pulse transformer 24 for a full-bridge type SEPP (Single Ended Push-Pull) class D amplifier, and a high power transistor. Q12 to Q15 and a first power supply 29.

  The FET driver ICs 21a, 21b, 21c, and 21d are included in the FET driver IC 6 in FIG. 2. The FET driver IC 21a receives the carrier signal and drives the transistor Q10. The FET driver IC 21b receives the carrier signal. The transistor Q2 is driven in response to the input of the inverted phase signal.

In addition, a timing adjustment unit 30 is provided in front of the FFT driver ICs 21c and 21d.
The timing adjustment unit 30 includes a resistor 31, a capacitor 32, and inverting circuits 33 and 34.

The resistor 31 is a variable resistor connected in series with the carrier wave input before the inverting circuit 33.
The capacitor 32 has one end connected between the resistor 31 and the input stage of the inverting circuit 33 and the other end grounded.
The carrier wave signal input by the resistor 31 and the capacitor 32 is delayed to adjust the timing.

  The inverting circuits 33 and 34 perform an operation of inverting the input carrier wave signal. Since the inverter circuit has two stages, the signal input to the inverter circuit 33 has the same phase when output from the inverter circuit 34.

The output from the inverting circuit 34 is branched, and one of the outputs is input to a logical sum (OR) circuit 36, and the output is input to the FET driver IC 21c.
The other output from the inverting circuit 34 is input to one input terminal of a logical product (AND) circuit 37 via the inverting circuit 35, and the output is input to the FET driver IC 21d.

  An amplifier ON / OFF (PA ON / OFF) signal is input to the other input terminal of the AND circuit 37. The amplifier on / off signal is turned on when an audio signal is inputted, and turned off when no audio signal is inputted.

Since the OR circuit 36 is a one-input OR circuit, it outputs a signal having the same phase as the input signal to the FET driver IC 21c.
The AND circuit 37 receives the signal from the inverting circuit 35 and the amplifier on / off signal, and outputs a signal having the same phase to the input signal from the inverting circuit 35 to the FET driver IC 21d when the amplifier is on.
Therefore, the output signal from the AND circuit 37 is an antiphase signal with respect to the output signal from the OR circuit 36.

  The output of the FET driver IC 21c is input to the gate of the transistor Q15, and the output of the FET driver IC 21d is input to the gate of the transistor Q14.

  The pulse transformer 24 amplifies the digital signal, and is composed of two secondary side parts 24a and 24b. The pulse transformer 24a outputs a rectangular wave when the transistor Q10 is turned on, and the pulse transformer 24b outputs the transistor Q11. A square wave is output when is turned on.

  The high power transistors Q12, Q13, Q14, and Q15 are configured by large FETs that can withstand the high voltage (about 180 to 200 V) of the first power supply 29, and perform switching of the amplifier.

  That is, the pulse transformer 24 is operated only in the upper part of the full bridge circuit composed of the transistors Q12 to Q15, and the lower part of the full bridge circuit is directly driven by the general-purpose FET drivers IC21c and C22.

Then, two lines derived from the line connecting the transistor Q12 and the transistor Q14 and the line connecting the transistor Q13 and the transistor Q15 output an output signal via the transformer.
Note that serial addition synthesis is performed by the transformer.

[Operation]
The carrier wave signal input from the oscillator (OSC) is input to the FET driver IC 21a, and the carrier wave signal is input to the FET driver IC 21b via an inverting circuit.
The output from the FET driver IC 21a and the output from the FET driver IC 21b are input to the gates of the transistors Q10 and Q11 as gate input signals having opposite phases.

  Transistors Q10 and Q11 alternately perform on and off operations in accordance with sequentially input gate input signals. As a result, a push-pull operation is performed around the center of the primary side of the pulse transformer 24.

  The carrier wave signal is adjusted in timing by the timing adjusting means 30 and inputted to the OR circuit 36 and the inverting circuit 35. The OR circuit 36 outputs the inputted carrier wave signal to the FET driver IC 21c as it is, and the inverting circuit 35 A signal having a phase opposite to that of the carrier wave signal is output to the AND circuit 37.

  The AND circuit 37 receives a signal from the inverting circuit 35 (a signal having a phase opposite to that of the carrier wave signal) and an amplifier on / off signal. While the amplifier on signal is input (while an audio signal is input). A signal having a phase opposite to that of the carrier wave signal is output to the FET driver IC 21d.

  The output from the FET driver IC 21c and the output from the FET driver IC 21d are input to the gates of the transistors Q15 and Q14 as gate input signals having opposite phases.

  Here, the functions of the timing adjustment unit 30 and the OR circuit 36 are to adjust the output of the rectangular wave signal having the same phase as the rectangular wave input from the pulse transformer 24a to the gate of the transistor Q12 to the FET driver IC 21c.

  The function of the timing adjustment means 30, the inverting circuit 35, and the AND circuit 37 is that the rectangular wave signal having the same phase as the rectangular wave input from the pulse transformer 24b to the gate of the transistor Q13 (the rectangular wave input to the gate of the transistor Q12). (Rectangular wave signal having an opposite phase to that of the FET driver IC 21d).

  By repeating the on / off operations in the transistors Q10 and Q11, switching is performed in the transistors Q12 to Q15 on the secondary side of the transformer, and a class D amplification operation is performed by a combination of the on / off operations.

The combination of the on / off operation is such that the transistors Q12 and Q15 perform the same operation, and the transistors Q13 and Q14 perform the same operation.
If the transistors Q12 and Q15 are on, the transistors Q13 and Q14 are off. If the transistors Q12 and Q15 are off, the transistors Q13 and Q14 are on.

  The power amplifier (PA) output is turned on / off, that is, turned on while an audio signal is input, and turned off while an audio signal is not input. The transistors Q14 and Q15 below the full bridge are controlled. This is done by stopping the input signal.

  Specifically, under the control of the AND circuit 37 to which the amplifier on / off signal is input, the operation of the full bridge is stopped because the transistor Q14 does not operate while the amplifier off signal is input.

  Originally, the class D amplifier is theoretically performed by a combination of on / off of full-bridge transistors, so that a pulse transformer is not necessary. Ideally, all transistors are directly driven by an FET driver IC.

  Although it is effective to prevent the pulse transformer by separating the driver portion from a lightning surge or the like that has entered from the power supply, it is harmful from the viewpoint of high-speed switching.

  Regarding the current ground side, as can be seen by referring to a conventional circuit, it has been confirmed that the on / off transistors (transistors Q14 and Q15) are operating without being separated by a transformer.

  Also, the timing shift between the side where the transformer is inserted and the side where the transformer is not included is performed by the timing adjustment means 30 such as a simple timing adjustment circuit using the resistor R and the capacitor C.

[Effect of the embodiment]
According to the class D amplifier according to the embodiment of the present invention, the transistors Q10 and Q11 that repeat ON / OFF in opposite phases based on the carrier wave signal, and the push-pull centering on the primary side midpoint by the ON / OFF. The pulse transformer 24 that performs the operation, the power transistors Q12 and Q13 that perform switching thereby, the timing adjustment unit 30 that adjusts the output timing of the carrier wave signal by the time of the push-pull operation in the pulse transformer 24, and the audio signal are input. In the case where the carrier wave signal from the timing adjustment unit 30 is generated, the inverting circuit 35 and the AND circuit 37 generate a signal having an opposite phase with respect to the carrier wave signal from the timing adjustment unit 30. Transistor Q14 that turns on / off with rectangular wave, and timing adjustment Since a structure in which a transistor Q15 for turning on / off the carrier signal by the rectangular wave of the same phase from stage 30, provides fast and uniform switching, there is an effect that it is possible to reduce the size of the apparatus.

  The present invention is particularly suitable for a class D amplifying device that realizes high-speed and uniform switching and can reduce the size of the device.

It is a block diagram of the class D amplifier which comprises the class D amplifier which concerns on embodiment of this invention. It is a block diagram of the general amplitude modulation transmitter provided with the class D amplifier. It is a block diagram of the conventional class D amplifier. It is explanatory drawing which shows the switching characteristic of the conventional class D amplifier.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... A / D converter, 2 ... Encoder, 3 ... Big step PA, 4 ... Binary step PA, 5 ... Carrier wave oscillator, 6 ... FET driver IC, 7 ... Output composition part, 8 ... Band pass filter, 9 ... First 1 power supply, 11 ... FET driver IC, 14 ... pulse transformer, 20 ... first power supply, 21 ... FET driver IC, 24 ... pulse transformer, 29 ... first power supply

Claims (1)

In a class D amplification device comprising a plurality of full-bridge amplifiers and a synthesizer that synthesizes outputs from the plurality of amplifiers in series,
A first transistor that turns on / off in accordance with a carrier signal from an oscillator;
An inverting circuit for generating a signal having a phase opposite to that of the carrier wave signal;
A second transistor that is turned on / off in accordance with a signal having an opposite phase to the carrier signal generated by the inverting circuit;
A pulse transformer that performs a push-pull operation around the primary side midpoint by turning on and off the first and second transistors, and outputs a rectangular wave of the same phase or antiphase to the carrier signal from the secondary side;
A third transistor that forms a full-bridge type by turning on / off a rectangular wave of the same phase to the carrier wave signal output from the secondary side of the pulse transformer;
A fourth transistor that forms a full-bridge type by turning on / off the carrier wave signal output from the secondary side of the pulse transformer with a rectangular wave of opposite phase;
Timing adjustment means for adjusting the output timing of the carrier wave signal from the oscillator for the time of the push-pull operation in the pulse transformer;
A logic circuit that generates a signal in reverse phase with respect to the carrier signal from the timing adjustment means when an audio signal is input;
A fifth transistor which is generated by the logic circuit and is turned on / off with a rectangular wave having an opposite phase to the carrier wave signal from the timing adjustment unit;
A class-D amplifying device comprising: a sixth transistor that is turned on / off by a rectangular wave having the same phase as the carrier wave signal from the timing adjusting means.

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