JP2008154117A - Class-d amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a class-D amplifier which performs sufficiently wide gain control while maintaining a required S/N. <P>SOLUTION: The class-D amplifier comprises: a digital signal processing circuit 1, a class-D output stage 2 connected to output of the digital signal processing circuit 1; an output filter 4 for smoothing a signal outputted from the class-D output stage 2; and an analog gain control circuit 3 connected to the class-D output stage 2, wherein the amount of current to be supplied from the analog gain control circuit 3 to the class-D output stage 2 is adjusted so as to control a class-D amplification gain of the class-D output stage 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a class D amplifier that amplifies and outputs an input signal with high efficiency by a switching technique.

  Conventionally, a class D amplifier is known as a high efficiency amplifier. According to this class D amplifier, power amplification is performed by a pulse signal in which amplitude information of an analog input signal is reflected in a pulse width, and the pulse signal passes through a low-pass filter, so that a signal of an amplified analog amount is obtained. can get.

  As a method of converting amplitude information of an input analog signal into a pulse signal, there are a PWM (Pulse Width Modulation) that is controlled by the width of the pulse ON time, a PDM (Pulse Density Modulation) that is controlled by the pulse density, and the like. . With these pulse signals as inputs, the transistors in the class D output stage perform power amplification by switching operation, whereby highly efficient power amplification can be performed.

  Since such a class D amplifier can be formed on a silicon chip, it can be realized in a small size and at a low cost, and is widely used in portable terminals and personal computers that require low power consumption.

  FIG. 5 is a block diagram showing a configuration example of a conventional class D amplifier. In FIG. 5, 19 is a digital signal processing circuit, 20 is a digital gain adjustment circuit, 21 is a class D output stage, and 22 is an output filter.

  FIG. 6 shows a PWM signal as an example of an input signal input to the digital signal processing circuit 19 in the conventional class D amplifier. As shown in FIG. 6, the voltage of an analog signal to be amplified by the class D amplifier is compared with a triangular wave signal having a sufficiently higher frequency, and the period during which the analog signal is higher in voltage than the triangular wave is “H (high)”. By setting the level and vice versa to the “L (low)” level, the H period of the pulse signal becomes longer as the voltage value (amplitude) of the analog signal becomes higher than the reference value level (for example, 0 V), The L period of the pulse signal becomes longer as it becomes lower than the reference value level (for example, 0 V). It is converted into ()).

  The input signal (PWM signal) obtained by converting the amplitude information of the analog signal into the pulse width (the length of the H period or the L period) in this way is input to the digital signal processing circuit 19 to convert the sampling rate, oversampling, and noise shaper. Such digital signal processing is performed. The digital gain adjustment circuit 20 is configured as a part of the digital signal processing circuit 19 and performs gain adjustment in the process of digital signal processing for an input signal. The output of the digital signal processing circuit 19 is input to the class D output stage 21, and the output of the class D output stage 21 is input to the output filter 22.

  FIG. 7 is a circuit diagram showing a configuration example of the class D output stage 21 in the conventional class D amplifier. The class D output stage 21 is a switching circuit that outputs an “H” level or an “L” level. In this example, the gates of the NMOS transistor 23 and the PMOS transistor 24 are used as an input terminal, and the drains are connected in common as an output terminal. A drain output type configuration in which the sources of the transistor 23 and the PMOS transistor 24 are connected to GND and VCC, respectively.

  Here, for example, during a period in which the PWM signal is at the “H” level, the NMOS transistor 23 is turned on and the PMOS transistor 24 is turned off, so that the output voltage is approximately the GND potential, and the PWM signal is in the “L” level. In FIG. 5, the NMOS transistor 23 is turned off and the PMOS transistor 24 is turned on, and the output voltage is outputted so as to be approximately the VCC potential. In this way, the class D output stage operates as a switching circuit that outputs the VCC potential and the GND potential, and when the load resistance is RL, the output current increases or decreases from 0 A to the maximum value Imax = VCC / RL.

  When the transistor is ON, the maximum current Imax passes through the transistor. At this time, the resistance value between the drain and the source is very small, and the loss is almost zero. Since no current flows when the transistor is OFF, the loss is zero. Thus, the class D output stage is characterized by a very small loss, and the class D amplifier using the class D output stage can perform amplification with high efficiency.

  The signal output from the class D output stage 21 is output as an analog signal after unnecessary harmonic components are removed by the output filter 22. FIG. 8 is a circuit diagram showing a configuration example of the output filter 22 in the conventional class D amplifier, and FIG. 9 shows input / output waveforms of the output filter 22 shown in FIG.

  The output filter 22 is configured as a low-pass filter by an inductor 25 and a capacitor 26, thereby removing unnecessary high-frequency components. Since the class D output stage 21 performs a switching operation, only the voltage of VCC or GND is output. The amplitude information of the analog signal to be reproduced is included in the pulse width. An analog signal is regenerated by passing the pulse signal through the output filter 22.

  As shown in FIG. 9A, if the “H” period of the pulse waveform is long, an analog signal having a high voltage is reproduced in proportion to the period. On the contrary, as shown in FIG. 9B, if the period of “L” is long, an analog signal having a low voltage is reproduced in proportion to the period. As shown in FIG. 9C, when the ratio of 'H' and 'L' is the same, the output voltage becomes the reference value. By operating in proportion to the pulse width of the input pulse signal in this way, an analog signal can be reproduced from the PWM signal.

  As described above, the class D amplifier digitally processes the amplitude information of the analog signal as a pulse signal reflected in the pulse width by the digital signal processing circuit 19, and performs power amplification with high efficiency by the switching operation in the class D output stage 21. The pulse signal passes through the output filter 22 to obtain a power-amplified analog signal.

  In the conventional class D amplifier configured as described above, the digital signal processed by the digital signal processing circuit 19 is multiplied or divided by an arbitrary value by the digital gain adjustment circuit 20, thereby adjusting the gain. Has been done. Therefore, only the signal component is adjusted in the gain adjustment, and the quantization noise level generated in the digital signal processing circuit 19 does not change. For example, when the gain is set to -6 dB, a digital signal with a signal component of -6 dB is output, but the output quantization noise level does not change. As a result, S / N deteriorates by -6 dB. As described above, when the gain is lowered to lower the output level, the S / N is deteriorated by the amount that the gain is lowered.

To avoid this problem, the digital signal processing circuit 19 does not adjust the amplification gain digitally, but the class D output stage 21 adjusts the amplification gain in an analog manner to prevent S / N degradation. However, in the method of performing gain adjustment in the class D output stage 21 in this way (see, for example, Patent Document 1), the control circuit controls the number of transistors operated in the class D output stage 21 to output impedance. Is adjusted, the amplification gain in the class D output stage 21 is adjusted.
JP 2001-223537 A

  However, in the conventional class D amplifier as described above, the output impedance of the transistor operated in the class D output stage is very small, and many transistors are required to change the output impedance depending on the number of transistors operated. There is a problem of increasing the circuit scale.

  In addition, if the number of transistors to be operated is changed on a large scale such that the gain can be adjusted, the resistance between the drain and the source changes, causing fluctuations in the amplitude of the output signal, resulting in an error in gain adjustment. There is also a problem.

  The present invention solves the above-mentioned conventional problems. Even when the amplification gain is lowered to lower the output level without increasing the circuit scale, the gain adjustment is performed while maintaining the necessary S / N. Provided is a class D amplifier that can be widely and accurately performed.

  In order to solve the above problem, a class D amplifier according to claim 1 of the present invention is a digital signal processing circuit, a class D output stage for class D amplification of an output signal from the digital signal processing circuit, and An output filter for smoothing the output signal from the class D output stage, and the class D output stage amplifies the output signal from the digital signal processing circuit by class D by current output.

  A class D amplifier according to claim 2 of the present invention is the class D amplifier according to claim 1, wherein the analog for adjusting the gain of the class D amplification by adjusting the output current of the class D output stage. A gain adjustment circuit is provided.

  The class D amplifier according to claim 3 of the present invention is the class D amplifier according to claim 1 or 2, wherein the class D output stage is connected to a high voltage side of a power source. A series configuration of a transistor and a low-side switching transistor connected to the low-voltage side of the power supply, and the analog gain adjustment circuit has a current mirror configuration including the high-side switching transistor and the low-side switching transistor, and the class D A current source circuit for adjusting the output current of the output stage is provided.

  A class D amplifier according to a fourth aspect of the present invention is the class D amplifier according to any one of the first to third aspects, wherein the digital signal processing circuit has a gain adjustment function for a digital signal. It is characterized by having.

  A class D amplifier according to claim 5 of the present invention is the class D amplifier according to any one of claims 1 to 4, wherein the analog gain adjustment circuit and the class D output stage are separated from each other. A switching circuit is provided.

  As described above, according to the present invention, the current value supplied to the class D output stage can be adjusted in an analog manner by the analog gain adjustment circuit having the current mirror configuration connected to the class D output stage.

  Therefore, even when the amplification gain is lowered to reduce the output level without increasing the circuit scale, the gain adjustment can be performed widely and accurately while maintaining the necessary S / N.

Hereinafter, a class D amplifier showing an embodiment of the present invention will be specifically described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the class D amplifier according to the first embodiment. In FIG. 1, 1 is a digital signal processing circuit, 2 is a class D output stage, 3 is an analog gain adjustment circuit, and 4 is an output filter.

The input signal is subjected to digital signal processing such as sampling rate conversion, oversampling, and noise shaper by the digital signal processing circuit 1, and is output to the class D output stage 2. The class D output stage 2 is not a strict switching operation that completely turns on and off, but discharges the load current according to the current amount supplied from the analog gain adjustment circuit 3 to the output filter 4 when outputting the “H” level. When the 'L' level is output, it flows from the output filter 4. By this operation, the digital signal input from the digital signal processing circuit 1 is amplified.
The output filter 4 removes unnecessary harmonic components and takes out the output signal as an analog signal.

  According to such a configuration, when gain adjustment is performed, the gain of the input signal and the quantization noise generated in the digital signal processing circuit 1 is adjusted together, so that the S / N of the output signal does not deteriorate.

  FIG. 2 is a circuit diagram showing a detailed configuration example of the analog gain adjustment circuit 3 and the class D output stage 2 in FIG. 2, 5 is a PchMOS transistor, 6 is an NchMOS transistor, 2 is a class D output stage, 8 is a variable current source, 9 is an NchMOS transistor, 10 is an NchMOS transistor, 11 is a PchMOS transistor, and 3 is an analog gain adjustment circuit. ing.

  The class D output stage 2 includes a Pch MOS transistor 5 and an Nch MOS transistor 6. Input signals are respectively input to the gates of the Pch MOS transistor 5 and the Nch MOS transistor 6, and the commonly connected drains serve as output terminals. The analog gain adjustment circuit 3 includes a variable current source 8, an Nch MOS transistor 9, an Nch MOS transistor 10, and a Pch MOS transistor 11.

  The gate of the NchMOS transistor 9 is connected to the variable current source 8, the drain of the NchMOS transistor 9, the gate of the NchMOS transistor 10, and the gate of the NchMOS transistor 6. The NchMOS transistors 9, 10 and 6 are current mirrors having the NchMOS transistor 9 as a parent. Configure the circuit.

  The drain of the NchMOS transistor 10 is connected to the drain of the PchMOS transistor 11, the gate of the PchMOS transistor 11 is connected to the drain of the NchMOS transistor 11 and the gate of the PchMOS transistor 5, and the PchMOS transistors 11 and 5 are parented to the PchMOS transistor 11. Configure a current mirror circuit.

The operation of the analog gain adjustment circuit 3 and the class D output stage 2 configured as described above will be described below.
The class D output stage 2 performs a switching operation that is turned ON / OFF by an input signal, and supplies a load current from the output. At this time, since the Nch MOS transistor 6 forms a current mirror circuit having the Nch MOS transistor 9 as a parent, the load current supplied when the Nch MOS transistor 6 is turned on is connected to the current of the variable current source 8 by the Nch MOS transistor 6, 9 multiplied by the mirror ratio of the current mirror.

  Similarly, since the PchMOS transistor 5 forms a current mirror circuit with the PchMOS transistor 11 as a parent, the load current supplied when the PchMOS transistor 5 is turned on is connected to the current of the variable current source 8 by the NchMOS transistor 9, 10 multiplied by the mirror ratio of the current mirror composed of 10 and further multiplied by the mirror ratio of the current mirror composed of PchMOS transistors 11 and 5.

  Therefore, the analog gain adjustment circuit 3 can control the load current output from the class D output stage 2 by changing the current of the variable current source 8, and the gain of the class D amplifier can be adjusted.

  In this embodiment, the class D output stage 2 is composed of a PchMOS transistor and an NchMOS transistor, and the analog gain adjustment circuit 3 is composed of a current mirror circuit composed of a PchMOS transistor and an NchMOS transistor. Even when the stage 2 is composed of only an Nch MOS transistor or a bipolar transistor, the same effect can be obtained by matching the transistor polarity in the current mirror circuit configuration.

In the present embodiment, the current supplied to the class D output stage 2 is switched by changing the current amount of the variable current source 8, but can also be switched by switching the mirror ratio of the current mirror configuration. And the same effect can be obtained.
(Embodiment 2)
FIG. 3 is a block diagram showing the configuration of the class D amplifier according to the second embodiment. In FIG. 3, 13 is a digital signal processing circuit, 14 is a digital gain adjustment circuit, 15 is a class D output stage, 16 is an analog gain adjustment circuit, and 17 is an output filter.

  The input signal is subjected to digital signal processing such as sampling rate conversion, oversampling, and noise shaper by the digital signal processing circuit 13, and at the same time, gain adjustment is performed by the digital gain adjustment circuit 14 configured as a part of the digital signal processing circuit 13. Is done. The class D output stage 15 amplifies the signal input from the digital signal processing circuit 13 in accordance with the amount of current supplied from the analog gain adjustment circuit 16 and outputs the amplified signal to the output filter 17. The output filter 17 removes unnecessary harmonic components and takes out the output signal as an analog signal.

  According to such a configuration, the digital gain adjustment circuit 14 that is accompanied by S / N degradation but has a small circuit scale and low current consumption can be used in combination with the analog gain adjustment circuit 16 that does not involve S / N degradation. .

  For example, when it is desired to perform gain adjustment from 0 dB to −10 dB in 1 dB steps, the gain setting of the digital gain adjustment circuit 14 can be adjusted from 0 dB to −5 dB in 1 dB steps, and the gain setting of the analog gain adjustment circuit 16 is set to 0 dB. It shall be switched to -5 dB.

The analog gain adjustment circuit 16 is set to 0 dB from 0 dB to -4 dB, the analog gain adjustment circuit is set to -5 dB from -5 dB to -10 dB, and the rest is adjusted by the digital gain adjustment circuit. It is possible to adjust the gain up to -10 dB while suppressing the degradation of 5 dB at maximum, and in a system that can tolerate S / N degradation of 5 dB at maximum, without increasing the circuit scale and current consumption more than necessary. A class D amplifier can be realized.
(Embodiment 3)
FIG. 4 is a block diagram showing the configuration of the class D amplifier according to the third embodiment. The same reference numerals are used for the same components as those in FIG. In FIG. 4, reference numeral 18 denotes a switching circuit.

  The switching circuit 18 is connected between the class D output stage 15 and the analog gain adjustment circuit 16, and has a function of switching whether or not the analog gain adjustment circuit 16 adjusts the gain of the class D output stage 15.

  According to such a configuration, the analog gain adjustment circuit 16 is disabled by the switching circuit 18 when a large amplitude output signal is required or when it is desired to avoid an increase in current consumption due to the function of the analog gain adjustment circuit 16. Therefore, when it is necessary to suppress current consumption or when an output signal having a large amplitude is required, a wide range of correspondence can be realized.

  The class D amplifier of the present invention can perform gain adjustment widely and accurately while maintaining the necessary S / N even when the amplification gain is reduced to reduce the output level without increasing the circuit scale. It is useful as various power amplifiers that require gain adjustment in addition to audio output.

1 is a block diagram showing the configuration of a class D amplifier according to Embodiment 1 of the present invention. Circuit diagram showing a detailed configuration example of an analog gain adjustment circuit and a class D output stage in the class D amplifier of the first embodiment The block diagram which shows the structure of the class D amplifier of Embodiment 2 of this invention. The block diagram which shows the structure of the class D amplifier of Embodiment 3 of this invention. Block diagram showing the configuration of a conventional class D amplifier Waveform diagram showing a PWM signal as an example of a signal input to a digital signal processing circuit in the conventional class D amplifier Circuit diagram showing a configuration example of a class D output stage in the conventional class D amplifier Circuit diagram showing a configuration example of an output filter in the conventional class D amplifier Waveform diagram showing the input / output signals of the output filter in the conventional class D amplifier

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Digital signal processing circuit 2 Class D output stage 3 Analog gain adjustment circuit 4 Output filter 5 PchMOS transistor 6 NchMOS transistor 8 Variable current source 9 NchMOS transistor 10 NchMOS transistor 11 PchMOS transistor 13 Digital signal processing circuit 14 Digital gain adjustment circuit 15 Class D Output stage 16 Analog gain adjustment circuit 17 Output filter 18 Switching circuit 19 Digital signal processing circuit 20 Digital gain adjustment circuit 21 Class D output stage 22 Output filter 23 NMOS transistor 24 PMOS transistor 25 Inductor 26 Capacitor

Claims (5)

A digital signal processing circuit;
A class D output stage for class D amplification of the output signal from the digital signal processing circuit;
An output filter for smoothing the output signal from the class D output stage,
The class D output stage is:
A class D amplifier characterized by a class D amplification of an output signal from the digital signal processing circuit by a current output. 2. The class D amplifier according to claim 1, further comprising an analog gain adjustment circuit that adjusts an output current of the class D output stage to adjust a gain of the class D amplification. The class D output stage is:
Having a series configuration of a high-side switching transistor connected to the high-voltage side of the power source and a low-side switching transistor connected to the low-voltage side of the power source;
The analog gain adjustment circuit is
3. The D according to claim 1, wherein a current source circuit that adjusts an output current of the class D output stage is configured by a current mirror configuration including the high-side switching transistor and the low-side switching transistor. Class amplifier. The class D amplifier according to any one of claims 1 to 3, wherein the digital signal processing circuit has a gain adjustment function for a digital signal. 5. The class D amplifier according to claim 1, further comprising a switching circuit that separates the analog gain adjustment circuit from the class D output stage. 6.

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