JP2010040596A - Laminated lead frame and method of manufacturing the same, and semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated lead frame that meets diffusion bonding conditions of a laminated lead frame having no plating layer formed. <P>SOLUTION: The laminated lead frame is constituted by applying predetermined form-shaping to each of a lead frame material and a lead frame material for lamination (a conductor plate 16 and a surface outside terminal 17), and bonding the lead frame material for lamination on the form-shaped lead frame material, wherein a surface of the lead frame material made of copper or copper alloy is coated with an copper oxide layer C of ≥0.1 μm in thickness. The copper oxide layer formed on the lead frame material prevents a brittle copper oxide coating film from being formed, and tight adhesiveness between the lead frame material and the formed copper oxide layer improves reliability of a semiconductor device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a laminated lead frame, and more particularly to a laminated lead frame capable of improving the reliability of a semiconductor device and a semiconductor device using the same.

  In the structure of an IC (Integrated Circuit) semiconductor device, there are a plurality of independent stacked semiconductor devices (PoP: Package on Package) for the purpose of realizing high integration and high-density mounting of internal electronic components of small electronic devices. By stacking individual semiconductor devices in the height direction, the mounting area is reduced while improving the yield of the individual semiconductor devices. Among the semiconductor devices used in the stacked semiconductor device, the semiconductor device located in the lowermost layer is characterized by having a terminal for connecting the upper layer semiconductor device on the upper surface in addition to the substrate mounting terminal on the lower surface. Yes, it is necessary to make an electrical connection from the lower surface terminal to the upper surface terminal. As in Patent Document 1, the structure of the lowermost semiconductor device having double-sided electrodes using a lead frame material is formed by stacking and joining a plurality of laminated lead frame materials having different shapes, and increasing the thickness of the laminated lead frame material. A “laminated lead frame” method is known in which a semiconductor device is formed using electrodes to form electrodes on upper and lower surfaces.

  For joining the lead frame materials, a diffusion joining method by applying an appropriate load and heat from the thickness direction to the superimposed lead frame material and the laminated lead frame material is mainly used. In this diffusion bonding, first, as shown in FIG. 8A, a load is applied in a state where the metal material 41 that is the lead frame material and the metal material 42 that is the lead frame material for lamination are overlapped, and FIG. As shown, when heated, atomic energy in the metal material is activated, atomic diffusion occurs between the materials, and the metal materials 41 and 42 are bonded to each other. Thereafter, the semiconductor chip 43 is mounted on the semiconductor mounting portion as shown in FIG. 8C, the wire 44 is bonded, and the semiconductor device is manufactured by sealing with a resin 45 as shown in FIG. 8D. . In this diffusion bonding method, generally, the higher the temperature, the easier the diffusion and the better the bondability.

By using this diffusion bonding method, it is possible to realize bonding having bonding strength, conductivity, and heat conductivity equivalent to those of the base material.
In addition, a metal having high diffusibility as a “diffusion insert material” is formed on the lead frame material as a plating layer so that bonding heating can be performed at the lowest possible temperature.

  A thin copper oxide film (copper oxide film) is formed on the surface of the lead frame material made of copper or copper alloy by heating. For example, as described in Patent Document 1, the lead frame material is selectively etched (primary etching) after leaving the portion on which the semiconductor element mounting portion and the bonding terminal are formed to be about half the thickness from the surface side, and then the semiconductor An element is mounted and wire bonding is performed, but as shown in FIG. 9A, a brittle copper oxide film is exposed at a portion where a copper or copper alloy metal material such as a terminal side surface is exposed by heating in the wire bonding step. Will be formed. Since this copper oxide film has extremely low adhesion to the metal material, as shown in FIG. 9B, the sealing resin is a resin at the interface with the lead frame material due to the fragile copper oxide film. As a result, peeling occurs, and the reliability of the semiconductor device is remarkably lowered.

Patent Documents 2 and 3 describe an invention in which a copper material is immersed in a forced oxidant to form a copper oxide layer on the surface in order to prevent resin peeling that occurs on the surface of the lead frame.
Further, there is known a means for protecting by forming a noble metal plating layer such as gold on the entire surface of the lead frame including a portion exposed by etching.

JP 2008-71815 A JP 2002-231871 A JP 2004-14842 A

However, in order to promote diffusion bonding for forming the laminated lead frame, it is necessary to heat at a temperature higher than the recrystallization temperature of the material. For example, when a gold plating layer is used as a diffusion insert material, diffusion bonding of the lead frame material is performed with a load applied at 240 ° C. or higher for 15 minutes. In order to form a semiconductor device as described in Patent Document 1 as a stacked semiconductor device, it is necessary to perform diffusion bonding at a high temperature for a long time, but the thickness in Patent Document 2 and Patent Document 3 is 0.001. In a copper oxide layer of ~ 0.1 μm, the copper of the lead frame material diffuses on the copper oxide layer under diffusion bonding conditions to form a more fragile copper oxide film. It will peel off and the reliability of a semiconductor device will fall.
Further, if a plating layer is formed on the entire surface of the lead frame, a large amount of noble metal such as gold is used, resulting in an increase in cost.

  In view of the above circumstances, the present invention does not form a fragile copper oxide film on a portion where a metal material is exposed, even under diffusion bonding conditions in a multilayer lead frame in which a plating layer is not formed. An object of the present invention is to provide a laminated lead frame that does not cause this, a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof.

  In order to solve the above-mentioned problems, the present invention relates to the following laminated lead frames (1) to (16), a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof.

(1) In a laminated lead frame in which a lead frame material and a laminated lead frame material are respectively processed into a predetermined shape, and the laminated lead frame material is joined on the shaped lead frame material.
Of the lead frame material and the lamination lead frame material, at least the lead frame material is made of a material made of copper or a copper alloy, and the surface of the lead frame material is covered with a copper oxide layer. Lead frame.

(2) In a laminated lead frame formed by subjecting a lead frame material and a laminated lead frame material to predetermined shape processing, and joining the laminated lead frame material on the shaped lead frame material,
A laminated lead frame, wherein surfaces of the lead frame material made of copper or copper alloy and at least one of the laminated lead frame materials laminated thereon are covered with a copper oxide layer.

(3) The laminated lead frame according to (1) or (2), wherein the copper oxide layer has a thickness of 0.1 μm or more.

(4) The laminated lead frame according to any one of (1) to (3), wherein the copper oxide layer is composed of cuprous oxide (Cu ₂ O) and copper monoxide (CuO).

(5) In a method for manufacturing a laminated lead frame, wherein the lead frame material and the laminated lead frame material are each processed in a predetermined shape, and the laminated lead frame material is bonded onto the shaped lead frame material.
Of the lead frame material and the lamination lead frame material, at least the lead frame material is made of copper or a copper alloy, and the surface of the lead frame material is covered with a copper oxide layer. Lead frame manufacturing method.

(6) In a method for manufacturing a laminated lead frame, in which a lead frame material and a laminated lead frame material are each processed in a predetermined shape, and the laminated lead frame material is bonded onto the shaped lead frame material.
A method for producing a laminated lead frame, wherein the surfaces of the lead frame material made of copper or a copper alloy and at least one of the laminated lead frame materials laminated thereon are covered with a copper oxide layer.

(7) The method for producing a laminated lead frame according to (5) or (6), wherein the thickness of the copper oxide layer is 0.1 μm or more.

(8) the copper oxide layer is cuprous oxide (2 Cu _O) and one of the layered manufacturing method of lead frame of copper monoxide characterized by consisting with (CuO) (5) ~ (7).

(9) In a semiconductor device having a laminated lead frame in which a lead frame material and a laminated lead frame material are respectively processed in a predetermined shape, and the laminated lead frame material is bonded onto the shaped lead frame material. ,
Among the lead frame material and the laminated lead frame material, at least the lead frame material is a material made of copper or a copper alloy, and a laminated lead frame in which the surface of the lead frame material is covered with a copper oxide layer,
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
A semiconductor device comprising: a sealing resin for sealing the semiconductor element.

(10) In a semiconductor device having a laminated lead frame in which a lead frame material and a laminated lead frame material are processed in a predetermined shape, and the laminated lead frame material is bonded onto the shaped lead frame material. ,
A laminated lead frame in which the surfaces of the lead frame material made of copper or copper alloy and at least one of the laminated lead frame materials laminated thereon are coated with a copper oxide layer;
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
A semiconductor device comprising: a sealing resin for sealing the semiconductor element.

(11) a laminated lead frame in which the thickness of the copper oxide layer is 0.1 μm or more;
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
The semiconductor device according to (9) or (10), comprising: a sealing resin for sealing the semiconductor element.

(12) a laminated lead frame in which the copper oxide layer is composed of cuprous oxide (Cu ₂ O) and copper monoxide (CuO);
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
The semiconductor device according to any one of (9) to (11), comprising a sealing resin for sealing the semiconductor element.

(13) In a method for manufacturing a semiconductor device in which a lead frame material and a lead frame material for lamination, each having a predetermined shape processing, are joined.
A lead frame pattern forming step of forming a pattern on a resist film coated on the lead frame material;
A plating step of forming a predetermined plating layer on the front and back surfaces of the lead frame material;
A primary etching step of performing etching using the plating layer formed on the surface side of the lead frame material as a plating resist;
A copper oxide layer forming step of immersing the lead frame material in a forced oxidizing agent to form a copper oxide layer on the surface of the lead frame material;
A bonding step of bonding the lead frame material and at least one or more of the lamination lead frame materials;
A resin sealing step of mounting a semiconductor element on the lead frame material, connecting the semiconductor element and a terminal portion with a bonding wire, and sealing the semiconductor element and the terminal portion with a resin;
A method of manufacturing a semiconductor device, comprising: a secondary etching step of performing etching using the plating layer formed on the back surface side of the lead frame material as a plating resist to make the terminal portions independent.

(14) The method for manufacturing a semiconductor device according to (13), wherein the copper oxide layer is formed on a side surface of the terminal portion and an upper surface of the element mounting portion.

(15) The method for manufacturing a semiconductor device according to (13) or (14), wherein the copper oxide layer has a thickness of 0.1 μm or more.

(16) The method for manufacturing a semiconductor device according to any one of (13) to (15), wherein the copper oxide layer is made of cuprous oxide (Cu ₂ O) and copper monoxide (CuO).

  In the present invention, a surface treatment (chemical treatment) is performed on the exposed surface of the copper material (or copper alloy) of the lead frame material before the diffusion bonding step, and a copper oxide layer of preferably 0.1 μm or more is forcibly formed. (Forced oxidation treatment), preventing formation of a fragile copper oxide film due to copper diffusion of the lead frame material on the copper oxide layer under long-time high temperature conditions in the diffusion bonding process, and the fragile copper oxide film It is possible to prevent the occurrence of resin peeling due to.

In addition, when the formation of a copper oxide layer is applied not only to the lead frame material but also to the lead frame material for lamination, the lead frame material for lamination may be a minimum of partial plating only on the terminal part and the joint part, such as gold. The amount of noble metal used can be reduced and the cost can be reduced. In this case as well, the formation of a brittle copper oxide film is prevented as in the case of the lead frame material, and the resin is prevented from peeling by improving the adhesion with the lead frame material, and the surface of the copper oxide layer is further improved by forced oxidation treatment. As a result, the anchor effect is enhanced, the adhesion between the laminated lead frame and the sealing resin can be increased, and the reliability of the semiconductor device can be improved.
Since the forced oxidation treatment used in the present invention does not react with metals other than copper at all, there is no effect on the surface of the plating layer even after the formation of the copper oxide layer, and sufficient diffusion bonding strength can be secured. There is no decline in bonding and solder wettability.

  Further, it can be applied not only to a semiconductor device having a stand-off formed but also to an ordinary stacked semiconductor device such as QFP, and it is only necessary to partially form a plating layer on the lead frame material, and the entire surface needs to be plated. This reduces the amount of precious metal used.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a use state of the semiconductor device according to the first embodiment.
In addition, the form for implementing this invention shown below is an example of the specific aspect of this invention, and is not limited to the said form.

As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 12 arranged in the center of the element mounting portion 11, and terminal portions arranged in an area array (bonding wires 13 are applied to the respective electrode pads of the semiconductor element 12. A group of back inner terminals 14 that are connected to each other and exposed from the bottom surface of the semiconductor device 10 and arranged in an area array, and a back outer terminal 15 that is formed in an area array alongside the group of the back inner terminals 14. And a lead frame material for lamination (for example, a conductor made of copper or a copper alloy) which is directly above the back outer terminal 15 and is partially exposed from the upper surface of the semiconductor device 10 and connected to the back outer terminal 15. A group of front and outer terminals 17 made of, for example, copper or a copper alloy, which are electrically connected via the conductor plate), these semiconductor elements 12 and bonding wires 13, and terminals And plating resin 19 and 19a are formed on the front and back surfaces of the back inner terminal 14 and the back outer terminal 15, respectively. A plating layer 19b is formed on the substrate. In addition, the contact surface with the sealing resin 18 of the element mounting part 11, the terminal part, and the side part of the lead frame material for lamination is a copper oxide layer made of cuprous oxide (Cu ₂ O) or copper monoxide (CuO). Is formed.

  Here, the semiconductor element 12 is fixed to the element mounting portion 11 via the conductive adhesive layer 20, and plating layers 19 and 19 a are applied to the front and back sides of the element mounting portion 11 in the same manner as the terminal portion. . By forming the plating layers 19 and 19a on the terminal portion, it is possible to maintain bondability and to have a function as a diffusion insert material at the time of diffusion bonding. Furthermore, the plating layer 19b is also formed on the front and back surfaces of the conductor plate 16 and the front and back surfaces of the front and outer terminals 17, so that a function as a diffusion insert material at the time of diffusion bonding can be provided.

  In this embodiment, gold is used for the plating layers 19, 19 a, 19 b, but the plating layers 19, 19 a, 19 b are formed by plating with one or a combination selected from silver, palladium, copper, tin, nickel, etc. Also good. In this embodiment, the nickel base plating layer is formed prior to the formation of the plating layers 19, 19a, 19b. However, the plating layer can be formed directly without forming the base plating.

  In FIG. 2 showing the use state of the semiconductor device of FIG. 1, in the semiconductor device 10, the back inner terminal 14 is connected to the semiconductor element 12, and the back outer terminal 15 is connected to the front outer terminal 17 via the conductor plate 16, respectively. Therefore, for example, as shown in FIG. 2, the semiconductor device 10 is disposed on the lower side and the other semiconductor device 21 is disposed on the upper side, so that the connection terminals exposed on the front and outer terminals 17 of the semiconductor device 10 and the bottom surface of the semiconductor device 21. The layer can be laminated while being electrically connected to 22. Thereby, three-dimensional system mounting can be realized using the semiconductor devices 10 and 21. Here, 23 is a semiconductor element of the semiconductor device 21, 24 is an element mounting portion, 25 is a bonding wire, 26 is an unexposed portion of the connection terminal 22, a sealing resin for sealing the semiconductor element 23 and the bonding wire 25. .

  Although the said Example demonstrated the case where the lead frame material for lamination | stacking of copper or a copper alloy (the conductor board 16, the outer side outer terminal 17) was used, the lead frame material for lamination | stacking is not restricted to this, Iron system, such as Alloy42, etc. It can also be applied to lead frames. In the above embodiment, the conductor plate 16 and the outer side terminal 17 are used as the lead frame material for lamination. However, only the conductor plate 16, only the outer side terminal 17 or a plurality of layers of them are laminated leads. A frame can be formed. As the diffusion insert material, not only gold but also a highly diffusible metal such as silver or palladium can be used. For example, a gold plating layer is used for the bonding surface of the lead frame material, and a bonding surface of the laminated lead frame material is used. It is also possible to apply a diffusion insert material of a different material such as a silver plating layer.

  Next, a method for manufacturing the semiconductor device 10 according to the first embodiment will be described with reference to FIG.

  In the first embodiment, only one semiconductor device will be described. However, a plurality of semiconductor devices are actually connected in multiple columns and multiple rows. FIG. 3 shows only the left half of the semiconductor device 10 among the plurality of semiconductor devices.

(1): Lead frame pattern process As shown in FIG. 3A, an element mounting portion in which the semiconductor element 12 is mounted on a lead frame material 28 (copper or copper alloy) whose front and back surfaces are covered with a resist film 27. 11. Exposure processing is performed on a pattern that forms a group of back inner terminals 14 and a group of back inner terminals 15, and then development processing is performed to form patterns on the resist films 27 on the front and back of the lead frame material 28.

(2): Plating step As shown in FIG. 3B, nickel base plating is performed on the front and back of the lead frame material 28 to form plated layers 19 and 19a by gold plating.

(3): Resist Film Removal Step As shown in FIG. 3C, the resist film 27 on the front and back sides of the lead frame material 28 is removed.

(4): Cover Tape Application Step As shown in FIG. 3D, a cover tape 29 is applied to the back surface of the lead frame material 28 to cover the entire back surface of the lead frame material 28.

(5): Primary etching As shown in FIG. 3E, the gold plating layer 19a formed on the front side of the lead frame material 28 is used as a plating resist to the lead frame material 28 from the surface side to a predetermined depth (for example, lead 3/4 to 1/2) of the thickness of the frame material 28 is performed, and the upper surface side of the element mounting portion 11, the upper surface side of the group of the back inner terminals 14, and the group of the back outer terminals 15 The upper side is protruded, and then the cover tape 29 is removed.
At this time, the lower portion of the element mounting portion 11, the group of the back inner terminals 14, and the group of the back outer terminals 15 are connected by the connecting member 30.

(6): Copper oxide layer forming step As shown in FIG. 3 (F), forcibly oxidizing the exposed portion of the metal material surface of the lead frame material 28, that is, each terminal portion and the side surface portion of the element mounting portion. The copper oxide layer C is formed by immersing the lead frame material 28 in a forced oxidizing agent.

(7): Joining step As shown in FIG. 3G, the conductor plate 16 is placed on each back outer terminal 15 of the lead frame material 28, and the front outer terminal 17 is placed thereon. These are diffusion bonded.
Here, the conductor plate 16 is formed in advance in another process (not shown), specifically, a laminated lead frame material made of copper or a copper alloy whose front and back surfaces are coated with a resist film, A pattern of a group of conductor plates 16 is formed, an etching process is performed, gold plating layers 19b are formed on the upper and lower surfaces of the conductor plates, and the side surfaces of the conductor plates 16 are formed in the same manner as in the above (6): copper oxide layer forming step. A copper oxide layer C is formed.

Similarly, the front and outer terminals 17 are also formed by forming a pattern of a group of front and outer terminals 17 on a lead frame material made of copper or copper alloy whose front and back surfaces are coated with a resist film, and performing an etching process. The gold plating layer 19b is formed on the upper surface and the lower surface of the terminal 17, and the copper oxide layer C is formed on the side surface of the outer terminal 17 in the same manner as in the step (6): copper oxide layer formation.
In addition, the bonding between the back outer terminal 15 and the conductor plate 16 and the bonding between the conductor plate 16 and the outer outer terminal 17 are performed by applying a load to the upper surface of the outer outer terminal 17 through a gold plating layer formed on the contact surface. The diffusion bonding is performed by heating to a predetermined temperature.
Thereby, the laminated lead frame 31 used for the semiconductor device 10 is formed.
In addition, if the plating layer is formed in advance on the entire surface of the conductor plate 16 that is the lead frame material for lamination and the front and outer terminals 17, it is not necessary to form a copper oxide layer on the lead frame material for lamination. It is preferable to use a highly diffusible metal as a “diffusion insert” on the contact surface of the joint.

(8): Die-bonding step As shown in FIG. 3 (H), the semiconductor element 12 is fixed on the element mounting portion 11 via the conductive adhesive layer 20.

(9): Wire bonding step As shown in FIG. 3I, each electrode pad of the semiconductor element 12 and the corresponding back inner terminal 14 (bonding wire connection region formed on the upper surface of the back inner terminal) are wire bonded. Connect electrically.

(10): Resin sealing step As shown in FIG. 3J, the semiconductor element 12, the bonding wire 13, the back inner terminals 14, the back outer terminals 15, and the external connection terminals of the front outer terminals 17 The part excluding the part is put in a mold and sealed with a sealing resin 18.

(11): Secondary etching step As shown in FIG. 3 (K), a secondary etching process is performed by using the plating layer 19 formed on the back side of the lead frame material 28 as a plating resist, and the element mounting portion 11 and the back inner side. The connecting member 30 that connects the terminal 14 and the back outer terminal 15 is removed, and these are electrically separated and then cut into individual semiconductor devices, whereby the semiconductor device 10 is manufactured.

  In the above embodiment, the gold plating layer 19a is also formed on the upper surface of the element mounting portion 11 to form a plating resist so that the upper surface height of the element mounting portion 11 and the upper surface height of the terminal portion are the same. However, in order to reduce the size of the semiconductor device and shorten the length of the bonding wire as in the second embodiment shown in FIG. 4, about half of the upper surface of the element mounting portion 11 is removed by primary etching. However, the element mounting position may be formed low. In this case, since the lead frame material is exposed over the entire upper surface of the element mounting portion 11, there is a concern about peeling at the interface between this portion and the resin sealing, but the copper oxide layer C is formed on the upper surface of the element mounting portion 11. By forming, the adhesiveness with the sealing resin is strengthened, and the reliability of the semiconductor device can be improved.

Next, a method for forming a copper oxide layer using a forced oxidizing agent will be described.
In this embodiment, the forced oxidizing agent is a mixture of sodium chlorite or sodium persulfate with caustic. When “Emplate MB-438 (Meltex)” is used as a sodium chlorite type, the surface of the lead frame material is washed with acid or pure water in advance, and then a low concentration forced oxidant is used at a temperature of 20 ° C. Soak for 60 seconds. Then, it is immersed for 300 seconds at a temperature of 80 ° C., washed with water and dried. As a result, the copper of the lead frame material is oxidized by the forced oxidizing agent to form a copper oxide layer having a thickness of about 0.5 μm.
The copper oxide layer contains cuprous oxide (Cu ₂ O) and copper monoxide (CuO).

  FIG. 5 is an explanatory view showing the effect of the present invention. Since the copper oxide layer is formed with needle-like irregularities, the anchor effect is enhanced, and the adhesion between the laminated lead frame and the sealing resin can be further increased, so that the reliability of the semiconductor device can be improved. In addition, the thickness of the copper oxide layer can be changed depending on the chemical concentration, treatment time, and temperature, and as the layer thickness increases, the color tone changes from bronze to reddish brown to brown to black, acicular crystals The convex shape becomes a longer layer shape. The thickness of the strong copper oxide layer that can withstand the diffusion bonding heating (240 ° C. × 15 min) of the present invention is 0.1 μm or more, and the color tone is brown.

The reaction formula of the copper oxide layer is as follows.
2Cu + NaClO ₂ + 2H ₂ O → 2Cu (OH) ₂ + NaCl
2Cu (OH) ₂ → 2CuO + 2H ₂ O
When a forced oxidant comes into contact with the copper surface, a thin Cu ₂ O layer is quickly formed, and when the oxidation further proceeds, it becomes an intermediate compound of Cu (OH) ₂ .
A part of this becomes CuO and is tightly bonded to the Cu surface to form a strong copper oxide layer.

The remaining Cu (OH) ₂ reacts with excess —OH to become Cu (OH) _m ^m−2 , and CuO is reprecipitated. Since this CuO is crystal-formed in a needle shape, an anchor effect with the sealing resin in the assembly process can be produced.

  The forced oxidant used in the present invention does not affect the plating layer, and even if oxidation treatment is performed, the strength of diffusion bonding and the bonding strength of wire bonding can be sufficiently secured, and there is no effect on solder wettability. .

  As a result, the formed copper oxide layer can increase the adhesion between the lead frame material and the copper oxide layer, prevent the resin from peeling off, and improve the reliability of the semiconductor device.

○：良 ×：不良
Table 1 shows the evaluation of the reliability of the semiconductor device with respect to the thickness of the copper oxide layer.

○: Good ×: Bad

The thickness of the copper oxide layer according to the embodiment of the present invention is suitably 0.1 to 1 μm. Under the above conditions, a copper oxide layer having a thickness of 1 μm can be formed in 10 minutes in a forced oxidizer. And
Although it is possible to make the copper oxide layer thicker than 1 μm, there is no significant difference in the effect of the copper oxide layer thicker than 1 μm formed over a long time and the copper oxide layer having a thickness of 0.1 to 1 μm. Considering this point, it is not preferable from the viewpoint of productivity to form a copper oxide layer thicker than 1 μm.

  In the first and second embodiments, a partial plating layer is formed, primary etching is performed using the plating layer as a plating resist, and the lead frame material in which copper (or copper alloy) is exposed is copper oxide. Although the layer is formed, it can also be applied to a lead frame material in which a plating layer is formed on the upper surface of the terminal portion after etching using a general resist film, and the lead frame material after the plating layer is formed is exposed. By forming the copper oxide layer in the part, the formation of a fragile copper oxide film is prevented, and there is no need to perform a rust prevention treatment after the lead frame material is formed. In addition, since the plating layer may be partially formed, the amount of metal used can be reduced, and the manufacturing cost can be reduced.

Furthermore, the present invention can also be applied to general SON (Small Outline Nom-leaded Package) and QFP (Quad Flat Non-leaded Package).
6 and 7 are explanatory views of a third embodiment in which SON is formed in a stacked semiconductor device.
6 is a cross-sectional view of the stacked semiconductor device, and FIG. 7 is a view of a part A of FIG. First, after forming a gold plating layer on the upper and lower surfaces of the terminal part and the element mounting part, it is possible to ensure adhesion with the sealing resin by forming a copper oxide layer on the side surface of the terminal part and the element mounting part. it can.
In the present embodiment, the plating layer only needs to be formed on the upper and lower surfaces of the terminal portion and the element mounting portion, and compared to the case where the plating layer is formed on the entire surface, the amount of plating metal used can be reduced, Cost can be reduced.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the use condition of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows the effect of this invention. It is sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is the perspective view seen from the back surface which shows a part of semiconductor device concerning the 3rd Embodiment of this invention. It is explanatory drawing of the conventional diffusion bonding system. It is explanatory drawing which shows the conventional problem.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Element mounting part 12 Semiconductor element 13 Bonding wire 14 Back inner side terminal 15 Back outer side terminal 16 Conductor board 17 Outer side outer terminal 18 Sealing resin 19, 19a, 19b Plating layer 20 Conductive adhesive layer 21 Semiconductor device 22 Connection Terminal 23 Semiconductor element 24 Element mounting portion 25 Bonding wire 26 Sealing resin 27 Resist film 28 Lead frame material 29 Cover tape 30 Connecting member 31 Multilayer lead frame 32 Support lead 34 Support lead

Claims (16)

In a laminated lead frame in which a lead frame material and a laminated lead frame material are respectively processed into a predetermined shape, and the laminated lead frame material is joined on the shaped lead frame material,
Of the lead frame material and the lamination lead frame material, at least the lead frame material is made of a material made of copper or a copper alloy, and the surface of the lead frame material is covered with a copper oxide layer. Lead frame. In a laminated lead frame in which a lead frame material and a laminated lead frame material are respectively processed into a predetermined shape, and the laminated lead frame material is joined on the shaped lead frame material,
A laminated lead frame, wherein surfaces of the lead frame material made of copper or copper alloy and at least one of the laminated lead frame materials laminated thereon are covered with a copper oxide layer.   The multilayer lead frame according to claim 1, wherein the copper oxide layer has a thickness of 0.1 μm or more. The laminated lead frame according to claim 1, wherein the copper oxide layer is made of cuprous oxide (Cu ₂ O) and copper monoxide (CuO). In the manufacturing method of the laminated lead frame, in which the lead frame material and the laminated lead frame material are respectively processed into a predetermined shape, and the laminated lead frame material is joined on the shaped lead frame material.
Of the lead frame material and the lamination lead frame material, at least the lead frame material is made of copper or a copper alloy, and the surface of the lead frame material is covered with a copper oxide layer. Lead frame manufacturing method. In the manufacturing method of the laminated lead frame, in which the lead frame material and the laminated lead frame material are respectively processed into a predetermined shape, and the laminated lead frame material is joined on the shaped lead frame material.
A method for producing a laminated lead frame, wherein the surfaces of the lead frame material made of copper or a copper alloy and at least one of the laminated lead frame materials laminated thereon are covered with a copper oxide layer.   The method for manufacturing a laminated lead frame according to claim 5 or 6, wherein the copper oxide layer has a thickness of 0.1 µm or more. The method for manufacturing a multilayer lead frame according to claim 5, wherein the copper oxide layer is made of cuprous oxide (Cu ₂ O) and copper monoxide (CuO). In a semiconductor device having a laminated lead frame in which a lead frame material and a laminated lead frame material are processed in a predetermined shape, and the laminated lead frame material is bonded onto the shaped lead frame material.
Among the lead frame material and the laminated lead frame material, at least the lead frame material is a material made of copper or a copper alloy, and a laminated lead frame in which the surface of the lead frame material is covered with a copper oxide layer,
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
A semiconductor device comprising: a sealing resin for sealing the semiconductor element. In a semiconductor device having a laminated lead frame in which a lead frame material and a laminated lead frame material are processed in a predetermined shape, and the laminated lead frame material is bonded onto the shaped lead frame material.
A laminated lead frame in which the surfaces of the lead frame material made of copper or copper alloy and at least one of the laminated lead frame materials laminated thereon are coated with a copper oxide layer;
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
A semiconductor device comprising: a sealing resin for sealing the semiconductor element. A laminated lead frame having a copper oxide layer thickness of 0.1 μm or more;
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
The semiconductor device according to claim 9, further comprising a sealing resin that seals the semiconductor element. A laminated lead frame in which the copper oxide layer comprises cuprous oxide (Cu ₂ O) and copper monoxide (CuO);
A semiconductor element fixed to the element mounting portion of the laminated lead frame;
It has sealing resin which seals the said semiconductor element, The semiconductor device in any one of Claims 9-11 characterized by the above-mentioned. In the manufacturing method of the semiconductor device formed by joining the lead frame material and the lead frame material for lamination, each having a predetermined shape processing,
A lead frame pattern forming step of forming a pattern on a resist film covering the surface of the lead frame material;
A plating step of forming a predetermined plating layer on the front and back surfaces of the lead frame material;
A primary etching step of performing etching using the plating layer formed on the surface side of the lead frame material as a plating resist;
A copper oxide layer forming step of immersing the lead frame material in a forced oxidizing agent to form a copper oxide layer on the surface of the lead frame material;
A bonding step of bonding the lead frame material and at least one or more of the lamination lead frame materials;
A resin sealing step of mounting a semiconductor element on the lead frame material, connecting the semiconductor element and a terminal portion with a bonding wire, and sealing the semiconductor element and the terminal portion with a resin;
Etching with the plating layer formed on the back side of the lead frame material as a plating resist, and a secondary etching step for making the terminal portions independent.   The method for manufacturing a semiconductor device according to claim 13, wherein the copper oxide layer is formed on a side surface of the terminal portion and an upper surface of the element mounting portion.   The method of manufacturing a semiconductor device according to claim 13, wherein the copper oxide layer has a thickness of 0.1 μm or more. The method for manufacturing a semiconductor device according to claim 13, wherein the copper oxide layer is made of cuprous oxide (Cu ₂ O) and copper monoxide (CuO).

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