JP2010040537A - Semiconductor integrated circuit and designing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To arrange decoupling cells at positions capable of efficiently preventing voltage drop or noise without the necessity of an enormous amount of processing time for calculating the arrangement positions of the decoupling cells. <P>SOLUTION: The semiconductor integrated circuit 100 includes: power supply wirings 101, 102 for cells of first potential and second potential; a first power supply wiring 103 and a second power supply wiring 104 arranged in a direction perpendicular to the power supply wirings for cells of first potential and second potential; standard cells 105; and decoupling cells 106. First potential, i.e. power supply potential is supplied to the first power supply wiring 103; and second potential, i.e. ground potential is supplied to the second power supply wiring 104. The decoupling cells 106 are arranged below the second power supply wiring 104, and supplied with the first potential and the second potential. The region where the standard cells 105 are arranged is a region other than the region where the decoupling cells 106 are arranged. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a decoupling cell composed of a capacitor element is appropriately arranged in a standard cell system in which a capacitor element for power supply decoupling is formed in a semiconductor chip, and a design method thereof.

  In a semiconductor chip forming a semiconductor integrated circuit, power supply potential and ground potential are generally supplied via pads. In a logic gate circuit or the like arranged far from the pad, the power supply voltage between the power supply potential and the ground potential decreases due to a voltage drop due to the resistance component of the wiring from the pad to the pad. In addition, in a large-scale / high-speed LSI or the like, since a synchronous design type automation technology is introduced, all circuits operate in synchronization with a reference clock, and an instantaneous current becomes very large.

  Therefore, a decoupling cell capable of accumulating charges is arranged between the power supply potential wiring and the ground potential wiring to assist power supply from the power supply and suppress a decrease in power supply voltage.

  However, enormous processing time is required to calculate an appropriate insertion position of the decoupling cell, and there is a problem in that the development period is prolonged. In addition, even if the optimal insertion location is calculated over an enormous amount of processing time, decoupling cells cannot be placed in areas where other cells or signal wirings are dense, and sufficient power supply voltage reduction is suppressed. Some issues cannot be done.

In order to solve these problems, in Patent Document 1 described later, a semiconductor chip is partitioned into a plurality of segments, a decoupling cell is arranged for each segment, and an operation failure due to a voltage drop is effectively reduced. A design approach is disclosed.
JP 2005-332979 A

  However, in the design method of the semiconductor integrated circuit using the above-described conventional technology, the decoupling cell is only arranged at an optimum position with respect to the plurality of segments separated from each other. Cannot adapt.

  Further, even if the problem of power source separation of each segment is ignored, it is necessary to newly provide a region for disposing decoupling cells, which increases the chip area.

  In view of such circumstances, the present invention eliminates the need to calculate the location of the decoupling cell over a huge amount of processing time, and allows the decoupling cell to be arranged at a position where voltage drop and noise can be effectively prevented. It is intended to provide a circuit and a design method thereof.

  The present invention provides means for solving these problems, and employs the technical configuration described below.

The present invention relates to a standard cell composed of a plurality of elements, a decoupling cell composed of a capacitive element, and first and second potential power supply lines for supplying operating power to the standard cell and the decoupling cell. And a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply lines for the first potential and the second potential,
The decoupling cell is disposed below the first power supply line or the second power supply line, and the first potential and the second potential are supplied from the first and second potential cell power supply lines, The standard cell is not arranged in the arrangement region of the decoupling cell.

The present invention relates to a standard cell composed of a plurality of elements, a decoupling cell composed of a capacitive element, and first and second potential power supply lines for supplying operating power to the standard cell and the decoupling cell. And a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply lines for the first potential and the second potential,
The decoupling cell is disposed below the first power supply wiring and the second power supply wiring, and the first potential and the second potential are supplied from the first power supply wiring and the second power supply wiring for the cell. The standard cell is not arranged in the arrangement region of the decoupling cell.

  Here, the first power supply wiring and the second power supply wiring may be mesh wiring for wiring the entire circuit like a mesh, or the power supply wiring for cells of the first potential and the second potential. The strap wiring may be wired only in the vertical direction.

  Further, one of the first potential and the second potential may be a power supply potential, and the other may be a ground potential.

The present invention also provides a standard cell composed of a plurality of elements, a decoupling cell composed of a capacitive element, and a cell having a first potential and a second potential for supplying operating power to the standard cell and the decoupling cell. A semiconductor comprising: a power supply line; a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply lines for the first potential and the second potential. In an integrated circuit design method,
The decoupling cell is disposed below the first power supply line or the second power supply line to be supplied with the first potential and the second potential, and the standard cell is disposed in a region where the decoupling cell is disposed. It is not arranged.

The present invention also provides a standard cell composed of a plurality of elements, a decoupling cell composed of a capacitive element, and a cell having a first potential and a second potential for supplying operating power to the standard cell and the decoupling cell. A semiconductor comprising: a power supply line; a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply lines for the first potential and the second potential. In an integrated circuit design method,
The decoupling cell is disposed below the first power supply wiring and the second power supply wiring, and the first potential and the second potential are supplied from the first power supply wiring and the second power supply wiring for the cell. The standard cell is not arranged in the arrangement region of the decoupling cell.

  The following effects are brought about by the present invention described above.

  It is most effective to place the decoupling cell close to a place where the voltage drop is the largest. In order to identify the place where the voltage drop is the largest, a huge amount of processing time is required, and further analysis is possible only after placement and routing. Even if the place where the voltage drop is the largest can be determined, there is no effect if the area where the decoupling cell can be arranged in the vicinity is secured and the area cannot be arranged in the vicinity.

  Therefore, the decoupling cell is arranged in advance under the first power supply wiring and the second power supply wiring in the direction perpendicular to the power supply wiring for the first potential and the second potential before performing the standard cell placement wiring. Thus, it is not necessary to analyze the optimal arrangement location of the decoupling cell over a long time, and the decoupling cell can be arranged while securing a location where the voltage drop is large.

  Further, if the voltage drop is within an allowable range after the placement and wiring, the previously placed decoupling cell can be easily removed, which can contribute to the reduction of standby current.

  Furthermore, since the mesh wiring and the strap wiring have wide power supply wiring, the wiring area is small and the wiring congestion is high. By placing the decoupling cell in this wiring congestion area in advance before placing and routing the standard cell, it becomes a placement prohibition area, the standard cell cannot be placed, it is possible to avoid wiring congestion in advance, and design is easy Can also contribute.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram showing another example of the first embodiment.

  A semiconductor integrated circuit 100 shown in FIG. 1 includes a cell power supply wiring 101 having a first potential and a cell power supply wiring 102 having a second potential, and a first potential and a second potential. The first power supply wiring 103 and the second power supply wiring 104 are arranged in a direction perpendicular to the cell power supply wiring, the standard cell 105, and the decoupling cell 106. Here, the first power supply wiring 103 is supplied with a first potential, that is, a power supply potential, and the second power supply wiring 104 is supplied with a second potential, that is, a ground potential. Of course, the first power supply wiring 103 may be supplied with the second potential, and the second power supply wiring 104 may be supplied with the first potential.

  The decoupling cell 106 is disposed below the second power supply wiring 104 and is supplied with the first potential and the second potential from the cell power supply wiring 101 for the first potential and the cell power supply wiring 102 for the second potential. The arrangement area of the standard cell 105 is an area other than the arrangement part of the decoupling cell 106.

  A semiconductor integrated circuit 110 shown in FIG. 2 includes a cell power supply wiring 111 having a first potential and a cell power supply wiring 112 having a second potential, and a first potential and a second potential. The first power supply wiring 113 and the second power supply wiring 114 are arranged in a direction perpendicular to the cell power supply wiring, the standard cell 115, and the decoupling cell 116. Here, the first power supply wiring 113 is supplied with a first potential, that is, a power supply potential, and the second power supply wiring 114 is supplied with a second potential, that is, a ground potential. The difference from the semiconductor integrated circuit 100 of FIG. 1 is that a cell is not disposed between the cell power supply lines 112 and 111 of the first potential and the second potential.

  In the semiconductor integrated circuits of FIGS. 1 and 2, the decoupling cell is disposed under the second power supply wiring, but may be under the first power supply wiring.

  Thus, the decoupling cell is disposed under the first power supply wiring and the second power supply wiring in a direction perpendicular to the power supply wiring for the first potential and the second potential cells, so that the decoupling cell takes a long time. Therefore, it is not necessary to analyze the optimal placement location, and it is possible to secure the location where the voltage drop is large and place the decoupling cell. In addition, since the standard cell is disposed outside the region where the decoupling cell is disposed, if the voltage drop is within an allowable range after the placement and wiring, the previously disposed decoupling cell can be easily removed and the standby current can be removed. Can contribute to the reduction of

The first and second power supply wirings may be mesh wirings or strap wirings.
FIG. 3 is a configuration diagram of the semiconductor integrated circuit when the first and second power supply wirings are mesh wirings. FIG. 4 is a configuration diagram of a semiconductor integrated circuit when the first and second power supply wirings are strap wirings.

First, the case where the power supply wiring is mesh wiring will be described.
As shown in FIG. 3, the semiconductor chip 201 has a plurality of connection pads 202 arranged at the peripheral end, and an integrated circuit portion is formed inside the connection pad row. FIG. 3 shows power supply wiring formed in the integrated circuit portion. First, power ring wirings 203 and 204 connected in a ring shape are arranged around the integrated circuit portion. The power supply ring wirings 203 and 204 are connected to a pad to which a power supply potential is supplied among the connection pads 202, and a first potential is supplied to the power supply ring wiring 203 and a second potential is supplied to the power supply ring wiring 204. . A plurality of power supply wirings 205 are arranged so as to cross in the horizontal direction and the vertical direction in FIG. 3 and are connected to the power supply ring wiring 203. A plurality of power supply wirings 206 are arranged so as to cross in the vertical and horizontal directions in FIG. 3 and are connected to the power supply ring wiring 204. A blank portion of the integrated circuit portion indicates a standard cell arrangement region 207. In this way, the power wiring of the mesh wiring is arranged in a mesh pattern on the integrated circuit portion of the semiconductor chip 201, and power is supplied to the entire circuit.

  FIG. 3 does not show the power supply wirings for the first and second potential cells described in FIGS. 1 and 2 for explaining the mesh wiring, but in FIG. 3, the horizontal or vertical direction is not shown. Are arranged in either direction. Therefore, the decoupling cell is disposed under the first power supply line and the second power supply line perpendicular to the cell power supply lines for the first potential and the second potential.

Next, a case where the power supply wiring is a strap wiring will be described.
As shown in FIG. 4, the semiconductor chip 301 has a plurality of connection pads 302 arranged at the peripheral end, and an integrated circuit portion is formed inside the connection pad row. FIG. 4 shows power supply wiring formed in the integrated circuit portion. First, power ring wirings 303 and 304 connected in a ring shape are arranged around the integrated circuit portion. The power supply ring wirings 303 and 304 are connected to the pad supplied with the power supply potential among the connection pads 302, and the power supply ring wiring 303 is supplied with the first potential and the power supply ring wiring 304 is supplied with the second potential. . A plurality of power supply wirings 305 are arranged in the vertical direction in FIG. 4 and connected to the power supply ring wiring 303. A plurality of power supply wirings 306 are arranged in the vertical direction and connected to the power supply ring wiring 304. A blank portion of the integrated circuit portion indicates a standard cell arrangement region 307. Thus, the power supply wiring of the strap wiring is arranged in a direction perpendicular to the integrated circuit portion of the semiconductor chip 201, and power is supplied to the entire circuit.

  4 does not show the power supply wirings for the first and second potential cells described in FIGS. 1 and 2 for explaining the strap wiring, but in FIG. 3, they are arranged in the horizontal direction. ing. Therefore, the decoupling cell is disposed under the strap power supply wiring.

  As described above, the mesh wiring and the strap wiring have a wide power supply wiring, so that the wiring area is small and the wiring congestion is high. Since a decoupling cell is arranged under the power supply wiring and this area becomes a standard cell arrangement prohibition area, the decoupling cell cannot be arranged due to wiring congestion, and the design can be facilitated.

The procedure of the method for designing the semiconductor integrated circuit of FIGS. 1 and 2 is shown in FIG.
In the method for designing a semiconductor integrated circuit according to the present embodiment, a floor plan process is performed as in a normal layout process (step S11). A layout process for the power supply wirings for the first and second potential cells is performed (step S12), and a layout process for the first and second power supply wirings is performed (step S13). Next, placement of the decoupling cell is performed (step S14). Then, the standard cells are arranged (step S15), and the process proceeds to the wiring process (step S16).

  As described above, the decoupling cell is arranged in advance under the power supply wiring that is the mesh wiring or strap wiring in the vertical direction with respect to the power supply wiring for the cell of the first potential and the second potential before the standard cell placement wiring is performed. Thus, it is not necessary to analyze the optimal arrangement location of the decoupling cell over a long time, and the decoupling cell can be arranged while securing a location where the voltage drop is large. Further, if the voltage drop is within an allowable range after the placement and wiring, the previously placed decoupling cell can be easily removed, which can contribute to the reduction of standby current. Furthermore, by placing the decoupling cell in advance before performing standard cell placement and routing, the decoupling cell placement area becomes a placement prohibited area for other cells, and the decoupling cell is placed in advance to avoid wiring congestion. This can contribute to the simplification of design.

(Second Embodiment)
FIG. 6 is a block diagram showing a second embodiment of the semiconductor integrated circuit according to the present invention, and FIG. 7 is a block diagram showing another example of the second embodiment.

  A semiconductor integrated circuit 400 shown in FIG. 6 includes a cell power wiring 401 having a first potential and a cell power wiring 402 having a second potential, and a first potential and a second potential. The first power supply wiring 403 and the second power supply wiring 404 arranged in the direction perpendicular to the cell power supply wiring, the standard cell 405, and the decoupling cell 406 are configured. Here, the first power supply wiring 403 is supplied with the first potential, that is, the power supply potential, and the second power supply wiring 404 is supplied with the second potential, that is, the ground potential.

  The decoupling cell 406 is disposed under the first power supply wiring 403 and the second power supply wiring 404 and is supplied with the first potential and the second potential. The arrangement area of the standard cell 405 is an area other than the arrangement part of the decoupling cell 406.

  The semiconductor integrated circuit 410 shown in FIG. 7 includes a cell power line 411 having a first potential and a cell power line 412 having a second potential, and a first potential and a second potential. The first power supply wiring 413 and the second power supply wiring 414 arranged in the direction perpendicular to the cell power supply wiring, the standard cell 415, and the decoupling cell 416 are configured. Here, the first power supply wiring 413 is supplied with the first potential, that is, the power supply potential, and the second power supply wiring 414 is supplied with the second potential, that is, the ground potential. A difference from the semiconductor integrated circuit 400 of FIG. 6 is that a cell is not disposed between the cell power supply wirings 412 and 411 of the first potential and the second potential.

  The design procedure of the second embodiment is the same as that shown in FIG. 5, and the power supply wiring is formed by mesh wiring or strap wiring.

  In the second embodiment, in addition to the effects of the first embodiment, a decoupling cell can be arranged under the first and second power supply wirings, so that a region where more decoupling cells can be arranged can be secured.

  It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

1 is a configuration diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention. It is a block diagram which shows the other example of 1st Embodiment. It is a block diagram of a semiconductor integrated circuit when the 1st and 2nd power supply wiring is a mesh wiring. It is a block diagram of a semiconductor integrated circuit when the 1st and 2nd power supply wiring is a strap wiring. FIG. 7 is a block diagram showing a second embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 7 is a block diagram showing another example of the second embodiment. It is a block diagram which shows 2nd Embodiment of the semiconductor integrated circuit which concerns on this invention. It is a block diagram which shows the other example of 2nd Embodiment.

Explanation of symbols

100 Semiconductor Integrated Circuit 101 First Potential Cell Power Supply Line 102 Second Potential Cell Power Supply Line 103 First Power Supply Line 104 Second Power Supply Line 105 Standard Cell 106 Decoupling Cell 109 Disk Drive 110 Semiconductor Integrated Circuit 111 First Potential Cell power wiring 112 of the second cell power wiring 113 for the second potential 113 first power wiring 114 second power wiring 115 standard cell 116 decoupling cell 201 semiconductor chip 202 connection pad 203, 204 power ring wiring 205, 206 power wiring 207 standard Cell placement region 301 Semiconductor chip 302 Connection pads 303 and 304 Power supply ring wirings 305 and 306 Power supply wiring 307 Standard cell placement region 400 Semiconductor integrated circuit 401 Power supply wire for first potential cell 402 Power supply for second potential cell Source wiring 403 First power supply wiring 404 Second power supply wiring 405 Standard cell 406 Decoupling cell 410 Semiconductor integrated circuit 411 First potential cell power supply wiring 412 Second potential cell power supply wiring 413 First power supply wiring 414 Second power supply Wiring 416 Decoupling cell

Claims (7)

A standard cell composed of a plurality of elements;
A decoupling cell comprising a capacitive element;
First and second potential cell power supply lines for supplying operating power to the standard cell and the decoupling cell;
A first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply line;
With
The decoupling cell is disposed below the first power supply line or the second power supply line, and the first potential and the second potential are supplied from the first and second potential cell power supply lines, A standard integrated circuit is not arranged in the arrangement region of the decoupling cell. A standard cell composed of a plurality of elements;
A decoupling cell comprising a capacitive element;
First and second potential cell power supply lines for supplying operating power to the standard cell and the decoupling cell;
A first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply line;
With
The decoupling cell is disposed below the first power supply wiring and the second power supply wiring, and the first potential and the second potential are supplied from the first power supply wiring and the second power supply wiring for the cell. The standard cell is not arranged in the arrangement region of the decoupling cell.   3. The semiconductor integrated circuit according to claim 1, wherein the first power supply wiring and the second power supply wiring are mesh wirings for wiring the entire circuit like a mesh.   The semiconductor integrated circuit according to claim 1, wherein the first power supply wiring and the second power supply wiring are strap wirings that are wired only in a direction perpendicular to the cell power supply wiring.   5. The semiconductor integrated circuit according to claim 1, wherein one of the first potential and the second potential is a power supply potential, and the other is a ground potential. A standard cell composed of a plurality of elements;
A decoupling cell comprising a capacitive element;
First and second potential cell power supply lines for supplying operating power to the standard cell and the decoupling cell;
A first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply lines for the first potential and the second potential;
In a method for designing a semiconductor integrated circuit comprising:
The decoupling cell is disposed below the first power supply line or the second power supply line, and the first potential and the second potential are supplied from the first and second potential cell power supply lines. The method of designing a semiconductor integrated circuit, wherein the standard cell is not arranged in an arrangement region of the decoupling cell. A standard cell composed of a plurality of elements;
A decoupling cell comprising a capacitive element;
First and second potential cell power supply lines for supplying operating power to the standard cell and the decoupling cell;
A first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied, which are perpendicular to the cell power supply lines for the first potential and the second potential;
In a method for designing a semiconductor integrated circuit comprising:
The decoupling cell is disposed below the first power supply wiring and the second power supply wiring, and the first potential and the second potential are supplied from the first power supply wiring and the second power supply wiring for the cell. The method of designing a semiconductor integrated circuit, wherein the standard cell is not arranged in an arrangement region of the decoupling cell.

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