JP2010027980A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving the voltage resistance of a junction part in source/drain regions and capable of reducing the influence of parasitic bipolar transistor characteristics. <P>SOLUTION: A low voltage resistance transistor shown in Fig.2(a) includes: a gate insulating film 15 and a first gate electrode 16 which are formed on a first region of a substrate 11 between source and drain regions 13, 14; and silicide layers 13A, 14A formed on the source and drain regions 13, 14. A high voltage resistance transistor shown in Fig.2(b) includes: a gate insulating film 25 whose film thickness is larger than that of the gate insulating film 15 and a second gate electrode 16 which are formed on a second region whose surface is removed by predetermined depth on the substrate 11 between source and drain regions 23, 24; and silicide layers 23A, 24A formed on the source and drain regions 23, 24. The predetermined depth corresponds to a difference of thickness between the gate insulating film 25 and the gate insulating film 15, and the upper surfaces of the silicide layers 23A, 24A have structure higher than an interference between the second region of the substrate 11 and the gate insulating film 25. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device including a high breakdown voltage and a low breakdown voltage MOS field effect transistor having a salicide diffusion layer, and a manufacturing method thereof.

  In a general semiconductor memory device, miniaturization is achieved by arranging and assembling a plurality of semiconductor memory circuits (memory cell array). However, circuits (row decoder, sense amplifier, etc.) for driving the semiconductor memory device are larger in size than individual semiconductor memory circuits, and thus need to be arranged around the memory cell array. At this time, since the wiring length traversing the memory cell array becomes long, a low resistance wiring that suppresses a voltage drop due to wiring resistance is required. In a semiconductor memory device, in many cases, a gate for selecting a semiconductor memory circuit is used in series. Therefore, it is advantageous to use a gate using a silicide compound having a lower resistance than a gate made of silicon material.

  In a nonvolatile semiconductor memory device using a FN tunnel current and requiring a high voltage, when a salicide compound is used for the source and drain electrodes, parasitic resistance can be reduced. However, in a MOSFET that requires a high breakdown voltage, it is necessary to avoid junction breakdown due to a high voltage by separating the gate electrode and a field oxide film such as STI (Shallow Trench Isolation) to some extent (for example, Patent Documents). 1). For this reason, when a salicide compound is formed in the diffusion layer of a MOSFET that requires high breakdown voltage, it is difficult to reduce the size of the semiconductor device.

  In a NAND flash memory which is a kind of nonvolatile semiconductor memory device, a low breakdown voltage (high performance low voltage) MOS field effect transistor (hereinafter referred to as a low breakdown voltage MOSFET) having a low breakdown voltage specification and a high breakdown voltage MOS having a high breakdown voltage specification. A field effect transistor (hereinafter referred to as a high voltage MOSFET) is required. In these transistors, it is necessary to salicide the gate electrode and the source and drain diffusion layers in order to reduce the wiring resistance. For example, the low withstand voltage MOSFET is a transistor used at an applied voltage of 10 V or less, and the high withstand voltage MOSFET is a transistor used at an applied voltage of 40 V or less.

When the high voltage MOSFET and the low voltage MOSFET are formed on the same semiconductor substrate, it is necessary to salicide the high voltage MOSFET and the low voltage MOSFET simultaneously after processing the gate electrode. In a MOSFET, a self-alignment technique cannot be used, and dedicated processes increase. Further, in order to use the self-alignment technique, it is necessary to prepare a sidewall oxide film using a step of STI that is sufficiently higher than the silicon interface of the MOSFET, so that the flatness deteriorates before the electrode is processed. End up.
JP 2007-201494 A

  An object of the present invention is to provide a semiconductor device that can improve the breakdown voltage of the junction in the source region and the drain region and can reduce the influence of parasitic bipolar transistor characteristics, and a method of manufacturing the same.

The semiconductor device according to an embodiment of the present invention is a semiconductor device having a low breakdown voltage transistor and a high breakdown voltage transistor on a semiconductor substrate, wherein the low breakdown voltage transistor includes a source region formed in a first region of the semiconductor substrate, and the source A drain region formed in the first region of the semiconductor substrate spaced apart from the region; a first gate insulating film formed on the first region between the source region and the drain region; A first gate electrode formed on one gate insulating film; and a first silicide layer formed on the first gate electrode, the source region, and the drain region, wherein the high breakdown voltage transistor includes the semiconductor A second region from which the surface of the substrate has been removed to a predetermined depth, a source region formed in the second region, and a second region separated from the source region. A drain region, a second gate insulating film formed on the second region between the source region and the drain region, and having a thickness greater than that of the first gate insulating film; and on the second gate insulating film A second silicide layer formed on the second gate electrode, the source region, and the drain region; and the predetermined depth is a thickness of the second gate insulating film. And the thickness of the first gate insulating film,
The upper surface of the second silicide layer is higher than an interface between the second region of the semiconductor substrate and the second gate insulating film.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a low breakdown voltage transistor and a high breakdown voltage transistor on a semiconductor substrate; A step of forming a recess having a predetermined depth removed from the substrate and a protrusion maintaining the height of the surface of the semiconductor substrate, a step of forming a first insulating film in the recess, and a region for forming the low breakdown voltage transistor Forming a second insulating film on the semiconductor substrate and forming the second insulating film on the first insulating film and on the convex portion in a region where the high breakdown voltage transistor is to be formed; and the low breakdown voltage transistor Forming a device isolation region in a region for forming the high breakdown voltage transistor and a region for forming the high breakdown voltage transistor, a region for forming the low breakdown voltage transistor, and the high breakdown voltage transistor Forming a conductive film to be a gate electrode on the second insulating film in a region where a transistor is to be formed; a region in which the low breakdown voltage transistor is to be formed; a region in which the high breakdown voltage transistor is to be formed; Etching the two insulating films to form gate electrodes, exposing the source region and the drain region of the first region, and the convex portion of the second region; and on the gate electrode, Forming a metal film on the source region, the drain region, and the convex portion; and reacting the metal film with the gate electrode, the source region, the drain region, and the convex portion to form a silicide layer Forming the step.

  According to the present invention, it is possible to provide a semiconductor device capable of improving the breakdown voltage of the junction in the source region and the drain region and reducing the influence of the parasitic bipolar transistor characteristics, and a method for manufacturing the same.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  As a semiconductor device according to an embodiment of the present invention, a NAND flash memory which is a kind of nonvolatile semiconductor memory device will be described as an example. In the peripheral circuit of the NAND flash memory, the low breakdown voltage MOSFET and the high breakdown voltage MOSFET are formed on the same semiconductor substrate. In order to reduce the wiring resistance in these transistors, the gate electrode, the source diffusion layer, and the drain of the transistor It is necessary to salicide the diffusion layer.

  FIG. 1A is a plan view showing the configuration of the low voltage MOSFET according to the embodiment, and FIG. 1B is a plan view showing the configuration of the high voltage MOSFET. 2A and 2B are cross-sectional views of the low breakdown voltage MOSFET and the high breakdown voltage MOSFET taken along the line 2a-2b shown in FIG.

  First, the structure of the low breakdown voltage MOSFET will be described with reference to FIG.

  As shown in FIG. 2A, an element isolation region 12 is formed in the silicon semiconductor substrate 11. The element isolation region 12 is made of, for example, STI (Shallow Trench Isolation) in which a silicon oxide film or the like is embedded in a trench formed in the semiconductor substrate 11, and is formed between low-voltage MOSFETs (elements) formed on the semiconductor substrate 11. An element region in which the low breakdown voltage MOSFET is formed is determined by electrical isolation.

  A source region (diffusion layer) 13 and a drain region (diffusion layer) 14 having an LDD (lightly doped diffusion) structure are formed separately on the surface region of the semiconductor substrate 11 in the element region. Salicide layers (silicide compound layers) 13A and 14A are formed in the upper layer portions of the source region 13 and the drain region 14, respectively.

  A first gate insulating film (for example, silicon oxide film) 15 is formed on the semiconductor substrate 11 between the source region 13 and the drain region 14. A gate electrode (for example, a polysilicon film) 16 is formed on the first gate insulating film 15. The gate electrode 16 includes a salicide layer. Further, a gate sidewall insulating film 17 is formed on the sidewall of the gate electrode 16. The gate sidewall insulating film 17 is made of, for example, a film including at least one of a silicon oxide film and a silicon nitride film.

  A barrier insulating film 18 that protects the salicide layer is formed on the gate electrode 16, the source region 13, the drain region 14, and the element isolation region 12. Interlayer insulating films 19 and 20 are formed on the barrier insulating film 18. In the barrier insulating film 18 and the interlayer insulating films 19 and 20 on the salicide layers 13A and 14A, buried contacts 21 electrically connected to the salicide layers 13A and 14A are formed. Further, a wiring 31 is formed on the contact 21.

  Next, the structure of the high voltage MOSFET will be described with reference to FIG.

  As shown in FIG. 2B, an element isolation region 12 is formed in the silicon semiconductor substrate 11. The element isolation region 12 is made of, for example, STI, and electrically isolates and isolates the high breakdown voltage MOSFETs (elements) formed on the semiconductor substrate 11 to define an element region in which the high breakdown voltage MOSFET is formed.

  A source region 23 and a drain region 24 having an LDD (lightly doped diffusion) structure are formed separately on the surface region of the semiconductor substrate 11 in the element region. Salicide layers (silicide compound layers) 23A and 24A are formed in the upper layer portions of the source region 23 and the drain region 24, respectively.

  An insulating film (for example, a silicon oxide film) 25A is formed on the semiconductor substrate 11 between the source region 23 and the drain region 24, and a first gate insulating film 15 is formed on the insulating film 25A. . The second gate insulating film 25 is configured by a laminated structure of the insulating film 25A and the first gate insulating film 15. A gate electrode (for example, a polysilicon film) 16 is formed on the second gate insulating film 25. The gate electrode 16 includes a salicide layer. Further, a gate sidewall insulating film 17 is formed on the sidewall of the gate electrode 16. As described above, the gate sidewall insulating film 17 is made of, for example, a film including at least one of a silicon oxide film and a silicon nitride film.

  On the source region 23 and the drain region 24, an insulating film 25A having an opening is formed. In the openings of these insulating films 25A, salicide layers (silicide compound layers) 23A and 24A, and part of the source region 23 and the drain region 24 are formed. More specifically, a salicide layer 23A is formed in the opening of the insulating film 25A on the source region 23 from the height of the upper surface of the insulating film 25A to the middle of the thickness of the insulating film 25A, and below the salicide layer 23A. A source region 23 is formed. In the opening of the insulating film 25A on the drain region 24, a salicide layer 24A is formed from the height of the upper surface of the insulating film 25A to the middle of the thickness of the insulating film 25A, and the drain region 24 is formed under the salicide layer 24A. Is formed.

  A barrier insulating film 18 that protects the salicide layer is formed on the gate electrode 16, the salicide layers 23 </ b> A and 24 </ b> A, and the element isolation region 12. Interlayer insulating films 19 and 20 are formed on the barrier insulating film 18. In the barrier insulating film 18 and the interlayer insulating films 19 and 20 on the salicide layers 23A and 24A, buried contacts 21 electrically connected to the salicide layers 23A and 24A are formed. Further, a wiring 31 is formed on the contact 21.

  Next, a manufacturing method of the low breakdown voltage MOSFET and the high breakdown voltage MOSFET according to the embodiment of the present invention will be described.

  3 to 9 are cross-sectional views of each process showing the method of manufacturing the low breakdown voltage MOSFET and the high breakdown voltage MOSFET of the embodiment. (A) of each figure is sectional drawing of the manufacturing process of low voltage | pressure-resistant MOSFET, (b) of each figure is sectional drawing of the manufacturing process of high voltage | pressure-resistant MOSFET.

  First, in the region where the low breakdown voltage MOSFET is formed, the semiconductor substrate 11 is covered with a resist film 32 as shown in FIG. On the other hand, in the region where the high voltage MOSFET is to be formed, as shown in FIG. 3B, a resist film 32 is formed on the semiconductor substrate 11 and the surface of the semiconductor substrate 11 is covered with the resist film 32. The other portions are etched, for example, by RIE (Reactive Ion Etching) while leaving the portion 11A. The predetermined portion (convex portion) 11A is a region where a salicide layer is formed in a later step. In other words, the surface of the semiconductor substrate in the region where the high voltage MOSFET is formed is set lower than the surface of the semiconductor substrate in the region where the low voltage MOSFET is formed. At this time, in the region (concave portion) where the high breakdown voltage MOSFET is formed, the portion (convex portion) that will become the salicide layer of the source and drain regions in the subsequent process is masked by the resist film 32 so as not to be etched.

  Next, after removing the resist film 32, as shown in FIGS. 4A and 4B, an insulating film (silicon oxide film) 25A is formed on the semiconductor substrate 11 by, for example, a thermal oxidation method. At this time, the thickness of the insulating film 25A is approximately the same as the height of the predetermined portion 11A formed in the region where the high voltage MOSFET is formed. Thereafter, in the region where the low breakdown voltage MOSFET is formed, as shown in FIG. 4A, the insulating film 25A on the semiconductor substrate 11 is removed by, for example, RIE without covering with a resist film. At this time, in the region where the high breakdown voltage MOSFET is formed, as shown in FIG. 4B, the insulating film 25A is protected by the resist film 33 so that the insulating film 25A is not etched by RIE, for example. That is, only the insulating film 25A formed in the region for forming the low breakdown voltage MOSFET is removed.

  Thereafter, after the resist film 33 is peeled off, an insulating film (silicon oxide film) 15 is formed on the semiconductor substrate 11 by, eg, thermal oxidation in the region where the low breakdown voltage MOSFET is to be formed, as shown in FIG. . At this time, in the region where the high voltage MOSFET is to be formed, as shown in FIG. 5B, the insulating film 15 is formed on the insulating film 25A and the predetermined portion 11A of the semiconductor substrate 11 by the thermal oxidation method. In the region where the low breakdown voltage MOSFET is formed, the insulating film 15 constitutes the gate insulating film of the low breakdown voltage MOSFET, and in the region where the high breakdown voltage MOSFET is formed, the laminated film of the insulating film 25A and the insulating film 15 is the high breakdown voltage MOSFET. A gate insulating film is formed.

  Next, as shown in FIGS. 6A and 6B, element isolation regions 12 such as STI are formed in the semiconductor substrate 11, respectively. Subsequently, a polysilicon film 16 is formed on the insulating film 15 by, for example, CVD (Chemical Vapor Deposition). Thereafter, as shown in FIGS. 7A and 7B, the gate electrode 16 is formed by patterning the polysilicon film 16 by RIE, for example. Subsequently, the insulating film 15 other than under the gate electrode 16 is removed. Further, impurity ions are introduced into the semiconductor substrate on both sides of the gate electrode 16 by ion implantation to form the source region 13, the drain region 14, the source region 23, and the drain region 24.

  Subsequently, an insulating film 17 is formed on the gate electrode 16, the source region 13, the drain region 14, the source region 23, and the drain region 24 by, for example, CVD. Then, the insulating film 17 is etched by RIE, leaving the gate sidewall insulating film 17 only on the side surface of the gate electrode 16.

  At this time, as shown in FIG. 7B, since openings are formed in the insulating film 25A on the source region 23 and the drain region 24, the silicon substrate (predetermined portion 11A) for forming the salicide layer is formed. Exposed. Here, for example, in a normally used manufacturing method, as shown in FIG. 14B, after forming the gate sidewall insulating film 17 in the region where the high voltage MOSFET is formed, the resist film 36 is formed by photolithography. The step of forming and etching the insulating film 25A on the source region 23 and the drain region 24 to form an opening for forming the salicide layer is necessary. However, in the manufacturing method of this embodiment, as described above, when the formation of the gate sidewall insulating film 17 is completed, the silicon substrate 11 is already exposed from the opening of the insulating film 25A on the source region 23 and the drain region 24. Therefore, the process described above is not necessary and the process can be reduced.

  Thereafter, as shown in FIGS. 8A and 8B, a metal which is a reaction material for forming a salicide layer on the gate electrode 16, the source regions 13 and 23 and the drain regions 14 and 24. A film 34, for example, nickel (Ni) or cobalt (Co) is deposited. Subsequently, the semiconductor substrate 11 shown in FIGS. 8A and 8B is subjected to heat treatment, and the silicon and metal film 34 of the gate electrode 16, the source regions 13 and 23, and the drain regions 14 and 24 are formed. React. Then, in the region where the unreacted metal film 34 is removed and the low breakdown voltage MOSFET is formed, the salicide layers 16 and 13A are formed on the gate electrode 16, the source region 13, and the drain region 14, as shown in FIG. 14A, and in the region where the high breakdown voltage MOSFET is formed, as shown in FIG. 9B, the salicide layers 23A, 23A are formed in the openings of the insulating film 25A on the source region 23 and the drain region 24 and on the gate electrode 16. 24A and 16 are formed.

  Next, as shown in FIGS. 2A and 2B, the salicide layer is protected on the salicide layer on the gate electrode 16, the source regions 13 and 23, and the drain regions 14 and 24. A barrier insulating film 18 is formed. Subsequently, interlayer insulating films 19 and 20 are formed, and contact holes are formed in the interlayer insulating films 19 and 20 and the barrier insulating film 18 on the salicide layers 13A, 14A, 23A, and 24A. Then, a buried contact 21 is formed by embedding a metal material in the contact hole. Further, a wiring 31 is formed on the embedded contact 21. Thus, the semiconductor device of this embodiment is manufactured.

  Next, with reference to FIG. 10 and FIG. 11, the detailed structure and effect of the high voltage MOSFET according to the embodiment will be described.

  FIG. 10 is an enlarged cross-sectional view of a portion where the salicide layer is formed in the high voltage MOSFET shown in FIG. FIG. 11 is an enlarged cross-sectional view of a portion where a salicide layer is formed in a high voltage MOSFET as a comparative example. FIG. 12 is a circuit diagram of the high voltage MOSFET according to the embodiment, and FIG. 13 is a diagram showing current-voltage characteristics between the source and drain in the high voltage MOSFET.

  In this embodiment, as described above, the depth (bottom surface) of the salicide layers 23A and 24A is obtained by leaving the silicon substrate region to be the salicide layer on the source region 23 and the drain region 24 in advance and digging out other regions. And the depth (bottom surface) of the source region 23 and the drain region 24 are formed to be large. As a result, the breakdown voltage against high voltage ((1) in FIG. 13) at the junction between the source region 23 and the drain region 24 can be improved. That is, in FIG. 10, the distance obtained by subtracting the thickness Xj2 of the salicide layer 24A from the thickness Xj3 of the drain region 24 is the distance obtained by subtracting the thickness Xj2 of the salicide layer 35A from the thickness Xj1 of the drain region 35 in FIG. Since it becomes larger than that, the breakdown voltage of the junction between the drain region 24 and the silicon substrate 11 can be improved. In other words, since the bottom surface of the salicide layer 24A is formed above the interface between the silicon substrate 11 and the gate insulating film 25A, the depth of the salicide layer 24A and the source / drain diffusion layer (LDD diffusion layer) are increased. The difference from the depth is increased, and the breakdown voltage of the junction when a high voltage is applied can be improved.

  Further, the distance D1 between the gate electrode 16 and the salicide layer 24A is extended, and the distance along the bottom surface of the gate insulating film 25 can be increased between the salicide layers 23A and 24A arranged on both sides so as to sandwich the gate electrode 16 therebetween. Therefore, it is possible to suppress the occurrence of punch-through and improve the characteristics of the parasitic bipolar transistor ((2) in FIG. 13).

  In FIG. 13, A is the characteristic of the comparative example, and B is the characteristic of the present embodiment. Thereby, it turns out that the characteristic is improved in the high voltage | pressure-resistant MOSFET of embodiment.

  Further, since the portions on the salicide layers 23A and 24A where the contacts 21 are formed are planarized, the formation of the contacts 21 and the formation of the electrode wirings are facilitated. Further, in the comparative example, as shown in FIG. 11, the barrier insulating film 18 is formed so as to enter the opening of the insulating film 25A on the salicide layer 35A, but in this embodiment, as shown in FIG. Since the salicide layer 24A is formed from the position of the upper surface of the insulating film 25A to the middle of the thickness of the insulating film 25A in the portion, the diameter H2 of the opening can be made smaller than the diameter H1. Thereby, an area required for forming one high voltage MOSFET can be reduced. That is, the diameter of the opening for forming the salicide layer can be reduced, thereby reducing the transistor size.

  The embodiment described above is not the only embodiment, and various embodiments can be formed by changing the configuration or adding various configurations.

It is a top view which shows the structure of the semiconductor device of embodiment of this invention. 2 is a cross-sectional view taken along line 2a-2b of the semiconductor device of the embodiment shown in FIG. It is sectional drawing of the 1st process which shows the manufacturing method of the semiconductor device of embodiment. It is sectional drawing of the 2nd process which shows the manufacturing method of the semiconductor device of embodiment. It is sectional drawing of the 3rd process which shows the manufacturing method of the semiconductor device of embodiment. It is sectional drawing of the 4th process which shows the manufacturing method of the semiconductor device of embodiment. It is sectional drawing of the 5th process which shows the manufacturing method of the semiconductor device of embodiment. It is sectional drawing of the 6th process which shows the manufacturing method of the semiconductor device of embodiment. It is sectional drawing of the 7th process which shows the manufacturing method of the semiconductor device of embodiment. FIG. 3 is an enlarged cross-sectional view of a portion where a high-voltage MOSFET salicide layer is formed in the semiconductor device of the embodiment shown in FIG. 2. It is sectional drawing to which the part in which the salicide layer in the high voltage | pressure-resistant MOSFET as a comparative example was formed was expanded. It is a circuit diagram of the high voltage MOSFET of the embodiment. It is a figure which shows the current-voltage characteristic between the source-drain in the high voltage | pressure-resistant MOSFET of embodiment. It is sectional drawing of the process which shows the manufacturing method of the semiconductor device as a comparative example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Silicon semiconductor substrate, 12 ... Element isolation region, 13 ... Source region (diffusion layer), 14 ... Drain region (diffusion layer), 13A, 14A ... Salicide layer (silicide compound layer), 15 ... 1st gate insulating film , 16 ... gate electrode, 17 ... gate sidewall insulating film, 18 ... barrier insulating film, 19, 20 ... interlayer insulating film, 21 ... buried contact, 23 ... source region (diffusion layer), 24 ... drain region (diffusion layer), 23A, 24A ... salicide layer (silicide compound layer), 25A ... insulating film, 25 ... second gate insulating film, 31 ... wiring.

Claims (4)

In a semiconductor device having a low breakdown voltage transistor and a high breakdown voltage transistor on a semiconductor substrate,
The low breakdown voltage transistor is:
A source region formed in a first region of the semiconductor substrate;
A drain region formed in the first region of the semiconductor substrate and spaced apart from the source region;
A first gate insulating film formed on the first region between the source region and the drain region;
A first gate electrode formed on the first gate insulating film;
A first silicide layer formed on the first gate electrode, on the source region and on the drain region;
The high voltage transistor is
A second region in which a surface of the semiconductor substrate is removed to a predetermined depth;
A source region formed in the second region;
A drain region formed in the second region apart from the source region;
A second gate insulating film formed on the second region between the source region and the drain region and thicker than the first gate insulating film;
A second gate electrode formed on the second gate insulating film;
A second silicide layer formed on the second gate electrode, the source region, and the drain region;
The predetermined depth corresponds to a difference between the thickness of the second gate insulating film and the thickness of the first gate insulating film,
An upper surface of the second silicide layer is higher than an interface between the second region of the semiconductor substrate and the second gate insulating film.   The semiconductor device according to claim 1, wherein a thickness of the second silicide layer is thinner than the predetermined depth. In a method for manufacturing a semiconductor device in which a low breakdown voltage transistor and a high breakdown voltage transistor are formed on a semiconductor substrate,
Forming a recess removed from the surface of the semiconductor substrate by a predetermined depth and a protrusion maintaining the height of the surface of the semiconductor substrate in a region for forming the high breakdown voltage transistor;
Forming a first insulating film in the recess;
A second insulating film is formed on the semiconductor substrate in a region where the low breakdown voltage transistor is formed, and the second insulating film is formed on the first insulating film and in the convex portion in the region where the high breakdown voltage transistor is formed. Forming, and
Forming an element isolation region in a region for forming the low breakdown voltage transistor and a region for forming the high breakdown voltage transistor;
Forming a conductive film to be a gate electrode on the second insulating film in the region for forming the low breakdown voltage transistor and the region for forming the high breakdown voltage transistor;
The conductive film and the second insulating film in the region for forming the low breakdown voltage transistor and the region for forming the high breakdown voltage transistor are etched to form gate electrodes, respectively, and the source region and the first region in the first region Exposing the drain region and the convex portion of the second region;
Forming a metal film on the gate electrode, on the source region, on the drain region, and on the protrusion;
Forming a silicide layer by reacting the metal film with the gate electrode, the source region, the drain region, and the protrusion;
A method for manufacturing a semiconductor device, comprising:   4. The method of manufacturing a semiconductor device according to claim 3, wherein the thickness of the silicide layer formed on the convex portion is thinner than the depth of the concave portion removed from the surface of the semiconductor substrate by a predetermined depth. .

Images