JP2010017336A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine without having unnecessary waiting time or without execution of a lottery processing caused by malfunction. <P>SOLUTION: In the game machine, a CPU executes the lottery processing based on a winning switch signal SG of a game ball to determine whether a game state advantageous to a player should be generated or not. A random number generating circuit for generating a random number value RND to be used in the lottery processing includes counters 43 and 44 to be updated circularly as a counting clock Φ is received; a flip-flop 42 for obtaining and holding the wining switch signal SG synchronously with the falling edge of the counting clock Φ when receives the winning switch signal SG; latch circuits 45 and 46 for synchronizing the falling edge of the winning switch signal SG received from the flip-flop 42 on condition that a control signal STL is at a permissible level, and obtaining and holding the output data from the counters 43 and 44 as random number values; and a flip-flop 60 for changing the level of the control signal STL to a prohibition level after the latch circuits 45 and 46 obtain the random number values. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a ball ball game machine or a slot machine that generates a big hit state by a lottery process caused by a game operation, and more particularly to a game machine that does not execute a lottery process due to a malfunction.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

  However, in actuality, whether or not the big hit state is determined in advance by the big hit lottery process executed at the time of winning the game ball, and the symbol display unit performs a symbol variation operation exclusively to enliven the player Yes. In the jackpot lottery process, for example, the output value of a random number generation circuit configured in hardware is used as a random number value for jackpot determination, and is compared with the jackpot winning value to determine whether or not the jackpot state.

The random number generation circuit typically has a circuit configuration as shown in FIG. 10A, and includes an oscillation circuit 71 that generates a count clock Φ, a counter 72 that cyclically counts the count clock Φ, and a counter 72. And a latch circuit 73 that temporarily holds the output (for example, Patent Document 1).
Japanese Patent Application No. 2007-337989

  In this type of random number generation circuit, when the detection switch SW provided at the symbol start port detects the passing of the game ball, the winning switch signal SG rises to the H level. It is supplied to the clock terminal CK of the latch circuit 73 and the input port 70 of the one-chip microcomputer MIC. Therefore, when the winning switch signal SG rises to the H level, the count value of the counter 72 at that moment is temporarily held in the latch circuit 73.

  On the other hand, the one-chip microcomputer MIC grasps the ON state (H level) of the winning switch signal SG based on the output of the input port 70, and acquires the count value held in the latch circuit 73 at that time as a random value. Yes. Specifically, for example, as shown in FIG. 10B, the data of the input port 70 is input at regular intervals (ST70), and if the input value is H level (ST71), the previous timing Is checked (ST72).

  If the old data is at the L level, the winning switch signal SG has risen. Therefore, after the winning flag FLG is set to 1 (ST73), the input data is saved (ST75). On the other hand, when the input data is at the L level (ST71), and when the input data is at the H level and the old data is also at the H level (ST72), the winning flag FLG is reset to zero (ST74). ).

  By repeatedly executing such processing at short time intervals, the rising edge of the winning switch signal SG can be reliably detected. Then, on the condition that the winning flag FLG is 1, the holding value of the latch circuit 73 is acquired (ST77), and the big hit lottery process is executed to determine whether or not the big hit state is set (ST78).

  However, in the above-described invention, there is a possibility that repeated big hit lottery processing is executed due to ringing of the winning switch signal SG or the like. That is, as shown in FIG. 10C, when the winning switch signal SG vibrates, the big hit lottery process may be executed twice even though only one game ball has passed through the symbol start opening. .

  In order to avoid such a situation, the output of the detection switch SW is pulled up to 12V and supplied to the buffer circuit BUF, and the winning switch signal SG is output as long as it does not exceed the comparison voltage Vr set in the buffer circuit BUF. Although it is configured so that the level does not change, it is still not enough as a countermeasure. As a countermeasure, it may be possible to repeat the process of step ST70 until the data of the input port 70 is sufficiently stabilized, but the waiting time is wasted.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that does not execute a lottery process due to a malfunction without providing useless waiting time.

  In order to achieve the above object, according to the present invention, whether or not the CPU executes a lottery process to generate a gaming state advantageous to the player based on a sensor signal indicating the occurrence of a predetermined gaming operation. A random number generation circuit that generates a random number value to be used in the lottery process, a counter that is cyclically updated in response to a count clock, and a sensor signal that receives the sensor signal, The counter storage data is synchronized with the edge of the output signal of the detection storage circuit on the condition that the detection storage circuit holds and outputs this in synchronization with the edge and the control signal is at the permission level. A latch circuit that acquires and holds the random number value, and a control circuit that changes the control signal from a permission level to a prohibition level after the latch circuit acquires the random number value. There.

  In the present invention, after the latch circuit acquires the output data of the counter, the control circuit changes the control signal from the permission level to the prohibition level, so even if the sensor signal vibrates, the counter output data is repeatedly acquired. There is no fear of being done. In addition, it is not necessary to provide a waiting time until the vibration of the sensor signal ends. The present invention is preferably applied to a ball game machine and a slot machine.

  It is preferable that when the CPU acquires the random number value held by the latch circuit, the control circuit returns the control signal of the prohibited level to the permitted level. By adopting such a configuration, it is possible to eliminate reading out of the sensor signal only by the CPU quickly acquiring the output data of the counter.

  It is preferable that the counter updates the counter value in synchronization with the first edge of the counting clock, while the detection storage circuit holds the sensor signal in synchronization with the second edge of the counting clock. . In this case, the counter value acquired by the latch circuit is a stable value after the update is reliably completed.

  The counting clock is preferably generated by dividing the basic clock by two. In this case, since the duty ratio of the counting clock is 50%, the operation of the latch circuit is further stabilized.

  In the present invention, it is preferable that a logic gate for receiving the output signal of the detection memory circuit and the control signal output from the control circuit is provided, and the output of the logic gate is supplied to the latch circuit. . Preferably, the control circuit is constituted by a flip-flop that receives the output signal of the logic gate by inverting the logic and stores a fixed value in synchronization with an edge of the output signal. The fixed value is typically at the H level, and the flip-flop is preferably a D-type flip-flop.

  The control circuit is preferably provided with a clear terminal for forcibly resetting its output value. The clear terminal is preferably activated when the CPU acquires the output data of the counter held by the latch circuit. The clear terminal of the logic circuit is preferably activated at the time of power reset together with the clear terminal of the counter and the detection memory circuit.

  The output data of the latch circuit is effectively acquired by the CPU via a buffer circuit having three states. The three states are an H level state, an L level state, and an open state (Hi impedance state).

  In addition, it is effective that the random number generation circuit is incorporated in a one-chip microcomputer together with the CPU. In this case, the effect on crime prevention is very high.

  According to the above-described present invention, it is possible to prevent malfunction related to the lottery process without providing useless waiting time.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Is arranged. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start port 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, it is opened and closed. The claw 15a is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM is provided with a power supply board 20 that receives AC 24V and outputs various DC voltages, system reset signals (power reset signals) SYS, and the like, and a main control board 21 that plays a central role in game control operations. And an effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the main control board 21, and a liquid crystal that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22. The control board 23, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and the game ball is fired in response to the player's operation. The launch control board 25 is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is set to the main board relay board 28. Is transmitted to the payout control board 24 via.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supply, DC12V, and DC32V received from the power board 20 to the main control unit 21 as they are. Similarly, the power supply relay board 30 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supply, which are received by the main control unit 21. Directly with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputers of the respective control units 21 to 24 by this power supply reset signal. The other IC elements are reset in power supply.

  The RAM clear signal DEL received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Therefore, it has a value corresponding to the ON / OFF state of the initialization switch SW operated by the attendant.

  The voltage drop signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal, each control unit 21, In 24, a necessary termination process is started prior to a power failure or business termination. The backup power source is a DC 5V DC power source that retains data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power source 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, as described above, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23 via the power relay board 30 and the effect interface board 27, and other controls are performed. The power supply reset operation is realized at a timing substantially synchronized with the units 21 and 24.

  As illustrated, the main control unit 21 transmits a control command CMD "to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 receives a prize ball indicating a payout operation of the game ball. A count signal and a status signal CON relating to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The switch signal includes a winning switch signal SG transmitted from the symbol start port 15 to the main control unit 21.

  FIG. 4 is a circuit diagram showing, in particular, a random number generation circuit in the circuit configuration of the main control unit 21. This random number generation circuit generates a random value RND based on a winning switch signal SG received from the game board relay board 29 when a game ball wins the symbol start port 15. It is built in the one-chip microcomputer 21A.

  As shown in the figure, the random number generation circuit includes an oscillation circuit 40 that generates a clock pulse of frequency f, a first flip-flop 41 that receives an output pulse of the oscillation circuit 40 at a clock terminal CK, and a Q-bar output of the first flip-flop. The second flip-flop 42 received at the clock terminal CK, the two counters 43 and 44 that receive the Q output of the first flip-flop and execute the counting operation, and the outputs of the first and second counters 43 and 44, respectively. The first and second latch circuits 45, 46, the first and second buffer circuits 47, 48 disposed between the two latch circuits 45, 46 and the CPU data bus, and the ON of the winning switch signal SG A winning storage circuit HIT that stores the state as a winning detection signal DET is mainly configured.

  Here, the winning memory circuit HIT is configured around the third flip-flop 60, the first and second AND gates 61 and 62, the NOT gate 63, and the third buffer circuit 64.

  The first to third flip-flops 41, 42, and 60 are all formed of D-type flip-flops. When a signal supplied to the clock terminal CK rises, data at the D input terminal at that time is stored. And output to the Q output terminal. When an L level signal is supplied to the clear terminal CLR, the Q output is forcibly set to the L level, while the Q bar output is set to the H level.

  Since the power reset signal SYS output from the power supply board 20 is directly supplied to the clear terminals CLR of the first and second flip-flops 41 and 42, the Q output terminal is automatically set to the L level when the power is turned on. It becomes.

  The first flip-flop 41 has its Q-bar output fed back to its D input terminal. Therefore, the first flip-flop 41 functions as a divide-by-2 circuit for the oscillation circuit 40, and a clock pulse having a duty ratio of 50% and a frequency f / 2 is output from its Q output terminal. In this embodiment, this clock pulse becomes the count clock Φ supplied to the first counter 43. It should be noted that the logically inverted count clock Φbar is output from the Q bar output terminal of the first flip-flop 41.

  The second flip-flop 42 receives the winning switch signal SG at the D input terminal. The clock terminal CK receives a logically inverted count clock Φbar. Therefore, the winning switch signal SG is stored and output to the Q output terminal at the timing when the counting clock Φ bar rises. This output signal (latch signal) LT is supplied to the winning memory circuit HIT.

  The two counters 43 and 44 are binary counters having 8-bit output terminals Q0 to Q7. The first counter 43 receives the count clock Φ output from the first flip-flop 41 at the clock terminal CK, and the second counter 44 receives the Q7 output of the first counter at the clock terminal CK and executes the count operation. is doing. Therefore, the two counters 43 and 44 output any numerical value of 0000H to FFFFH updated in synchronization with the rising edge of the count clock Φ. Here, H means a hexadecimal number.

  Since the power reset signal SYS output from the power supply board 20 is directly supplied to the clear terminals CLR of the counters 43 and 44, the outputs of the counters 43 and 44 are automatically reset to 0000H when the power is turned on. The

  The first and second latch circuits 45 and 46 are configured to be equivalent to, for example, 74825, and include eight D-type flip-flops. When the signal supplied to the clock terminal CK of the latch circuits 45 and 46 rises, each 8-bit data supplied from the counters 43 and 44 at that time is stored and output as a random value RND. As illustrated, the output of the first AND gate 61 is supplied to the clock terminal CK.

  The first and second buffer circuits 47 and 48 have a circuit configuration equivalent to a general-purpose bus buffer such as 74244. When the CPU receives L level chip select signals CS1 and CS2 at the OE (output enable) terminal, Each 8-bit data (random value RND) received from the latch circuits 45 and 46 is output. As shown, the chip select signal CS2 is supplied to the input terminal of the second AND gate 62 together with the OE terminal of the buffer circuit 48. The buffer circuits 47 and 48 are tristate buffers, and when the OE terminal is at the H level, the output terminal is in the HiZ state.

  The Q output of the second flip-flop 42 and the Q-bar output of the third flip-flop 60 are supplied to the input terminal of the first AND gate 61 constituting the winning memory circuit HIT. The Q output of the second flip-flop 42 is a latch signal LT, and the Q-bar output of the third flip-flop 60 is a control signal CTL. Note that the latch signal LT and the control signal CTL are pulled up to the H level.

  The output of the first AND gate 61 is supplied to the clock terminal CK of the first and second latch circuits 45 and 46, and is also supplied to the clock terminal CK of the third flip-flop 60 via the NOT gate 63. Yes. When a signal received at its clock terminal CK rises, the latch circuits 45 and 46 and the third flip-flop 60 perform a latch operation for storing data supplied to each input terminal therein. Therefore, the latch circuits 45 and 46 execute the latch operation at the rising timing of the output signal of the first AND gate 61, while the third flip-flop 60 executes the latch operation at the falling timing of the output signal of the first AND gate 61. To do. However, since the inverted latch signal LT bar is supplied to the clock terminal CK of the third flip-flop 60 via the NOT gate 63, the third flip-flop 60 is latched behind the latch operation of the latch circuits 45 and 46. Operate.

  An H level voltage Vcc is fixedly supplied to the D input terminal of the third flip-flop 60. The Q output of the third flip-flop 60 is supplied to the buffer circuit 64. The Q output of the third flip-flop 60 means the winning detection signal DET.

  The buffer circuit 64 has a circuit configuration equivalent to a general-purpose bus buffer such as 74244. When the L-level chip select signal CS3 is received from the CPU at the OE terminal, the buffer circuit 64 receives 1-bit data (from the third flip-flop 60). A winning detection signal DET) is output. Note that the buffer circuit 64 is also a three-state buffer.

  A chip select signal CS2 and a power reset signal SYS are supplied to the input terminal of the second AND gate 62. The output of the second AND gate 62 is supplied to the clear terminal CLR of the third flip-flop 60. Therefore, when either or both of the chip select signal CS2 and the power reset signal SYS become L level, the Q output of the third flip-flop 60 becomes L level and the Q bar output becomes H level.

  However, the power reset signal SYS is constantly at the H level after the game machine has started to operate normally, and the chip select signal CS2 is H except for the data read timing at which the data in the buffer circuit 48 is acquired by the CPU. Is a level. Accordingly, the Q-bar output (control signal CTL) of the third flip-flop 60 is maintained at the H level even after the third flip-flop 60 is cleared to the H level when the power is turned on.

  In such an initial state, when the winning switch signal SG is turned on, the Q bar output of the third flip-flop 60 changes to L level at the timing when the latch signal LT falls, and until the data read timing of the buffer circuit 48, Maintain that state. On the other hand, after the Q bar output (control signal CTL) of the third flip-flop 60 returns to the H level at the data read timing of the buffer circuit 48, the H level is maintained.

  FIG. 5 is a time chart showing waveforms of respective parts of the random number generation circuit described above. As shown in FIGS. 5A and 5B, the count values of the counters 43 and 44 are continuously updated in synchronization with the rise of the count clock Φ. The first counter 43 generates the lower 8 bits of the random value RND, and the second counter 44 generates the upper 8 bits of the random value RND.

  When the game ball passes through the symbol start port 15 during the counter value updating operation, the winning switch signal SG falls to the L level after rising to the H level (ON state). The winning switch signal SG is supplied to the main control unit 21 via the buffer circuit BUF (see FIG. 10) as in the conventional configuration. In this embodiment, the random number generation circuit shown in FIG. The difference is that it is built in the microcomputer 21A.

  Since the winning switch signal SG is supplied to the D input terminal of the second flip-flop 42, the winning switch signal SG is stored in the second flip-flop 42 at the timing when the counting clock Φ bar rises, It is output to the Q output terminal. This output signal is supplied as a latch signal LT to the winning storage circuit HIT (see FIGS. 5C to 5E).

  In the present embodiment, as in the conventional circuit shown in FIG. 10, the winning switch signal SG is not used as it is as a latch signal, but the winning switch signal SG is shaped by the count clock Φ bar to be the latch signal LT. Therefore, even if ringing occurs at the rise or fall of the winning switch signal SG, such a vibration component is automatically absorbed by the counting clock Φ bar.

  The latch signal LT output from the second flip-flop 42 is supplied to the clock terminals CK of the two latch circuits 45 and 46 via the input terminal of the first AND gate 61. Therefore, if the control signal CTL supplied to the first AND gate 61 is at the H level, the output data of the counters 43 and 44 is acquired as the random value RND by the latch circuits 45 and 46 at the rising timing of the latch signal. . As shown in FIG. 5 (h), since the control signal CTL is at the H level at the normal timing, the random number value RND is acquired by the latch circuits 45 and 46 corresponding to the winning switch signal SG. .

  However, in this embodiment, the latch circuits 45 and 46 are operated at the rising timing of the count clock Φ bar, rather than operating the latch circuits 45 and 46 at an arbitrary timing when the winning switch signal SG is generated. The count clock Φ bar has a duty ratio of 50%, and its rising timing coincides with the falling timing of the counting clock Φ. Since the counters 43 and 44 are updated at the rising timing of the counting clock Φ, according to the configuration of the present embodiment, the counter 43 is accurately delayed by 1/2 cycle from the update timing of the counters 43 and 44. , 44 stable output data is latched.

  On the other hand, for example, as shown in the circuit configuration of FIG. 10, if the latch circuit is operated at random timing, or if the update timing of the counter and the timing of the latch operation are not sufficiently separated, An unreasonable counter value may be obtained.

  Incidentally, the latch signal LT is logically inverted in the NOT gate 63 and supplied to the clock terminal CK of the third flip-flop 60 (see FIG. 5F). Therefore, the Q output of the third flip-flop 60 becomes H level at the falling timing of the latch signal LT. This H level can be recognized by the CPU via the buffer circuit 64 as well as the winning detection signal DET indicating that the winning switch signal SG is turned on.

  When the winning detection signal DET becomes H level, the Q bar output of the third flip-flop 60 becomes L level. The Q-bar output of the third flip-flop 60 is supplied to the first AND gate 61 as the control signal CTL. However, since the control signal CTL becomes L level, the latch signal LT is changed to H level again after that. Even if it rises, the latch circuits 45 and 46 do not latch. Therefore, for example, even if ringing occurs at the fall of the winning switch signal SG, the circuit is not affected.

  As will be described later, the CPU acquires data in the buffer 64 every 2 mS and determines whether or not the winning detection signal is at the H level. When the winning detection signal becomes H level, the CPU accesses the buffer 47 and the buffer 48 in this order, and the random number values (16-bit length) latched in the latch circuits 45 and 46 every 8 bits. To get to. That is, the chip select signals CS1 and CS2 are set to the L level in this order only by this data read timing.

  When the chip select signal CS2 becomes L level, the output of the second AND gate 62 changes to L level, so that the Q bar output of the third flip-flop 60 changes from L level to H level, and the control signal CTL becomes H level. Return to level. Therefore, thereafter, the latch signal LT is generated corresponding to the winning switch signal SG, and a new counter value (random number value) is latched in the latch circuits 45 and 46.

  As described above, in the random number generation circuit of the embodiment, after the counter values (random number value RND) of the counters 43 and 44 are once latched by the latch circuits 45 and 46, the CPU passes through the buffers 47 and 48. As long as the random value RND is not acquired, even if the winning switch signal SG is changed, the winning detection signal DET is not generated. Therefore, even if ringing occurs in the winning switch signal SG or the latch signal LT, there is no possibility that the winning detection signal DET is generated twice.

  As described above, in the present embodiment, the winning circuit is not permitted until the random number value RND is acquired by the CPU after the random number value RND is latched by the latch circuits 45 and 46. Therefore, there is a possibility that a problem may occur when the game balls win continuously. However, the CPU checks the winning detection signal DET every 2 mS. If the winning detection signal DET is ON, the CPU immediately acquires the random value RND via the buffers 47 and 48. There is no risk of harm. That is, it is not possible for a game ball to win continuously at a time interval of about 2 mS if the moving speed of the game ball is taken into consideration.

  Further, when the random number value RND is acquired, the winning detection signal DET automatically returns to the OFF level, so that an erroneous determination does not occur in the next check process.

  Next, an outline of a program of the main control unit 21 that controls the game operation in an integrated manner will be described. 6 to 7 are flowcharts showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 6) that is activated based on the restoration or input of the power supply voltage, and a maskable timer interrupt process (FIG. 7 (FIG. 7 ( a)). Note that a Z80 CPU (Zilog) equivalent product is built in the one-chip microcomputer 21A that realizes these processes. The one-chip microcomputer 21A also has a built-in watchdog timer, and is configured to forcibly reset the CPU when periodic clear processing is interrupted.

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SW is turned off and the power is turned on, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SW is turned on. There is a case where the power source is turned on by being operated. Note that the runaway of the control program may start the watchdog timer and forcibly reset the CPU.

  In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1) and sets to the interrupt mode 2 (ST2). Further, the value of the stack pointer SP in the CPU is initialized to the final address of the stack area (ST3), and the values of internal registers including each part of the one-chip microcomputer are initialized (ST4).

  Subsequently, the RAM clear signal DEL is acquired from the input port (ST5). The RAM clear signal DEL is a signal for determining whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer 21A, and has a value corresponding to the ON / OFF state of the initialization switch SW operated by the staff. Have.

  Next, the level of the RAM clear signal is determined (ST6). If it is assumed that the RAM clear signal is in the ON state, the entire area of the built-in RAM is cleared to zero (ST10). Therefore, the value of the backup flag BFL set in the process of step ST37 in FIG. 7B becomes zero together with other checksum values.

  Next, a power-on command for notifying that the RAM area has been cleared to zero is output (ST11), and a CTC (Z80 counter timer circuit for outputting an interrupt signal INT for starting the timer interrupt operation (FIG. 7A). ) Is initially set (ST12). Then, with the CPU set to the interrupt disabled state (ST13), update processing is executed for various counters (ST14), and then the CPU is returned to the interrupt enabled state and the process returns to step ST13. The counter updated in step ST14 includes a miss symbol counter. This miss symbol counter is out of the result of the big hit lottery process in the special symbol process (ST27) of FIG. 7A. It is a counter for deciding what kind of out-of-game to produce when it becomes a state.

  Returning to the determination process in step ST6, the RAM clear signal is OFF when the CPU is forcibly reset by the watchdog timer or when recovering from the power failure state. In such a case, the content of the backup flag BFL is determined following the determination in step ST6 (ST7). The backup flag BFL is data indicating that the operation of the power supply monitoring process of FIG. 7B is executed. In this embodiment, the backup flag BFL is set to 5AH in the process of step ST37 when the power is turned off. It is cleared to zero in the process of step ST33 after the power is restored.

  When the power is turned on or when recovering from a power failure, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST7 to step ST10 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum operation for calculating a checksum value is executed (ST8). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST9).

  In the SUM address, the checksum value by the same checksum calculation is stored in the power supply monitoring process (FIG. 7B) executed when the voltage drops (ST38). The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST9.

  However, if the checksum calculation (ST38) cannot be executed when the power is turned off, or if it can be executed, the data in the work area will be damaged until the checksum calculation (ST8) of the main process is executed. In such a case, the determination result in step ST9 is inconsistent. If data corruption is detected due to a discrepancy between the determination results, the process proceeds to step ST10, RAM clear processing is executed, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST9 that the checksum value obtained by the checksum calculation (ST8) matches the stored value at the SUM address, the process proceeds to step ST12.

  Next, a timer interrupt processing program (FIG. 7A) started every 2 mS while interrupting the main processing described above will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST15.

  In the power supply monitoring process (ST20), the level of the voltage drop signal supplied from the power supply board 20 is determined. The specific processing content will be described later. When the power monitoring process (ST20) ends, the value of the winning counter RG used in the lottery operation in the normal symbol process (ST26) is updated (ST21). Note that the random value RND for jackpot determination used in the lottery operation in the special symbol process (ST27) is generated by the random number generation circuit of FIG. 4 and is not updated in the process of step ST21.

  When the winning random number update process (ST21) ends, a timer subtraction process is performed for the timer that manages the time of each gaming operation (ST22). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times.

  Subsequently, ON / OFF signals of various switches including the winning detection switch of the big winning opening 16 are inputted, and the ON / OFF signals are stored in the work area (ST23). Note that the winning detection signal DET of the symbol start port 15 is acquired from the buffer circuit 64 of the random number generation circuit (FIG. 4), and if it is at the H level, an ON signal is stored in the work area.

  When the switch input process (ST23) is completed, an error management process is performed (ST24). The error management process includes a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged.

  Next, after executing the management process based on the prize ball counting signal received from the payout control unit 24 (ST25), the normal symbol process is performed (ST26). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball has passed through the gate based on the switch input result in step ST23, the winning counter RG updated in the random number updating process (ST21) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. In addition, if it is a hit, processing for the operation of a normal electric accessory such as an electric tulip is performed.

  Subsequently, special symbol processing is performed (ST27). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special winning opening 16. First, in the switch input process of step ST23, it is determined whether or not the H level winning detection signal DET is acquired from the buffer circuit 64. When it is determined that the winning detection state is set, a 16-bit random number value RND is acquired every 8 bits from the buffers 47 and 48 in FIG. Note that at the stage when the upper 8 bits of the random number value RND are acquired, the winning detection signal DET returns to the L level, and the control signal CTL returns to the H level (see FIG. 5).

  And based on the acquired random number value RND, a big hit lottery process is executed. Then, if the lottery result is a winning state, the operation mode is changed to the big hit operation mode. In addition, if it is a big hit, processing for the operation of special electric accessories such as a big prize opening is performed.

  After such special symbol processing (ST27), the lighting operation of the LEDs managed by the main control unit 21 is advanced (ST28), and the solenoid drive processing for realizing the opening / closing operation of the electric tulip, the big prize opening, etc. is executed. Later (ST29), the CPU is returned to the interrupt permission state EI and the timer interrupt is finished (ST30). As a result, the process returns from the interrupt process routine to the infinite loop process (FIG. 6) of the main process, and the process of step ST17 is executed.

  Next, the power supply monitoring process (ST20) shown in FIG. In the power supply monitoring process (ST20), first, a voltage drop signal supplied from the power supply board 20 is acquired through an input port (not shown) (ST31), and it is determined whether it is an abnormal level (ST32). If it is not an abnormal level, the abnormal number counter and the backup flag BFL are cleared to zero and the process is terminated (ST33).

  On the other hand, if the voltage drop signal is at an abnormal level, the abnormal number counter is incremented (+1) (ST34), and it is determined whether the counting result exceeds the upper limit value MAX (ST35). This is because the data acquired from the input port may be garbled due to the influence of noise or the like, and the abnormal level is continuously set for a predetermined number of times (for example, upper limit MAX = 2). In the case of maintaining, it is determined that the AC power source is actually shut off.

  As described above, in this embodiment, the subsequent backup processing is not started immediately even when the power is turned off, and the operation start timing is delayed by MAX × 2 mS. However, (1) The power supply drop signal is not a drop in the DC power supply voltage, but a drop in the AC DC voltage is detected. (2) The DC power supply voltage is maintained for a while after the AC power supply is shut off by a large-capacitance capacitor. (3) The power supply monitoring process is repeated at a high speed (every 2 ms), and (4) the backup process is extremely simple and finishes quickly, so there is virtually no adverse effect.

  By the way, as a result of the determination in step ST35, if the count value of the abnormal number counter coincides with the upper limit value MAX, the abnormal number counter is cleared to zero (ST36), and then 5AH is set to the backup flag BFL (ST37). Next, the same calculation as in step ST7 of the main routine is executed for the same work area (work area), and the calculation result is stored (ST38). The operation to be executed is typically an 8-bit addition operation.

  Thereafter, the one-chip microcomputer 21A is set in a RAM access prohibited state (ST39), and output data of all output ports is cleared (ST40). As a result, unreasonable data is prevented from being transmitted to the payout control unit 24 that starts the same type of power supply monitoring process later than the main control unit 21. When the above backup process is completed, the generation of the interrupt signal INT is prohibited by the setting process for the CTC, and the DC power supply voltage is lowered while repeating the infinite loop process (ST41). At this timing, the CPU is originally in an interrupt disabled state (see ST30). However, in this embodiment, an interrupt signal from the CTC is used to eliminate as much as possible the possibility of malfunction due to a drop in power supply voltage. INT output is also prohibited.

  Although the embodiments of the present invention have been specifically described above, the specific description content is not intended to limit the present invention, and various modifications can be made.

  For example, in the description of the embodiment, the winning detection signal DET is acquired by the input process by the CPU. However, as shown in FIG. 8, the winning detection signal DET may be added to the interrupt terminal INT of the CPU. is there. Then, in a winning interrupt process (FIG. 9 (a)) based on the winning detection signal DET, random values are obtained in order from the buffer circuits 47 and 48, and stored in LOT address and LOT + 1 address (ST50). Note that the interrupt process is started in a state where the CPU is in the interrupt disabled state, so there is no possibility of multiple interrupts due to the winning detection signal DET.

  When the process of step ST50 is executed, the chip select signal CS2 becomes L level during the data acquisition process from the buffer circuit 48. As a result, the winning detection signal DET returns to L level, and the control signal CTL is also at the H level which is a steady level. Return to.

  Next, the winning detection flag FLG is set to 1, and the CPU is set in an interrupt enabled state (ST51 to ST52). As a result, after completion of the interrupt process, an interrupt signal is accepted. At this timing, the winning detection signal DET returns to the L level, so there is no possibility of multiple interrupts.

  Thus, the random value acquired below the LOT address is used in the special symbol process. That is, as shown in FIG. 9B, in the special symbol process, first, the winning detection flag FLG is determined. If it is in the set state, the winning detection flag FLG is reset and the big hit lottery process is executed. (ST62).

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit block diagram which shows the random number generation circuit which is the principal part of a main control board. 6 is a time chart showing the operation of the random number generation circuit of FIG. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is a block diagram which shows the modification of a random number generation circuit. It is a flowchart explaining the program processing in the case of using the random number generation circuit of FIG. It is drawing explaining a prior art.

Explanation of symbols

GM gaming machine RND random number value Φ counting clock 43, 44 counter SG sensor signal 42 detection memory circuit 45, 46 latch circuit HIT control circuit

Claims (11)

A gaming machine that determines whether or not the CPU executes a lottery process to generate a gaming state advantageous to a player due to a sensor signal indicating the occurrence of a predetermined gaming operation,
A random number generation circuit for generating a random value used in the lottery process,
A counter that is cyclically updated in response to a counting clock;
Upon receipt of the sensor signal, a detection memory circuit that holds and outputs the signal in synchronization with an edge of the counting clock;
A latch circuit that acquires and holds the output data of the counter as the random number value in synchronization with the edge of the output signal of the detection storage circuit on condition that the control signal is at a permission level;
A gaming machine comprising: a control circuit that changes the control signal from a permission level to a prohibition level after the latch circuit acquires the random number value.   2. The gaming machine according to claim 1, wherein when the CPU acquires the random number value held by the latch circuit, the control circuit returns a control signal of a prohibited level to a permission level.   3. The counter updates the counter value in synchronization with the first edge of the count clock, while the detection storage circuit holds the sensor signal in synchronization with the second edge of the count clock. The gaming machine described in 1.   The gaming machine according to claim 1, wherein the counting clock is generated by dividing a basic clock by two.   The logic gate which receives the output signal of the said detection memory circuit and the said control signal which the said control circuit outputs is provided, The output of the said logic gate is supplied to the said latch circuit. Gaming machine.   The gaming machine according to claim 5, wherein the control circuit is configured by a flip-flop that receives the output signal of the logic gate by inverting the logic and stores a fixed value in synchronization with an edge of the output signal.   The gaming machine according to claim 5 or 6, wherein the control circuit is provided with a clear terminal for forcibly resetting its output value.   The gaming machine according to claim 7, wherein the clear terminal is activated when the CPU acquires output data of the counter held by the latch circuit.   The gaming machine according to claim 7 or 8, wherein the clear terminal of the logic circuit is activated at the time of power reset together with the clear terminal of the counter and the detection storage circuit.   The gaming machine according to claim 1, wherein output data of the latch circuit is acquired by the CPU through a buffer circuit having three states. The gaming machine according to claim 1, wherein the random number generation circuit is built in a one-chip microcomputer together with the CPU.