JP2010016233A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2010016233A5 JP2010016233A5 JP2008175720A JP2008175720A JP2010016233A5 JP 2010016233 A5 JP2010016233 A5 JP 2010016233A5 JP 2008175720 A JP2008175720 A JP 2008175720A JP 2008175720 A JP2008175720 A JP 2008175720A JP 2010016233 A5 JP2010016233 A5 JP 2010016233A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- manufacturing
- pad region
- gas
- cover layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000010410 layer Substances 0.000 claims 20
- 239000004065 semiconductor Substances 0.000 claims 18
- 238000004519 manufacturing process Methods 0.000 claims 17
- 239000007789 gas Substances 0.000 claims 10
- 238000000034 method Methods 0.000 claims 8
- 239000000460 chlorine Substances 0.000 claims 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims 4
- 229910052801 chlorine Inorganic materials 0.000 claims 3
- 239000011229 interlayer Substances 0.000 claims 3
- 238000001020 plasma etching Methods 0.000 claims 3
- 239000011241 protective layer Substances 0.000 claims 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- 229910003902 SiCl 4 Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- -1 chlorine ions Chemical class 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 125000004430 oxygen atom Chemical group O* 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 239000009719 polyimide resin Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Claims (11)
前記配線層群が被覆されるように、絶縁性のカバー層を形成するステップと、
前記パッド領域が露出するように、前記カバー層をプラズマエッチングにより除去するステップと、
を具備し、
前記パッド領域は、アルミニウムにより形成され、
前記プラズマエッチングにより除去するステップは、
炭素ラジカル及びフッ素ラジカルを発生させるＣＦ系ガスを用いて、前記パッド領域を露出させるステップと、
前記露出させるステップの後に、塩素ラジカル又は塩素イオンを発生させるＣｌ２系ガスを用いて、前記パッド領域の表面に生成した堆積物を除去するステップとを備える
半導体装置の製造方法。 Forming a wiring layer group having a pad region;
Forming an insulating cover layer so that the wiring layer group is covered;
Removing the cover layer by plasma etching so that the pad region is exposed;
Comprising
The pad region is formed of aluminum,
The step of removing by plasma etching comprises:
Exposing the pad region with a CF-based gas that generates carbon and fluorine radicals;
And a step of removing deposits generated on the surface of the pad region using a Cl 2 gas that generates chlorine radicals or chlorine ions after the exposing step.
前記Ｃｌ２系ガスは、Ｃｌ２ガス、ＢＣｌ３、ＳｉＣｌ４、及びＣＣｌ４からなる集合から選ばれる少なくとも一のガスを含んでいる
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the Cl 2 gas includes at least one gas selected from the group consisting of Cl 2 gas, BCl 3 , SiCl 4 , and CCl 4 .
前記ＣＦ系ガスは、ＣＦ４ガス、ＣＨＦ３ガス、及びＮ２ガスを含む混合ガスである
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the CF-based gas is a mixed gas containing CF 4 gas, CHF 3 gas, and N 2 gas.
前記カバー層は、酸素原子とシリコン原子とを含む化合物からなる酸化シリコン系の膜により形成される
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to any one of claims 1 to 3,
The method for manufacturing a semiconductor device, wherein the cover layer is formed of a silicon oxide film made of a compound containing oxygen atoms and silicon atoms.
前記酸化シリコン系の膜は、ＳｉＯＮ膜である
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the silicon oxide film is a SiON film.
更に、
前記カバー層を形成するステップの後に、前記カバー層上に、樹脂製の絶縁保護層を形成するステップと、
前記プラズマエッチングするステップの前に、前記パッド領域の上方において前記絶縁保護層を除去するステップと、
を具備する
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
Furthermore,
After the step of forming the cover layer, forming a resin insulating protective layer on the cover layer;
Removing the insulating protective layer above the pad region before the plasma etching step;
A method for manufacturing a semiconductor device comprising:
前記絶縁保護層は、ポリイミド樹脂を含んでいる
半導体装置の製造方法。 A manufacturing method of a semiconductor device according to claim 6,
The insulating protective layer is a method for manufacturing a semiconductor device including a polyimide resin.
前記配線層群を形成するステップは、
下層露出部を有する下部配線層を形成するステップと、
前記下部配線層上に、層間絶縁膜を介して、前記パッド領域を有する上部配線層を形成するステップとを備え、
前記パッド領域を露出させるステップは、前記パッド領域と前記下層露出部との双方が露出するように、前記カバー層及び前記層間絶縁膜をエッチングするステップを含んでいる
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
The step of forming the wiring layer group includes:
Forming a lower wiring layer having a lower layer exposed portion;
Forming an upper wiring layer having the pad region on the lower wiring layer via an interlayer insulating film,
The step of exposing the pad region includes a step of etching the cover layer and the interlayer insulating film so that both the pad region and the lower layer exposed portion are exposed.
前記下層露出部は、ヒューズ素子部分である
半導体装置の製造方法。 A method for manufacturing a semiconductor device according to claim 8, comprising:
The method for manufacturing a semiconductor device, wherein the lower layer exposed portion is a fuse element portion.
前記層間絶縁膜は、ＳｉＯＮ膜を含んでいる
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 8 or 9,
The method for manufacturing a semiconductor device, wherein the interlayer insulating film includes a SiON film.
前記配線層群を被覆する、絶縁性のカバー層と、 An insulating cover layer covering the wiring layer group;
を具備し、Comprising
前記カバー層には、前記パッド領域が露出するように、開口が設けられており、 The cover layer is provided with an opening so that the pad region is exposed,
前記パッド領域において、中央部分は露出しており、周縁部分は前記カバー層に覆われており、前記中央部分と前記周縁部分との間には、前記中央部分が低くなるように、段差が形成されている In the pad region, a central part is exposed, a peripheral part is covered with the cover layer, and a step is formed between the central part and the peripheral part so that the central part is lowered. Has been
半導体装置。Semiconductor device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008175720A JP2010016233A (en) | 2008-07-04 | 2008-07-04 | Method of manufacturing semiconductor device |
| KR1020090060270A KR101049383B1 (en) | 2008-07-04 | 2009-07-02 | Method for manufacturing semiconductor device |
| TW098122555A TW201013776A (en) | 2008-07-04 | 2009-07-03 | A manufacturing method of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008175720A JP2010016233A (en) | 2008-07-04 | 2008-07-04 | Method of manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010016233A JP2010016233A (en) | 2010-01-21 |
| JP2010016233A5 true JP2010016233A5 (en) | 2011-06-30 |
Family
ID=41702053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008175720A Withdrawn JP2010016233A (en) | 2008-07-04 | 2008-07-04 | Method of manufacturing semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2010016233A (en) |
| KR (1) | KR101049383B1 (en) |
| TW (1) | TW201013776A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015146023A1 (en) * | 2014-03-25 | 2015-10-01 | 株式会社Ｊｏｌｅｄ | Etching method and organic el display panel manufacturing method using same |
| JP2016122801A (en) * | 2014-12-25 | 2016-07-07 | ルネサスエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
| TWI794238B (en) * | 2017-07-13 | 2023-03-01 | 荷蘭商Ａｓｍ智慧財產控股公司 | Apparatus and method for removal of oxide and carbon from semiconductor films in a single processing chamber |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100805695B1 (en) * | 2005-08-17 | 2008-02-21 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device with metal fuse |
| KR20070105827A (en) * | 2006-04-27 | 2007-10-31 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device having repair fuse |
-
2008
- 2008-07-04 JP JP2008175720A patent/JP2010016233A/en not_active Withdrawn
-
2009
- 2009-07-02 KR KR1020090060270A patent/KR101049383B1/en not_active IP Right Cessation
- 2009-07-03 TW TW098122555A patent/TW201013776A/en unknown
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8018023B2 (en) | Trench sidewall protection by a carbon-rich layer in a semiconductor device | |
| JP2009530871A5 (en) | ||
| JP2007019187A5 (en) | ||
| TWI570840B (en) | Semiconductor device and manufacturing method thereof | |
| KR20130143515A (en) | Semiconductor device and method of manufacturing the same | |
| JP2009158940A5 (en) | ||
| JP2007110112A5 (en) | ||
| JP2010118513A (en) | Method of manufacturing semiconductor device and semiconductor device | |
| JP2004281936A (en) | Manufacturing method of semiconductor device | |
| JPWO2004097923A1 (en) | Manufacturing method of semiconductor device | |
| JP2007110043A (en) | Manufacturing method of semiconductor device | |
| TW451405B (en) | Manufacturing method of dual damascene structure | |
| US20160358811A1 (en) | Interconnect structure | |
| JP2010016233A5 (en) | ||
| TWI236094B (en) | Method for forming multi-layer metal line of semiconductor device | |
| JP4523351B2 (en) | Manufacturing method of semiconductor device | |
| TW200824039A (en) | Methods for forming semiconductor devices, damascene structures and interconnect structures | |
| JP2014078579A (en) | Semiconductor device manufacturing method | |
| JP2010238988A (en) | Method of manufacturing semiconductor device | |
| KR20120050827A (en) | Manufacturing method of metal line of semiconductor device | |
| TWI278063B (en) | Method for fabricating metal line in semiconductor device | |
| JP2007005583A5 (en) | ||
| JP4550786B2 (en) | Manufacturing method of semiconductor device | |
| JP2008300385A (en) | Wiring structure, and manufacturing method thereof | |
| US20130056874A1 (en) | Protection of intermetal dielectric layers in multilevel wiring structures |