TW201013776A - A manufacturing method of a semiconductor device - Google Patents

A manufacturing method of a semiconductor device Download PDF

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Publication number
TW201013776A
TW201013776A TW098122555A TW98122555A TW201013776A TW 201013776 A TW201013776 A TW 201013776A TW 098122555 A TW098122555 A TW 098122555A TW 98122555 A TW98122555 A TW 98122555A TW 201013776 A TW201013776 A TW 201013776A
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TW
Taiwan
Prior art keywords
gas
semiconductor device
layer
manufacturing
wiring layer
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TW098122555A
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Chinese (zh)
Inventor
Masao Kunitou
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Nec Electronics Corp
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Publication of TW201013776A publication Critical patent/TW201013776A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A purpose of the present invention is providing a manufacturing method of a semiconductor device which can suppress a generation of a deposit on a pad area. A manufacturing method of a semiconductor device comprises, forming a wiring layer group having a pad area, forming an insulated cover layer to cover the wiring layer group, and removing the cover layer by plasma etching to expose the pad area. The pad area is made of aluminum. The removing by plasma etching includes, exposing the pad area by a gas like CF that generates a carbon radical and a fluorine radical, and removing a deposit formed on a surface of the pad area by a gas like Cl2 that generates a chlorine radical or a chlorine ion, after the exposing.

Description

201013776 六、發明說明： 【發明所屬之技術領域】 本發明係有關半導體裝置之繫造方法，牡^ 墊區的半導體裝置之製造方法。 _關於具有銘製接 【先前技術】 基板(例如矽基板)上形成有半導體積體電路 已知。半導體裝置被製作成半導體晶片。製 體積體電路。該半導體積體電路包含配線:導=== 路後，半導體晶圓被切開成複數之半導體$成'^體積體電 圖1例示著顯示半導體晶圓的俯視圖00 體晶圓上之複數半導體“巾之—·讀。扣域於該+導 如圖1之放大圖所示，於複數之各個半 接塾區。接墊區為配線層中的一部分。接设有 線層與晶片外的裝扉下稱外部㈣電連接；^使各4的配 圖2係顯示各晶片之表面部分的剖面圖。各、 ΐί ^ 設有覆蓋層及絕緣樹脂層(例^酿亞i。就^ 石夕原子之化合物賴成的膜）。覆蓋氧原子及 =内，等體積體電路而找。於各晶片之表面部分中 Ϊ覆蓋層及絕緣樹脂層所覆蓋。另-方面，於ΪΪ 品上’覆蓋層及絕緣樹脂層設有開π，露雌墊區。 ' 以下說明圖2所示之轉難置之製造方法。 ρ Γ先/ Ϊ基板(未示)上形成包含接塾區的配線層。依序堆最 聚ϋ(絕緣樹脂層)及抗_，以覆蓋該配線層。而i, 除聚醯亞胺。圖3A顯示去除聚酸亞胺後之狀態的剖^遮H 3B係接墊區的俯視圖。 又圖 其後，以聚酿亞胺為遮罩而钱刻覆蓋層，俾露出接塾區。覆 201013776 區上殘留,儿積物時，使接塾與外 拉％。备接墊 困難^此，較理想係以接墊區上不殘留]變得 號公報）。專利文獻！言己载著如下=特開平9-115878 化系化學物質之氣體中的至少—種吏氣用齡^產生^系氧體及氧 【先磁敏獻】專利技術文獻丨日本特開平叫職號公報 【發明内容】 <發明所欲解決之課題> 接塾’有時採—此時， 接塾區使用_，當採用CF系氣體 來自CF系氣體的氟自由基反應，產生接 產生A1F3為沉積物。 銘Al^f。的且大t中的水分剛等反應，树產生氫氧化 、（）3 /、體而5，因下式ί，產生氫氧化鋁ai(〇h)3。201013776 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and a method of manufacturing a semiconductor device in a pad region. _About the connection with the prior art [Prior Art] It is known to form a semiconductor integrated circuit on a substrate (for example, a germanium substrate). The semiconductor device is fabricated as a semiconductor wafer. Making a volume circuit. The semiconductor integrated circuit includes wiring: after the === path, the semiconductor wafer is cut into a plurality of semiconductors. The volume of the semiconductor is shown in FIG. 1 to show the plurality of semiconductors on the 00-body wafer of the semiconductor wafer. The towel--reading. The buckle field is shown in the enlarged view of Figure 1. In each of the plurality of junctions, the pad area is part of the wiring layer. The wire layer and the outside of the wafer are attached. The external (four) electrical connection is hereinafter referred to as follows; ^ is a cross-sectional view showing the surface portion of each wafer in Fig. 2, each of which is provided with a cover layer and an insulating resin layer (for example, ^亚亚. The film formed by the compound is covered with an oxygen atom and an internal volume circuit. The surface layer of each wafer is covered with a ruthenium cover layer and an insulating resin layer. On the other hand, the cover layer is on the enamel. And the insulating resin layer is provided with an opening π, a female pad area. ' The following describes a manufacturing method of the turning device shown in Fig. 2. A wiring layer including a joint region is formed on the ρ Γ/ Ϊ substrate (not shown). The sequence stack is the most concentrated (insulating resin layer) and the anti- _ to cover the wiring layer, and i, in addition to polyimine. 3A shows a top view of the H 3B pad region in the state after removal of the polyimine. Further, the cover layer is covered with a poly-imine, and the exposed region is exposed. 201013776 Residues in the area, when the children are accumulated, the joints are pulled out and the outer ones are pulled out. It is difficult to prepare the mats. This is more desirable, and there is no residue on the mat area.] Patent Document! JP-A-9-115878 At least one kind of gas in the chemical substances of the chemical system is produced by the age of the gas, and the oxygen is produced. [Prototype of magnetic properties] [Technical literature of the first magnetic product] 丨 特 特 特 叫 【 【 【 发明 发明 发明 发明The problem to be solved by the invention> The connection is sometimes 'occupied' - at this time, the junction area is used _, and when a CF-based gas is used to react with a fluorine radical from a CF-based gas, A1F3 is produced as a deposit. ^f. The water in the large t just waits for the reaction, the tree produces hydrogen hydroxide, () 3 /, and the body 5, because of the following formula, the aluminum hydroxide ai (〇h) 3 is produced.

(式 1) ; A1F3 + 3 H2〇 -&gt; A1(0H)3 + 3HF 又，因式1產生為副產物的pjp，因下式2又產生A1F3。 (式 2) ; 3HF +A1 AlF3+3/2H2 因式2產生的AIF3又促進式}的反應。亦即，促進八1〇113的 產生。 產生於接墊區上的AIOH3妨礙接墊區與外部裝置的電連接。 又，所產生的AIOH3亦成為接墊區變色的原因，外觀上也不 201013776 4。半導體裝置的製程中， 晶圓測試之際，為調查各晶片的^ J蓋層後’進行晶圓測試。 時，如圖5A及圖5B所示，接執性而將針接觸至接塾區。此 產生時，如圖6A及圖6B所干，二土殘留針痕。當促進A10H3的 變色部。 ’、十痕之周圍形成因Α1〇Η3形成的 為抑制A1F3的產生，可去# 烘烤(加熱)處理。但是，徐A :】蝕刻覆蓋層後實施水洗處理或 接塾區溶出。又，實施理時’因水洗時間而有時銘在 上產生氧化銘膜。九、烤處叫’因供烤時間而有時在接墊區 為抑制A10H3的產生，可老廢/卜\丨 ，置(晶片或晶圓)。為在水分少5二二的t下保管半導體 包裝構件可考慮準備特別的構件^^保g t裝半導體裝置的 之沉積物產生 是’ ΪΓΓ構件成為製造縣增加聽乾財裝)等。但 的半=裝供可抑制接墊區上 〈解決課題之手段&gt; ❿ 有接1步驟，形成具 產生=!'ΐ體:使 塾=表面===或Α離子的c丨2系氣趙以去除產生於接 依本發明，藉由使用CF系氣體的雷將爲办丨，时进 :朽土蝕刻。由於使用CF系氣體，接墊“時:接J aif3為沉積物。所產生的A1F3因著 於以0¾系氣體去除ΛΑ，因此不會體刻。由 接塾區與外部裝㈣t連接。 （卿也顿於妨礙 &lt;發明之效果〉 201013776 =發明，能提供可抑雛·上之沉輸產生的半 置之製造方法 導體裝 【實施方式】 &lt;實施發明之最佳形態&gt; 以下，參照附加圖式，說明依本發明之實施 置之製造方法。 只他办t的+導體裝 (第1實施形態） 的丰導體晶圓。在半導體晶圓上形成包含配線層群 的U體積體電路。配線料包含賴職的配線圖案 配2群之一部分形成接墊區i。其後，形覆(Formula 1); A1F3 + 3 H2〇 -&gt; A1(0H)3 + 3HF Further, since Formula 1 is produced as a by-product pjp, A1F3 is again produced by the following Formula 2. (Formula 2); 3HF + A1 AlF3 + 3 / 2H2 The AIF3 produced by Formula 2 promotes the reaction of the formula. That is, to promote the production of 八〇113. The AIOH 3 generated on the pad area interferes with the electrical connection of the pad area to the external device. Moreover, the resulting AIOH3 also becomes a cause of discoloration in the pad area, and the appearance is not 201013776 4 . In the manufacturing process of a semiconductor device, at the time of wafer testing, a wafer test was performed after investigating the cap layer of each wafer. At the time, as shown in FIGS. 5A and 5B, the needle is brought into contact with the joint region. When this occurs, as shown in Fig. 6A and Fig. 6B, the two soils have residual needle marks. When promoting the discoloration part of A10H3. The formation of 十1〇Η3 around the ten marks is to suppress the production of A1F3, and can be baked (heated). However, Xu A:] is subjected to a water washing treatment or a dissolution of the joint region after etching the coating layer. In addition, the implementation time is based on the time of washing, and sometimes the oxidized film is produced. Nine, the roasting area is called 'due to the baking time and sometimes in the mat area to suppress the generation of A10H3, can be old waste / Bu \ 丨, set (wafer or wafer). In order to store the semiconductor package member at a temperature of 5 to 2%, it is conceivable to prepare a special member to prevent the deposition of deposits in the semiconductor device, and to produce a semiconductor device. However, the half = loading can suppress the area of the mat. <Means for solving the problem> ❿ There is a step to form a c丨2 system that produces ==!' ΐ: 塾=surface=== or Α ion The removal of Zhao is based on the invention, and the use of a CF-based gas will be carried out. Due to the use of CF-based gas, the pad "when: J aif3 is a deposit. The A1F3 produced is removed by the gas of the 03⁄4 system, so it is not engraved. It is connected to the external device (4) by the junction area. Also in the case of the effect of the invention. 201013776 = Inventive, it is possible to provide a semi-finished manufacturing method for suppressing the occurrence of sinking. [Embodiment] &lt;Best Mode for Carrying Out the Invention&gt; The manufacturing method according to the embodiment of the present invention will be described with reference to the drawings. Only the + conductor package of the + conductor package (the first embodiment) can be used. A U-volume circuit including a wiring layer group is formed on the semiconductor wafer. The wiring material includes a wiring pattern of Lai's job and one part of the two groups forms a pad area i. Thereafter, the shape is covered.

線層群。進而，在覆蓋層2上形成聚酿亞胺^^ ^ 夕3。覆盍層2為以矽氧化物系的膜(包含氧原子及矽i子 ΐ 成的膜)形成者。覆蓋層2具體而言可舉例如SiON ί制ΐ後，為將絕緣樹脂層3 _化，在絕緣樹脂層3上形成樹 3ΐίΪ糊4。以抗_ 4域罩，將接無1上视緣樹脂層 八示去除鱗植層3後之織的半導體晶®之表面部 二、*土队又’圖7Β顯不圖7Α之狀態的俯視圖。由於絕緣樹 月曰層3被去除’故露出接墊區1的覆蓋層2。 ，次，如圖8Α所示，以絕緣樹脂層3及抗蝕劑4為遮罩，蝕 二覆2 °圖8Β係接墊區1部分的俯視圖。由於覆蓋層2被蚀 刻’故露出接墊區1。 覆蓋^層2以電漿蝕刻進行蝕刻。蝕刻氣體使用CF系氣體。 CF系氣體為產生碳自由基及氟自由基的氣體。CF系氣體具 體而言可例示如包含cf4、CHF3及N2氣體的混合氣體。CF系/氣 體適合使用於姓刻矽氧化物系的膜’即覆蓋層2。來自CF系氣體 的碳5由基與覆蓋層2的氧原子反應。來自CF系氣體的氟自由基 與覆蓋層2的矽原子反應。藉此去除覆蓋層2。 在此’路出之接墊區1暴露於CF系氣體。如上述，露出之接 201013776 的銘與來自CF系氣體的氟自由基反應，產生娜為沉積 用Cl2系氣體=3，_結束後’為去除沉積物5 ，進行使 的氯基紐。來自Cl2系氣體 因昇華而從接墊區】應’气生Ala3°A1Cl3係昇華性高， 物5。圖9A顯示I顯-土除。藉此，從接墊區1上去除沉積 剖面圖，9B顯示其沉積物5後之半導體晶圓表面部分的 及體具體而言可例示如選自於由C12氣體、BC1、SiC】 及CClf成之集合的至少一種氣體。 2^^ BC13&gt;SiC14 絕緣層Ϊ圖1〇A所不’去除抗韻劑4。如圖10B所示，露出 圓測，丨進行_試。晶 的電特性。圖11A係、晶圓測試後之半°導^則^^體，體電路 圖，圖11B係其俯視圖。晶圓測試後；^罙針^剖面 1上。此時，由於已從接墊區！上去除殘留於接塾區 鲁 會產生A1_3，針痕6之周圍不ΐ於變色積物5)，因此也不 然後，將半導體晶圓切割成複數之半導體 晶片於接墊區1與外部裝置電連接。 數之各個 tA_3等之殘留物’嶋可靠度良好地舆 使用蓋層後， 韻刻而產生A1F3，但由於以Cl2系氣體所 體所進行的 因此接墊區1上不會產生A1(0H)3。藉此 外^除瑪’ 體晶片可靠度良好地連接。 外4裝置與各半導 實施：中半= 接 3故抑制AI(0H)3的 201013776 件ΒΛ 長時間，也不須準備特別的包裝構 件(例如Pr〇t〇s及銘乾综包裝)等，可降低保管時所需的成本。 如本實施形ϊ，由於去除A1F3，因此無紐置水洗處理 次供烤處理，可縮短製程。 (第2實施形態） 態之實施形態。圖12係顯示依本實施形 Ϊ體^置之表面。P刀的到面圖。本實施形態中，在配線層 沾，J有熔線兀件7(下層露出部熔線元件7設於比接墊區1深 西? ϋ。亦即’配線層群包含複數層之配線層(下部配線層及上部 -、’、θ ) ’下部配線層設有熔線元件7，上部配線層設有接墊區i。 與上部配線層隔著賴絕緣膜輯疊。制絕緣膜使 用與覆盍層2相同的材料(例如矽氧化物系的膜）。 與第1實施形態同樣地，接墊區1上設有開口。藉此，接墊 區1露出。 曰 ^又，熔線元件7上也留下些微的層間絕緣膜，而設有開口。 糟此，溶線元件7實質上露出。 以下說明依本實施形態的半導體裝置之製造方法。 ^首先，在基板(未圖示)上形成具有嫁線元件7的下部配線層。 其，，經由層間絕緣膜，堆疊具有接墊區丨的上部配線層。然後， 與$ 1實施形態同樣地’在上部配線層上依序堆疊覆蓋層2、聚醯 亞胺3及抗钱劑4。然後，於相當於接墊區i及熔線元件7之上方 的位置，在聚醯亞胺3設置開口。在聚醯亞胺3設置開口後的狀 態顯示於圖13。 接著’姓刻覆蓋層2及層間絕緣膜，同時形成到達接墊區j 之開口及到達熔線元件7之開口。此時，以使用CF系氣體的雷％ _’去除覆蓋層2及層間絕緣膜。 電水 在此，接塾區1設於上部配線層。另一方面，溶線元件7設 於下部配線層。比起形成到達接墊區丨之開口的情形，為形成到 達溶線元件7之開口’必須進行長時間姓刻。亦即，接塾區1上 恰如圖12中以高度h所示之量地多進行蝕刻。此時，接墊區】露 201013776 出以後也長時間暴露於CF系氣體。 使用= 1實施形態相同。 上的/儿積物5。其後的處理也與第 越容ΪΪΪ : ^出以;於C/系氣體的時間越長，3 ❹ 鲁 =====二 【圖式簡單說明】 圖1係顯示半導體晶圓的俯視圖。 口:導體晶圓之表面部分的剖面圖。 圖3A係顯示半導體裝置之製程的程序剖 圖3B係顯示半導體裝置之製程的俯視圖。 示半導體裝置之製程的程序剖面圖。 圖4B係顯示半導體裝置之製程的俯視圖。 示半導體裝置之製程的程序剖面圖。 圖5B係顯不半導體裝置之製程的俯視圖。 頁示輸裝置之製程的程序剖面圖。 圖6B係顯不半導體裝置之製程的俯視圖。 圖 圖7A係顯示依第i實施形態的半導體裝置之製程的程序剖面 圖7B係顯示依第〗實施形態 圖 圖8A係顯示依第彳每 能 ^置之衣知的俯視圖。 丁依弟1貝施形的+導體裝置之製程的程序剖面 圖犯係顯示依第i實施形態的半導體裳置之製裎的俯視圖。 9 201013776 圖 圖9A係顯示依第i實施形態的半導體裂置之製程的程序剖面 圖9B係顯示依第}實施形態的半導體裝置 面圖圖1〇A係顯示依第1實施形態的半導體裂置之製程的If剖 ^ 示依第1實施賴的半導體錢之製程的俯視圖。 面圖 顯示依第1貫施形_半導體裝置之製程的程序剖 ❹ 顯靴第1實施雜的轉體裝置之製_俯視圖。 圖12係顯示依第2實施形態之半導體裝置的气面圖。 圖13係顯示依第2實施形態的半導體裝置^程關面圖。 【主要元件符號說明】 1〜接墊區 2〜覆蓋層 3〜聚醯亞胺(絕緣樹脂層） 4〜抗姓劑 5〜沉積物 6 *〜&lt; 針痕(晶圓測試針痕）Line layer group. Further, a polynymine is formed on the cover layer 2. The cover layer 2 is formed of a ruthenium oxide-based film (a film containing an oxygen atom and a ruthenium i). Specifically, the cover layer 2 is made of, for example, SiON, and the insulating resin layer 3 is formed to form a tree 3 on the insulating resin layer 3. With the anti- 4 domain cover, the top surface of the resin layer 8 is removed, and the surface portion of the semiconductor crystal® after the scale layer 3 is removed, and the top surface of the semiconductor layer is also shown in Fig. 7. . Since the insulating tree layer 3 is removed, the cover layer 2 of the pad region 1 is exposed. Next, as shown in Fig. 8A, the insulating resin layer 3 and the resist 4 are used as a mask, and the top view of the portion of the pad region 1 is shown. Since the cover layer 2 is etched, the pad region 1 is exposed. The cover layer 2 is etched by plasma etching. A CF-based gas is used as the etching gas. The CF-based gas is a gas that generates carbon radicals and fluorine radicals. As the CF-based gas, a mixed gas containing cf4, CHF3, and N2 gas can be exemplified. The CF system/gas is suitably used for the film of the surnamed oxide system, i.e., the cover layer 2. The carbon 5 derived from the CF-based gas is reacted with the oxygen atom of the cap layer 2 by the group. The fluorine radical derived from the CF-based gas reacts with the ruthenium atom of the cap layer 2. Thereby the cover layer 2 is removed. Here, the padded area 1 is exposed to CF-based gas. As described above, the exposed 201013776 is reacted with a fluorine radical derived from a CF-based gas to produce a chlorine-based nucleus for the deposition of Cl2-based gas = 3, after the end of the removal of the deposit 5. From the Cl2 system gas due to sublimation from the pad area] should be 'air-generating Ala3 ° A1Cl3 system sublimation is high, material 5. Figure 9A shows I-soil removal. Thereby, the deposition profile is removed from the pad region 1, and 9B shows that the surface portion of the semiconductor wafer after the deposit 5 is specifically exemplified by, for example, C12 gas, BC1, SiC, and CClf. A collection of at least one gas. 2^^ BC13&gt; SiC14 Insulation Layer 〇A 〇A does not remove the anti-Magnetic Agent 4. As shown in Fig. 10B, the roundness is exposed, and the test is performed. The electrical properties of the crystal. Fig. 11A is a half-length guide body after the wafer test, a body circuit diagram, and Fig. 11B is a plan view thereof. After the wafer test; ^ 罙 pin ^ section 1 on. At this point, since it has been from the pad area! The removal of the residue in the joint area will produce A1_3, and the circumference of the needle mark 6 will not be affected by the discoloration product 5), and therefore, the semiconductor wafer will not be cut into a plurality of semiconductor wafers in the pad area 1 and the external device. connection. The number of residues of each tA_3, etc.' is reliable. After using the cap layer, A1F3 is generated by rhyme, but since the body of the Cl2 gas is used, A1(0H) is not generated on the pad area 1. 3. Thereby, the external wafers are reliably connected. The external 4 device and each semi-conductor are implemented: mid-half = 3, so it can suppress AI(0H)3 of 201013776 pieces for a long time, and it is not necessary to prepare special packaging components (such as Pr〇t〇s and dried composite packaging). , can reduce the cost of storage. According to the embodiment of the present invention, since the A1F3 is removed, there is no need for the washing process for the baking process, and the process can be shortened. (Second embodiment) Embodiment of the state. Fig. 12 is a view showing the surface of the body according to the present embodiment. The top view of the P knife. In the present embodiment, in the wiring layer, J has a fuse element 7 (the lower layer exposed portion fuse element 7 is provided deeper than the pad region 1), that is, the wiring layer group includes a plurality of wiring layers ( The lower wiring layer and the upper-, ', θ) 'lower wiring layer are provided with the fuse element 7, and the upper wiring layer is provided with the pad region i. The upper wiring layer is overlapped with the insulating film. The insulating film is used and covered. The same material as the ruthenium layer 2 (for example, a ruthenium oxide film). As in the first embodiment, an opening is provided in the pad region 1. Thereby, the pad region 1 is exposed. 又^ Again, the fuse element 7 A slight interlayer insulating film is left thereon, and an opening is provided. The lysing element 7 is substantially exposed. The method of manufacturing the semiconductor device according to the embodiment will be described below. First, a substrate (not shown) is formed. A lower wiring layer having the ruling element 7. The upper wiring layer having the pad region 堆叠 is stacked via the interlayer insulating film. Then, the overlay layer 2 is sequentially stacked on the upper wiring layer as in the first embodiment. , polyimine 3 and anti-money agent 4. Then, in the equivalent pad area i and melting The position above the wire member 7 is provided with an opening in the polyimide. The state after the opening of the polyimide 9 is shown in Fig. 13. Next, the cover layer 2 and the interlayer insulating film are formed at the same time, and the arrival pad is formed at the same time. The opening of the region j and the opening reaching the fuse element 7. At this time, the cover layer 2 and the interlayer insulating film are removed by using the Ray%_' of the CF-based gas. Here, the junction region 1 is provided in the upper wiring layer. On the other hand, the solvus element 7 is provided on the lower wiring layer. In order to form the opening reaching the solvating element 7 in the case of forming the opening reaching the pad region 必须, it is necessary to carry out a long time engraving. Just as shown in Fig. 12, the etching is performed in an amount as indicated by the height h. At this time, the pad area is exposed to the CF-based gas for a long time after 201013776. The use of the =1 embodiment is the same. The subsequent processing is also the same as the first: 出出; The longer the C/system gas is, 3 ❹ 鲁 ===== 2 [Simplified illustration] Figure 1 shows the top view of the semiconductor wafer Port: A cross-sectional view of the surface portion of the conductor wafer. Figure 3A shows the semiconductor package 3B is a plan view showing a process of a semiconductor device. Fig. 4B is a plan view showing a process of the semiconductor device. Fig. 4B is a plan sectional view showing a process of the semiconductor device. FIG. 6B is a plan view showing a process of the semiconductor device. FIG. 7A is a plan view showing a process of the semiconductor device according to the first embodiment. FIG. Fig. 7B is a plan view showing the structure of the first embodiment according to the first embodiment. Fig. 8A shows a plan view of the device according to the second embodiment of the device. The program cross-sectional view of the process of the + conductor device of the Ding Yidi type is shown in the first embodiment. A top view of the system of semiconductors. 9 201013776 FIG. 9A is a cross-sectional view showing a process of semiconductor chipping according to the first embodiment. FIG. 9B is a plan view showing a semiconductor device according to the first embodiment. FIG. 1A shows a semiconductor chip according to the first embodiment. The If of the process is a plan view of the process of semiconductor money according to the first embodiment. The plan view shows the process of the first embodiment of the semiconductor device. Fig. 12 is a gas-surface view showing a semiconductor device according to a second embodiment. Fig. 13 is a cross-sectional view showing the semiconductor device according to the second embodiment. [Main component symbol description] 1 ~ pad area 2 ~ cover layer 3 ~ polyimine (insulating resin layer) 4 ~ anti-surname agent 5 ~ deposit 6 * ~ &lt; needle mark (wafer test needle mark)

Q 7〜熔線元件(下層露出部） h〜顯示熔線元件上多進行钱刻之量的高度 10Q 7 ~ fuse element (lower exposed part) h ~ shows the height of the amount of money on the fuse element 10

Claims (1)

201013776 七、申請專利範圍： 1. 一種半導體裝置之製造方法，具備： ，1步驟，形成具有接墊區的配線層群； 第2步驟，形成絕緣性的覆蓋層，以覆蓋該配線層群； 第3步驟’以電漿钱刻去除該覆蓋層，俾使接墊區露出； 該接墊區以鋁形成；且 該以電毁钮刻去除的步驟包含： 使用產生碳自由基及氟自由基的CF系氣體，以使該接墊 區露出的步驟；及 ❹ 參 於雜出步驟後，使用產生氣自由基或氯離子的系氣 體if去除產生於該接塾區之表面的沉積物的步驟。 2. 如申，專利，圍第丨項之半導體裝置之製造方法，其中， ϋ、5亥〇2系氣體包含選自於由〇2氣體、BC13、SiC14及CC14 構成之集合的至少一種氣體。 3. 如申，專利範，第！項之半導體裝置之製造方法，其中， Αΐί α I氣體為包含CF4 1體、CHF3氣體及N2氣體的混 4.如^^範圍第1項之半導雌置之製造方法，其中， 化物ϊ的以包含氧原子及石夕原子之化合物所構成石夕氧 如=專利範圍第4項之半導體裝置之製造方法，其中， 该矽氧化物系的膜為Si0N膜。 &amp; =申請專利範圍第！項之半導體裳置之製造方法，其中，更具 緣保蓋Γ步驟後，在該覆蓋層上形成樹脂製之絕 護層峨靖，在職11之谢除該絕緣保 如申利範圍第6項之半導體裝置之製造方法，其中， 〇、、、邑緣保護層包含聚醯亞胺樹脂。 11 7. 201013776 8.如申請專利範圍第丨項之半導體 成配線層群的步驟包含： 方法，其中，該形 下層露出部之下部配線層的步驟；及 上部配線層的步驟； 联肜成具有該接墊區之 該使接墊區露出的步驟包含：餘 膜’以使該接塾區與該下層露出部兩以間絕緣 如申請專利範圍第8項之半導體裝置之製造 10.如申請專利範ϋ第8或9狀半導體裝置 該層間絕緣獏包含si0N膜。 表k方法 其中 Q 八、圖式 12201013776 VII. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising: a step of forming a wiring layer group having a pad region; and a second step, forming an insulating cover layer to cover the wiring layer group; In the third step, the cover layer is removed by plasma money, and the pad area is exposed; the pad area is formed of aluminum; and the step of removing the electrode by electro-destruction includes: using carbon radicals and fluorine radicals a CF-based gas for exposing the pad region; and a step of removing the deposit generated on the surface of the interface region using a gas gas if or generating a gas radical or chloride ion after the impurity step . 2. The method of manufacturing a semiconductor device according to the invention, wherein the ϋ, 5 〇 〇 2 series gas comprises at least one gas selected from the group consisting of 〇2 gas, BC13, SiC14, and CC14. 3. Such as Shen, patent model, the first! The manufacturing method of the semiconductor device of the present invention, wherein the Αΐί α I gas is a mixture comprising a CF4 1 body, a CHF 3 gas, and a N 2 gas. 4. The method for manufacturing a semiconductor device according to the first item of the first aspect, wherein A method for producing a semiconductor device according to the fourth aspect of the invention, wherein the yttrium oxide-based film is a SiO 2 film. &amp; = patent application scope! The manufacturing method of the semiconductor skirt of the item, in which the sealing layer of the resin is formed on the cover layer after the step of covering the cover, the employee 11 is removed from the insulation. A method of manufacturing a semiconductor device, wherein the ruthenium, and the ruthenium edge protective layer comprise a polyimide resin. 11 7. The method of claim 13, wherein the step of the semiconductor wiring layer group according to the scope of the patent application includes: a method of: forming a wiring layer under the lower portion of the lower layer; and a step of the upper wiring layer; The step of exposing the pad region of the pad region includes: a residual film 'to make the junction region and the lower layer exposed portion to be insulated. The semiconductor device of claim 8 is applied for. The interlayer insulating material of the 8th or 9th semiconductor device includes a si0N film. Table k method where Q VIII, schema 12
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TWI794238B (en) * 2017-07-13 2023-03-01 荷蘭商Ａｓｍ智慧財產控股公司 Apparatus and method for removal of oxide and carbon from semiconductor films in a single processing chamber

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WO2015146023A1 (en) * 2014-03-25 2015-10-01 株式会社Ｊｏｌｅｄ Etching method and organic el display panel manufacturing method using same
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Publication number Priority date Publication date Assignee Title
TWI794238B (en) * 2017-07-13 2023-03-01 荷蘭商Ａｓｍ智慧財產控股公司 Apparatus and method for removal of oxide and carbon from semiconductor films in a single processing chamber

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