JP2010002675A - Display and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display for enhancing image quality by forming a pixel electrode without being affected by a semiconductor layer, while provided with the semiconductor layer divided by film formation on a partitioning wall and patterned finely. <P>SOLUTION: This display formed arrayedly, on a substrate 3, with a thin film transistor Tr and a transparent pixel electrode 23 connected thereto, includes an insulating partitioning layer 15, on the substrate 3 formed with a source/drain 13sd of the thin film transistor, and the partitioning layer includes the first opening 15a in a position corresponding to a channel part of the thin film transistor, and includes the second opening 15b in a position corresponding to a forming area of the transparent pixel electrode. The first opening bottom part includes a channel part semiconductor layer 17ch constituting an active layer of the thin film transistor, and the semiconductor layer 17 of the second opening bottom part is removed. The transparent pixel electrode 23 is provided overlappedly with the second opening, on an insulating film 21 for covering an upper side of the substrate formed with the partitioning layer and the semiconductor layer 17. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention particularly relates to a display device including a thinly patterned semiconductor layer and a manufacturing method thereof.

  A thin film transistor is widely used as a pixel transistor in an electronic circuit, particularly in an active matrix driving flat display device. In recent years, attention has been paid to using an organic material as a semiconductor layer used in such a thin semiconductor device. A semiconductor device in which an organic material is used for a semiconductor layer can form a semiconductor layer at a lower temperature than a structure in which an inorganic material is used for a semiconductor layer. For this reason, it is advantageous for increasing the area, and can be formed on a flexible substrate having no heat resistance such as plastic, and it is expected to reduce the cost as well as increase the number of functions.

  In order to pattern the semiconductor layer made of an organic material, for example, a printing method or a vapor deposition method using a metal mask is performed. In addition to this, after forming an organic material layer on the resist pattern, a method of selectively lift-off removing the organic semiconductor layer portion on the resist pattern together with the resist pattern, and a method of pattern etching the semiconductor layer using the resist pattern as a mask Etc. are performed.

  However, the printing method and the vapor deposition method using a metal mask have a limit in pattern definition. In particular, in the vapor deposition method using a metal mask, it is difficult to form a pattern with good positional accuracy on a large-area substrate. Furthermore, in the method using a resist pattern, the resist stripping solution used for removing the resist pattern also damages the organic semiconductor layer, resulting in an increase in leakage current in the organic semiconductor layer, a decrease in mobility, and a threshold shift. There was a problem.

  Therefore, a partition wall (patterned insulating layer) having a large level difference is formed on the substrate on which the semiconductor layer is formed, and a semiconductor layer is formed on the partition wall so that the pattern shape is divided between the lower part and the upper part of the partition wall. A method for forming a semiconductor layer has been proposed. In this case, for example, a source / drain pattern is formed on a gate insulating film covering the gate electrode, and a partition is formed thereon. Then, a semiconductor layer serving as a channel portion is formed between the source / drain in the lower part in a state where the semiconductor layer is separated from the semiconductor layer on the upper part of the partition by forming the semiconductor layer on the partition (see Patent Document 1 and Patent Document 1 below). Non-patent document 1).

  In a liquid crystal display device in which a thin film transistor including the semiconductor layer is a pixel transistor, a pixel electrode is provided on the gate insulating film in the same layer as the source / drain or in a different layer in a state of being connected to the source / drain. Keep it. Thereafter, as described above, partition walls are formed on the source / drain and the pixel electrode, and a semiconductor layer serving as a channel portion is formed between the source / drain by forming a semiconductor layer on the partition walls. Then, an alignment film is formed through an insulating protective film so as to cover them, and a liquid crystal layer is sandwiched between the opposing substrate (similarly, see Patent Document 1 below).

JP 2000-269504 A (refer to FIG. 1, FIG. 6 and related descriptions in particular) Stijn De Vusser et al, “Integrated shodow mask method for patterning small molecule organic semiconductor”, “Applied Physics Letters 88”, 2006 American Institute of physics, 2006, 103501-1–103501-3.

  However, in the liquid crystal display device having the configuration disclosed in Patent Document 1 as described above, the partition walls and the semiconductor layer are overlaid on the pixel electrodes. Therefore, the display light is transmitted through the semiconductor layer and the partition wall, and the transmitted light is colored due to the presence of the semiconductor layer and the partition wall, thereby affecting the hue of the image quality.

  Even when the pixel electrode connected to the thin film transistor is drawn out on the protective film, since the semiconductor layer is provided on the entire surface under the protective film, coloring of the transmitted light by the semiconductor layer is inevitable.

  Therefore, the present invention avoids coloring of transmitted light by a semiconductor layer while having a semiconductor layer that is divided and patterned by film formation from above a partition wall, thereby improving the display quality and its display device. An object is to provide a manufacturing method.

  In order to achieve such an object, a display device according to the present invention is a display device in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged on a substrate, and the substrate on which the source / drain of the thin film transistor is formed. An insulating partition layer is provided thereon. In the partition layer, a first opening is provided at a position corresponding to the channel portion of the thin film transistor, and a second opening is provided at a position corresponding to the pixel electrode formation region. A channel portion semiconductor layer constituting an active layer of the thin film transistor is provided at the bottom of the first opening, while the semiconductor layer at the bottom of the second opening is removed. A pixel electrode is provided on the insulating film covering the substrate on which the partition wall layer and the semiconductor layer are formed so as to overlap the second opening.

  In the display device having such a structure, since the channel portion semiconductor layer is provided at the bottom of the first opening provided in the partition wall layer, the channel portion semiconductor layer is finely formed by forming a semiconductor layer on the partition wall layer. It is divided and patterned. In addition, the partition layer is provided with a second opening at a position overlapping the pixel electrode together with the first opening, and the semiconductor layer in the second opening is removed. It is taken out without being affected by the partition layer.

  The present invention is also a method for manufacturing the display device described above. First, a source / drain of a thin film transistor is formed on a substrate. Next, an insulating partition layer having a first opening that exposes between the end portions of the source / drain and a second opening at a position that does not overlap the source / drain is formed on the substrate. After that, a channel semiconductor layer made of the semiconductor layer is patterned at the bottom of the first opening. Next, the semiconductor layer formed at the bottom of the second opening is removed in the channel portion semiconductor layer pattern forming step. Thereafter, an insulating film is formed over the substrate so as to cover the partition layer and the semiconductor layer, and a pixel electrode is formed on the insulating film.

  As described above, according to the present invention, the channel layer semiconductor layer finely divided and patterned by the film formation from the partition wall layer is provided, but is affected by the partition wall layer and the semiconductor layer remaining on the channel layer semiconductor layer. Thus, it is possible to obtain a pixel electrode without any problem, and thereby improve the image quality of a display device having the pixel electrode.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, each embodiment in which the present invention is applied to an active matrix type liquid crystal display device will be described.

<First Embodiment>
FIG. 1 is a schematic plan view of one pixel of a driving side substrate in the display device 1-1 of the first embodiment, in which a bottom gate type thin film transistor is used as a thin film transistor Tr for driving a pixel. 2 is a schematic cross-sectional view of the display device 1-1 shown in FIG. 1, and corresponds to the AA ′ cross-section in FIG. Hereinafter, the configuration of the display device 1-1 of the first embodiment will be described based on these drawings.

  The display device 1-1 according to the first embodiment includes a scanning line 5 and a common wiring 7 (on a plan view only) on a first layer on a substrate 3 having transparency to visible light (hereinafter referred to as light transparency). Are wired in the horizontal direction. From each scanning line 5, the gate electrode 5 g of the thin film transistor Tr extends in the vertical direction toward the common wiring 7 side. Further, the intermediate portion of each common wiring 7 is patterned as the lower electrode 7c of the capacitive element Cs.

  A light transmissive gate insulating film 9 (shown only in a cross-sectional view) is provided in a state of covering the scanning line 5 and the common wiring 7 as described above.

  In the second layer on the gate insulating film 9, a plurality of signal lines 13 (shown only in the plan view) are arranged perpendicular to the scanning lines 5 and the common wiring 7.

  From each signal line 13, one source / drain 13sd of the thin film transistor Tr extends in the horizontal direction toward the gate electrode 5g. The other source / drain 13sd disposed with the gate electrode 5g interposed therebetween also serves as the upper electrode of the capacitive element Cs, and is disposed so as to extend over the lower electrode 7c via the gate insulating film 9. These laminated portions are configured as a capacitive element Cs.

  An insulating partition layer 15 is provided on the substrate 3 on which the signal line 13 and the source / drain 13sd are formed. The partition layer 15 has a first opening 15a at a position corresponding to the channel portion of the thin film transistor Tr, that is, between the source / drain 13sd-13sd and on the gate electrode 5g. The partition layer 15 is provided with a first opening 15a, a second opening 15b that opens widely on the substrate 3, and a third opening 15c that reaches the source / drain 13sd constituting the capacitive element Cs. . The second opening 15b and the third opening 15c may be separated from the first opening 15a.

  In addition, it is important that the partition layer 15 is configured such that a semiconductor layer 17 described below is divided at an upper portion and a lower portion of the partition layer 15. Such a partition layer 15 has a film thickness sufficiently thicker than that of the semiconductor layer 17, and the side walls of the first opening 15a, the second opening 15b, and the third opening 15c are vertical or more preferably open. Suppose that it is the reverse taper shape inclined so that an opening diameter may become narrow toward the upper part.

  The side wall shape (cross-sectional shape) of the partition wall layer 15 may be an inversely tapered shape in which the inclination angle is maintained substantially uniform as illustrated. Further, in the partition layer 15 formed of a laminated film, the lower layer film may have a wider opening width. Furthermore, the shape of the semiconductor layer 17 to be described below is not limited as long as the semiconductor layer 17 is divided into an upper part and a lower part of the partition wall layer 15.

  At the bottom of the first opening 15a of the partition layer 15, a channel semiconductor layer 17ch constituting an active layer of the thin film transistor Tr is provided. Then, the gate electrode 5g, the source / drain 13sd disposed on both sides of the gate electrode 5g via the gate insulating film 9, and the channel portion stacked on the gate electrode 5g in contact with the source / drain 13sd A thin film transistor Tr is constituted by the semiconductor layer 17ch.

  The channel portion semiconductor layer 17ch is composed of a semiconductor layer 17 (shown only in a cross-sectional view) formed from above the partition layer 15, and is separated from the semiconductor layer 17 on the partition layer 15 in the first opening 15a. At the bottom. The semiconductor layer 17 at the bottom of the second opening 15b is removed in a wide range.

  On the substrate 3 provided with the channel portion semiconductor layer 17ch and the partition wall layer 15 as described above, the first insulating film 19 shown only in the sectional view is provided. The first insulating film 19 serves as a protective film for the channel semiconductor layer 17ch. The first insulating film 19 is provided with a first connection hole 19a reaching the source / drain 13sd constituting the upper electrode of the capacitive element Cs in the third opening 15c. It is assumed that the semiconductor layer 17 at the bottom of the first connection hole 19a is also removed.

  Further, the first insulating film 19 may be provided with an opening window 19b from which a portion overlapping the second opening 15b of the partition wall layer 15 is removed in a wide range.

  On the substrate 3 on which the first insulating film 19 is provided, a second insulating film 21 is provided so as to cover the entire surface of the substrate 3. It is important that the second insulating film 21 is made of a light transmissive material. For example, the second insulating film 21 may be provided as a planarizing insulating film. In the second insulating film 21, a second connection hole 21 a reaching the source / drain 13 sd is formed in the first connection hole 19 a provided in the first insulating film 19. The second connection hole 21 a is provided with insulation against the semiconductor layer 17 on the partition wall 15.

  On the second insulating film 21, a transparent pixel electrode 23 connected to the source / drain 13sd through the second connection hole 21a is provided. The transparent pixel electrode 23 is light transmissive made of a transparent conductive material, and is provided in a wide range within each pixel set at each intersection of the scanning line 5 and the signal line 13, and on the second opening 15b. It is assumed that the pattern is formed so as to cover the surface.

  An alignment film 25 is provided above the substrate 3 so as to cover the transparent pixel electrode 23, and the upper portion of the substrate 3 on the driving side is configured.

  In the configuration described above, it is assumed that the layer formed on the transparent pixel electrode 23 and the substrate 3 have a visible light transmittance as good as possible.

  On the other hand, the counter substrate 31 illustrated only in the cross-sectional view is provided on the surface on which the transparent pixel electrode 23 is formed on the driving-side substrate 3 as described above. The counter substrate 31 is made of a light transmissive material, and a light transmissive common electrode 33 made of a transparent conductive material common to all pixels is provided on the surface facing the transparent pixel electrode 23. An alignment film 35 is provided in a covered state. A liquid crystal layer LC is sandwiched between the alignment films 25-35 of the two substrates together with a spacer (not shown).

  And the display apparatus 1-1 is comprised by arrange | positioning the deflection | deviation plate which abbreviate | omitted here here on the outer side of the board | substrate 3, and the outer side of the opposing board | substrate 31. FIG.

  In such a display device 1-1, the light incident from the substrate 3 side through the deflection plate passes through the transparent pixel electrode 23 and reaches the liquid crystal layer LC. Then, only the light that has become a predetermined deflection state by passing through the liquid crystal layer LC that has been orientated according to the voltage application state to the transparent pixel electrode 23 and the common electrode 33 passes through the deflection plate on the counter substrate 31 side. And is taken out as display light.

  Next, a manufacturing method of such a display device 1-1 will be described based on the sectional process diagram of FIG.

  First, as shown in FIG. 3A, a light-transmitting substrate 3 is prepared. The substrate 3 is not limited to a material such as plastic or glass, and may be a glass substrate or a plastic substrate on which an insulating protective film or the like is formed. However, it is preferable that the visible light transmittance is good (80% or more). In the case where the display device manufactured here is a flexible display, it is preferable to use a plastic substrate.

  On the substrate 3, together with the first-layer gate electrode 5g and the lower electrode 7c, scanning lines and common wirings not shown here are formed. Known techniques and materials can be applied to the formation of these electrodes and wirings, and these are not limited. For example, it is preferable to apply a lithography method in order to form finer electrodes and wirings. In this case, for example, pattern etching is performed using, as a mask, a resist pattern in which the formed electrode material layer is formed by lithography. As the electrode material layer, for example, aluminum (Al), gold (Au), a laminated film of gold (Au) and chromium (Cr), silver (Ag), palladium (Pd), or a laminated film of these is used. However, it is not limited to these.

  Next, a light transmissive gate insulating film 9 is formed on the substrate 3 so as to cover the gate electrode 5g and the lower electrode 7c. The gate insulating film 9 can be formed by using known techniques and materials such as inorganic material films such as silicon oxide and silicon nitride, and organic material films such as polyvinylphenol and polymethyl methacrylate (PMMA). However, these are not limited.

  Next, the source / drain 13 sd and the signal line are formed in the second layer on the gate insulating film 9. For forming these electrodes and wirings, known techniques and materials can be applied. For example, they are formed in the same manner as the gate electrode 5g and the lower electrode 7c of the first layer. As a result, a capacitive element Cs is obtained in which the gate insulating film 9 is sandwiched between the lower electrode 7c and one source / drain 13sd.

  Next, the partition wall layer 15 including the first opening 15a, the second opening 15b, and the third opening 15c each having a sidewall reverse taper shape is formed on the gate insulating film 9 in which the source / drain 13sd is formed. The formation positions of the openings 15a, 15b, and 15c are as described with reference to FIGS. 1 and 2, and the first opening 15a is formed on the gate electrode 5g, and the first opening 15a is wide open on the substrate 3. The second opening 15b is formed, and the third opening 15c is formed so as to reach the source / drain 13sd constituting the capacitive element Cs.

  Examples of a method for producing such a partition layer 15 include a method of producing by photo-patterning using a photosensitive resin, and a method of producing by combining the formation of an insulating thin film and etching. As the insulating thin film, for example, a resin such as PMMA, or an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) is used, but the material is not limited to these, and known materials can be widely used. .

  For example, in the case of the inversely tapered partition wall layer 15 in which the inclination angles of the side walls of the openings 15a, 15b, and 15c are kept substantially uniform, lithography is performed by adjusting the exposure conditions using a photosensitive resin. Thereby, the partition wall layer 15 having the openings 15a, 15b, and 15c whose side walls are reversely tapered is formed. Moreover, the partition wall layer 15 having a multilayer structure can be manufactured by the same method. For example, when this is realized by using a photosensitive resin, a difference in photosensitivity may be provided between the first lower layer film and the second upper layer film. Alternatively, a photosensitive resin may be used for the second layer, and a material that can be selectively patterned with respect to the second layer of the photosensitive resin may be used for the first layer. Further, when the formation of the insulating thin film and etching are used in combination, the first layer and the second layer may have etching selectivity.

  After the partition wall layer 15 is formed as described above, a semiconductor layer 17 is formed from above the partition wall layer 15 so as to be separated from the partition wall layer 15 as shown in FIG. A channel portion semiconductor layer 17ch made of the semiconductor layer 17 is formed at the bottom of the first opening 15a. Here, for example, the semiconductor layer 17 is formed on the entire surface of the substrate 3 by vacuum evaporation. As a result, the semiconductor layer 17 having a shape separated from the semiconductor layer 17 on the partition wall layer 15 is also provided at the bottom of the second opening 15b and the third opening 15c.

  The semiconductor layer 17 is made of, for example, a thiophene oligomer such as pentacene or zexithiophene, or an organic semiconductor such as polythiophene. In the case of using a method such as an ink jet method that allows patterning and film formation at the same time, the semiconductor layer 17 is selectively formed only on the bottom surface of the first opening 15a in the partition wall layer 15, and this is used as the channel semiconductor layer 17ch. Also good.

  As described above, the source / drain 13sd is provided on the gate insulating film 9 covering the gate electrode 5g, and the channel part semiconductor layer 17ch is provided above the source / drain 13sd and above the gate electrode 5g. A bottom gate / bottom contact type thin film transistor Tr is obtained. In the thin film transistor Tr, one source / drain 13sd is used as the upper electrode of the capacitive element Cs.

  Next, as shown in FIG. 3 (3), a first insulating film 19 is formed so as to cover the partition layer 15 and the semiconductor layer 17. The first insulating film 19 may be formed without embedding a step due to the partition wall layer 15 as shown, or may be formed as a planarized flat film. In the case where the surface of the first insulating film 19 is an uneven surface, it is preferable that the first insulating film 19 is composed of sidewalls obtained by converting the reverse tapered shape of the sidewalls of the openings 15a, 15b, 15c in the partition wall layer 15 into a forward tapered shape. . The first insulating film 19 may have a single layer structure or a laminated structure.

  Such a first insulating film 19 is made of, for example, an acrylic resin such as silicon nitride, silicon oxide, polyparaxylylene, polyvinyl alcohol, polyvinylphenol, PMMA, or the like, but is not limited thereto and is publicly known. These materials can be widely used.

  Next, the first insulating film 19 is pattern-removed inside the third opening 15c of the partition wall layer 15 to form a first connection hole 19a, and the first insulating film 19 is patterned-opened inside the second opening 15b. Windows 19b are formed, and the semiconductor layer 17 is exposed in these portions.

  Here, the first insulating film 19 may be formed in a shape including the first connection hole 19a and the opening window 19b by a printing method or the like.

  Next, the semiconductor layer 17 at the bottom of the first connection hole 19a and the bottom of the opening window 19b is formed by etching using the resist pattern used for pattern removal of the first insulating film 19 or the first insulating film 19 itself as a mask. Remove. At this time, the gate insulating film under the semiconductor layer may be continuously etched away after the semiconductor layer. This is effective, for example, when the visible light transmittance is reduced by the gate insulating film. In this case, the visible light transmittance can be improved by removing the gate insulating film.

  Next, as shown in FIG. 3 (4), the second insulating film 21 is formed so as to cover the first insulating film 19. The second insulating film 21 is preferably formed as a flattened film having a flat surface as shown.

  Such a second insulating film 19 is made of, for example, an acrylic resin such as silicon nitride, silicon oxide, polyparaxylylene, polyvinyl alcohol, polyvinylphenol, PMMA, or the like, but is not limited thereto and is publicly known. These materials can be widely used. The second insulating film 19 may have a single layer structure or a laminated structure.

  Next, in the first connection hole 19a provided in the first insulating film 19, the second insulating film 21 is patterned, and the second connection hole 21a reaching the source / drain 13sd constituting the upper electrode of the capacitive element Cs. Form. At this time, it is important that the second connection hole 21 a is kept insulated from the semiconductor layer 17 on the partition wall layer 15.

  Here, the second insulating film 21 may be formed in a shape having the second connection hole 21a by a printing method or the like.

  Thereafter, as shown in FIG. 3 (5), the transparent pixel electrode 23 connected to the source / drain 13 sd through the second connection hole 21 a is formed on the second insulating film 21. Next, the alignment film 25 is formed above the substrate 3 so as to cover the transparent pixel electrode 23, thereby completing the substrate 3 on the driving side (that is, the back plane of the display device).

  Thereafter, as shown in FIG. 2, a common electrode 33 and an alignment film 35 made of a transparent conductive material are sequentially formed on the counter substrate 31 made of a transparent material. Then, the substrate 3 and the counter substrate 31 are arranged to face each other with the alignment films 25 and 35 facing each other, and a spacer (not shown) is sandwiched between the substrates 3-31 to inject and seal the liquid crystal layer LC. Thus, the transmissive liquid crystal display device 1-1 is completed.

  In the first embodiment described above, the channel semiconductor layer 17ch is provided at the bottom of the first opening 15a while being separated from the partition layer 15 by film formation from the partition layer 15. For this reason, the channel semiconductor layer 17ch can be finely divided and patterned. In addition, the partition layer 15 is provided with the first opening 15a and the second opening 15b at a position overlapping the transparent pixel electrode 23, and the semiconductor layer 17 formed at the bottom of the second opening 15b is removed. The light transmitted through the transparent pixel electrode 23 can be extracted without being affected by the semiconductor layer 17 and the partition wall layer 15.

  As a result, the display light is not affected by the partition layer 15 or the semiconductor layer 17 remaining above the channel layer semiconductor layer 17ch that is finely divided and patterned by film formation from the partition layer 15. Thus, the image quality of the display device 1-1 having the transparent pixel electrode 23 can be improved.

Second Embodiment
FIG. 4 is a schematic cross-sectional view of the display device 1-2 of the second embodiment, and corresponds to the AA ′ cross section in FIG. The display device 1-2 shown in this figure is different from the display device of the first embodiment described with reference to FIG. 2 in that a reflective pixel electrode 27 is provided together with the transparent pixel electrode 23 to obtain a transflective display. However, the other configurations are the same.

  That is, the reflective pixel electrode 27 is provided in the same layer as the transparent pixel electrode 23 and connected to the transparent pixel electrode 23. Here, for example, the reflective pixel electrode 23 may be connected to the source / drain 13sd through the second connection hole 21a.

  Even in the second embodiment described above, the channel portion semiconductor layer 17ch is provided at the bottom of the first opening 15a formed in the partition wall layer 15, and the first layer 15 is formed at a position overlapping the transparent pixel electrode 23 of the partition layer 15. Since the semiconductor layer 17 formed at the bottom of the second opening 15b is removed because the two openings 15b are provided, the semiconductor layer 17ch is provided with a fine channel semiconductor layer 17ch as in the first embodiment. Display light can be obtained without being affected by the layer 17.

  Further, since the transflective display in which the reflective pixel electrode 27 is provided together with the transparent pixel electrode 23, the portion where the structure is formed in the lower layer can also be used as the pixel portion for performing the reflective display.

<Third Embodiment>
FIG. 5 is a schematic cross-sectional view of a display device 1-3 according to the third embodiment. The display device 1-3 shown in this figure is different from the display device of the second embodiment described with reference to FIG. 4 in that a shield layer 29 is disposed between the channel semiconductor layer 17ch and the reflective pixel electrode 27. The other configurations are the same.

  That is, the shield layer 29 is made of a conductive material, and is provided in a state sandwiched between the first insulating film 19 and the second insulating film 21 at a position where it is stacked on the channel portion semiconductor layer 17ch.

  A manufacturing method of a display device including such a shield layer 29 is such that after the first insulating film 19 is formed and before the second insulating film 21 is formed, the shield layer is formed on the first insulating film 19. The process for forming 29 is performed. The method for forming the shield layer 29 is not particularly limited, and is performed, for example, in the same manner as the formation of the gate electrode 5g and the lower electrode 7c.

  In the display device 1-3 of the third embodiment having such a configuration, in addition to the effects of the second embodiment, the shield layer 29 is provided between the reflective pixel electrode 27 and the channel part semiconductor layer 17ch, thereby It is possible to suppress a so-called back channel effect in which the potential of the pixel electrode 27 affects the channel part semiconductor layer 17ch. Thereby, the effect of reducing the operating voltage of the thin film transistor Tr can be obtained.

<Fourth embodiment>
FIG. 6 is a schematic cross-sectional view of a display device 1-4 according to the fourth embodiment. The display device 1-4 shown in this figure is different from the display device of the third embodiment described with reference to FIG. 5 in that a channel portion is provided in a configuration in which only a transparent pixel electrode 23 is provided without providing a reflective pixel electrode. The shield layer 29 is disposed between the semiconductor layer 17ch and the transparent pixel electrode 27, and other configurations are the same as those in the third embodiment.

  Even in such a configuration, the shield layer 29 is provided between the transparent pixel electrode 23 and the channel part semiconductor layer 17ch, so that the potential of the transparent pixel electrode 23 affects the channel part semiconductor layer 17ch. The back channel effect can be suppressed. Thereby, the effect of reducing the operating voltage of the thin film transistor Tr can be obtained. Further, when the shield material is made of a reflective material, reflective display is possible in the region above the shield electrode, and a transflective display can be obtained. In this case, it is advantageous that a display similar to that of the third embodiment can be obtained even though one process is reduced compared to the third embodiment.

<Fifth Embodiment>
FIG. 7 is a schematic plan view for one pixel of the driving side substrate in the display device 1-5 of the fifth embodiment to which the present invention is applied. A top gate type thin film transistor Tr ′ is used as a thin film transistor for driving a pixel. Is. 8 corresponds to the AA ′ cross section in FIG. The configuration of the display device 1-5 of the fifth embodiment will be described below based on these drawings. In addition, the same code | symbol is attached | subjected and demonstrated to the same component as previous embodiment.

  In the display device 1-5 shown in these drawings, a plurality of signal lines 13 are wired in the vertical direction on the first layer on the substrate 3 on the driving side. From each signal line 13, one source / drain 13sd of the thin film transistor Tr 'extends in the horizontal direction. In the first layer, the other source / drain 13 sd that also serves as the lower electrode of the capacitive element Cs is provided to face the source / drain 13 sd extending from the signal line 13.

  A partition wall layer 15 similar to that of the first embodiment is provided on the substrate 3 on which the signal line 13 and the source / drain 13sd as described above are formed. The partition layer 15 has a first opening 15a, a second opening 15b, and a third opening 15c (shown only in a plan view) similar to those of the first embodiment, and on the source / drain 13c constituting the capacitive element Cs. A fourth opening 15d that opens is provided.

  That is, the first opening 15a is provided at a position corresponding to the channel portion of the thin film transistor Tr ', that is, a position corresponding to between the source / drains 13sd-13sd. The second opening 15b is provided so as to open widely over the substrate 3. The third opening 15c and the fourth opening 15d are provided at a position reaching the source / drain 13sd on the side constituting the lower electrode of the capacitive element Cs in the source / drain 13sd of the thin film transistor Tr '. It is important that the third opening 15c and the fourth opening 15d are provided independently.

  Further, as in the first embodiment, the partition layer 15 has such a film thickness that a semiconductor layer 17 to be described below is divided at an upper portion and a lower portion of the partition layer 15, and further, an opening 15a. , 15b, 15c, and 15d are vertical or more preferably inversely tapered so that the opening diameter becomes narrower toward the upper part of the opening.

  At the bottom of the first opening 15 a of the partition layer 15, a channel part semiconductor layer 17 ch constituting the active layer of the thin film transistor Tr ′ is provided. The channel portion semiconductor layer 17ch is composed of a semiconductor layer 17 (shown only in a cross-sectional view) formed from above the partition layer 15, and is separated from the semiconductor layer 17 on the partition layer 15 in the first opening 15a. At the bottom. The semiconductor layer 17 at the bottom of the second opening 15b is removed in a wide range. On the other hand, the semiconductor layer 17 is provided on the source / drain 13sd at the bottom of the fourth opening 15d.

  The gate insulating film 9 (shown only in the cross-sectional view) is provided so as to cover the channel portion semiconductor layer 17ch and the semiconductor layer 17 in the fourth opening 15d as described above. The gate insulating film 9 is removed in a wide range at the bottom of the second opening 15b.

  On the gate insulating film 9, the scanning line 5 and the common wiring 7 illustrated only in the plan view are wired in a direction (horizontal direction) perpendicular to the signal line 13.

  From each scanning line 5, the gate electrode 5 g of the thin film transistor Tr ′ is extended to a position overlapping the channel semiconductor layer 17 ch between the source / drain 13 sd. A pair of source / drains 13sd, a channel part semiconductor layer 17ch provided between the source / drains 13sd, and a gate electrode 5g provided on the channel part semiconductor layer 17ch via the gate insulating film 9 A top gate type thin film transistor Tr ′ is formed.

  Further, the intermediate portion of each common wiring 7 is patterned as the upper electrode 7c 'of the capacitive element Cs. The upper electrode 7c 'is disposed so as to overlap the fourth opening 15d. Then, at the bottom of the fourth opening 15d, a capacitive element Cs is formed in which the gate insulating film 9 and the semiconductor layer 17 are sandwiched between the source / drain 13sd also serving as the lower electrode and the upper electrode 7c ′. ing.

  On the substrate 3 provided with the channel part semiconductor layer 17ch and the partition wall layer 15 as described above, the insulating film 19 shown only in the sectional view is provided. The insulating film 19 is provided with a connection hole 19a (see a plan view) reaching the source / drain 13sd constituting the lower electrode of the capacitive element Cs in the third opening 15c. It is assumed that the semiconductor layer 17 at the bottom of the connection hole 19a is also removed.

  On such an insulating film 19, a transparent pixel electrode 23 connected to the source / drain 13sd through the connection hole 19a is provided. The transparent pixel electrode 23 is light transmissive made of a transparent conductive material, and is provided in a wide range within each pixel set at each intersection of the scanning line 5 and the signal line 13, and on the second opening 15b. It is assumed that the pattern is formed so as to cover the surface.

  An alignment film 25 is provided above the substrate 3 so as to cover the transparent pixel electrode 23, and the upper portion of the substrate 3 on the driving side is configured.

  In the configuration described above, it is assumed that the layer formed on the transparent pixel electrode 23 and the substrate 3 have a visible light transmittance as good as possible.

  On the other hand, a counter substrate 31 (shown only in a cross-sectional view) similar to that of the first embodiment is provided on the formation side of the transparent pixel electrode 23 in the substrate 3 on the driving side as described above. That is, the counter substrate 31 is made of a transparent material, and a common electrode 33 made of a transparent conductive material common to all the pixels is provided on the surface facing the transparent pixel electrode 23, and the alignment film covers the common electrode 33. 35 is provided. A liquid crystal layer LC is sandwiched between the alignment films 25-35 of the two substrates together with a spacer (not shown).

  The display device 1-5 is configured as described above. In the display device 1-5, the same transmissive display as in the first embodiment is performed.

  Next, a method of manufacturing such a display device 1-5 will be described based on the sectional process diagram of FIG.

  First, as shown in FIG. 9A, a light-transmitting substrate 3 is prepared, and a signal line is formed on the upper portion together with a source / drain 13sd. The formation of these electrodes and wiring is the same as in the first embodiment, and known techniques and materials can be applied, and these are not limited.

  Next, on the substrate 3 on which the source / drain 13sd is formed, a partition wall layer having a first opening 15a, a second opening 15b, a third opening (not shown) having a reverse sidewall taper shape, and further a fourth opening 15d. 15 is formed. The formation positions of the openings 15a, 15b, (15c,) 15d are as described with reference to FIGS. 7 and 8, and the formation method may be the same as in the first embodiment.

  After that, as shown in FIG. 9B, a semiconductor layer 17 is formed from above the partition layer 15, so that the semiconductor layer 17 is separated from the partition layer 15 at the bottom of the first opening 15a. A channel portion semiconductor layer 17ch is formed. The method for forming the semiconductor layer 17 may be the same as in the first embodiment.

  Next, as illustrated in FIG. 9C, the gate insulating film 9 is formed so as to cover the partition layer 15 and the semiconductor layer 17. This gate insulating film 9 is formed in the same manner as in the first embodiment. Next, the gate insulating film 9 is pattern-removed in a wide range at the bottom of the second opening 15b and the third opening 15c of the partition wall layer 15.

  Here, the gate insulating film 9 may be formed in advance by a printing method or the like so that the bottom of the second opening 15b is wide open.

  Next, the semiconductor layer 17 at the bottom of the second opening 15b and the third opening 15c is removed in a wide range by etching using the resist pattern used for removing the pattern of the gate insulating film 9 or the gate insulating film 9 itself as a mask. To do.

  After the above, as shown in FIG. 9 (4), a scanning line and a common wiring are formed on the gate insulating film 9 together with the gate electrode 5g and the upper electrode 7c '. Known techniques and materials can be applied to the formation of these electrodes and wirings. Alternatively, after the gate electrode 5g and the upper electrode 7c 'are formed on the gate insulating film 9, the gate insulating film 9 and the semiconductor layer 17 may be removed by pattern at the bottom of the second opening 15b.

  As described above, the top gate / bottom contact type thin film transistor Tr ′ in which the gate electrode 5g is provided via the gate insulating film 9 on the channel portion semiconductor layer 17ch provided between the pair of source / drains 13sd. obtain. Further, a capacitive element in which the gate insulating film 9 and the semiconductor layer 17 are sandwiched between the source / drain 13sd also serving as the lower electrode and the upper electrode 7c ′ at the bottom of the fourth opening 15d in the partition wall layer 15. Get Cs.

  Thereafter, as shown in FIG. 9 (5), an insulating film 19 is formed above the substrate 3 so as to cover the thin film transistor Tr ′ and the capacitor element Cs. The insulating film 19 may be formed as a flat surface flattened film as illustrated, or may be formed without embedding a step due to the partition wall layer 15. When the surface of the insulating film 19 is a concavo-convex surface, it is preferable that the insulating film 19 is composed of sidewalls obtained by converting the reverse tapered shape of the sidewalls of the openings 15a, 15b, and 15c into the forward tapered shape. The insulating film 19 may have a single layer structure or a laminated structure.

  Such an insulating film 19 is made of, for example, an acrylic resin such as silicon nitride, silicon oxide, polyparaxylylene, polyvinyl alcohol, polyvinyl phenol, PMMA, or the like, but is not limited thereto, and a known material is used. It can be widely used.

  Next, although not shown here, the first insulating film 19 is patterned at the bottom of the third opening (15c) of the partition wall layer 15 to form a connection hole (19a). Here, the insulating film 19 may be formed in a shape having the connection hole (19a) by a printing method or the like.

  In addition, after the connection hole 19a is formed, the pattern of the insulating film 19 and the semiconductor layer 17 at the bottom of the connection hole may be removed.

  Thereafter, the transparent pixel electrode 23 connected to the source / drain 13sd through the connection hole (19a) is formed on the insulating film 19. Next, the alignment film 25 is formed above the substrate 3 so as to cover the transparent pixel electrode 23, thereby completing the substrate 3 on the driving side (that is, the back plane of the display device).

  Thereafter, as shown in FIG. 8, a common electrode 33 and an alignment film 35 made of a transparent conductive material are sequentially formed on the counter substrate 31 made of a transparent material. Then, the substrate 3 and the counter substrate 31 are arranged to face each other with the alignment films 25 and 35 facing each other, and a spacer (not shown) is sandwiched between the substrates 3-31 to inject and seal the liquid crystal layer LC. Thus, the transmissive liquid crystal display device 1-5 is completed.

  Even in the fifth embodiment described above, the channel portion semiconductor layer 17ch is provided at the bottom of the first opening 15a formed in the partition layer 15, and the first portion of the partition layer 15 overlaps the transparent pixel electrode 23. Since the semiconductor layer 17 formed at the bottom of the second opening 15b is removed because the two openings 15b are provided, the semiconductor layer is provided with the fine channel portion semiconductor layer 17ch as in the first embodiment. The display light can be obtained without being affected by 17.

<Sixth Embodiment>
FIG. 10 is a schematic plan view of one pixel of the driving side substrate in the display device 1-6 according to the sixth embodiment to which the present invention is applied, and an IPS using a bottom gate type thin film transistor Tr as a pixel driving thin film transistor. This is a liquid crystal display device in (In-Plane-Switching) mode. FIG. 11 is a schematic cross-sectional view of a display device 1-6 according to the sixth embodiment, corresponding to the AA ′ cross-section in FIG. In addition, the same code | symbol is attached | subjected and demonstrated to the same component as previous embodiment.

  The display device 1-6 shown in these figures differs from the display device 1-1 of the first embodiment in that a common electrode 33 is provided in the same layer as the transmissive display electrode (for example, a transparent electrode) 23. The common electrode 33 is not provided on the counter substrate 31 side, and the other configurations are the same. On the substrate 3, the common wiring 7a connected to the common electrode 33 may be provided separately from the common wiring 7 also serving as the lower electrode 7c of the capacitive element Cs. In this case, for example, the common wiring 7a Are formed in the same layer as the common wiring 7 which also serves as the gate electrode 5 and the lower electrode 7c of the capacitive element Cs.

  That is, in the sixth embodiment, the transmissive display electrodes 23 and the common electrodes 33 are alternately arranged in parallel on the laminated film of the first insulating film 19 and the second insulating film 21 covering the thin film transistor Tr and the capacitive element Cs. Wiring is arranged in a so-called comb-teeth shape. The common electrode 33 is connected to the gate electrode 5 and the capacitive element Cs through the connection hole 9a (shown only in the plan view) provided in the second insulating film 21, the first insulating film 19, and the gate insulating film 9. It is connected to a common wiring 7a formed in the same layer as the common wiring 7 also serving as the lower electrode 7c.

  The second opening 15 b provided in the partition wall layer 15 is provided in a shape that widely opens a portion overlapping the transmissive display electrode 23 and the common electrode 33.

  In the display device having such a configuration, when the orientation of the liquid crystal layer LC is in a predetermined state due to a lateral electric field applied between the transmissive display electrode 23 and the common electrode 33, the light is incident from the substrate 3 side through the deflection plate. Then, the light passing through the liquid crystal layer LC passes through the deflecting plate on the counter substrate 31 side and is extracted as display light.

  In the method of manufacturing the display device having the above-described configuration, the second insulating film 21 and the first insulating film 19 are formed before the transmissive display electrode 23 is formed in the procedure described with reference to FIG. 3 in the first embodiment. And a step of forming a connection hole 9 a reaching the common wiring 7 in the gate insulating film 9. The common electrode 33 may be patterned in the same process as the pattern formation of the transmissive display electrode 23.

  Even in such an IPS mode display device 1-6, the channel portion semiconductor layer 17ch is provided at the bottom of the first opening 15a formed in the partition layer 15, and the transmissive display electrode 23 is provided on the partition layer 15. Since the second opening 15b overlapping the common electrode 33 is provided and the semiconductor layer 17 formed at the bottom of the second opening 15b is removed, the fine channel portion semiconductor layer 17ch is formed as in the first embodiment. However, display light can be obtained without being affected by the semiconductor layer 17.

  The sixth embodiment may be a transflective type in combination with the second and third embodiments. Further, the sixth embodiment may be combined with the fifth embodiment, and the thin film transistor may be a top gate type.

  Furthermore, in the configuration of the sixth embodiment, an FFS (Field Fringe Switching) mode liquid crystal display is provided by providing a common electrode 33 below, for example, the second insulating film 21 below the comb-shaped transmissive display electrode 23. A device can be configured. In this case, the common electrode 33 may be provided on the entire surface corresponding to the second opening 15b. Even if it is such a structure, the same effect can be acquired.

It is a principal part top view for 1 pixel in the display apparatus of the 1st-4th embodiment using a bottom gate type thin-film transistor. It is sectional drawing for 1 pixel in the display apparatus of 1st Embodiment. It is a manufacturing-process figure of the display apparatus of 1st Embodiment. It is sectional drawing for 1 pixel in the display apparatus of 2nd Embodiment. It is sectional drawing for 1 pixel in the display apparatus of 3rd Embodiment. It is sectional drawing for 1 pixel in the display apparatus of 4th Embodiment. It is a principal part top view for 1 pixel in the display apparatus of 5th Embodiment using a top gate type thin-film transistor. It is sectional drawing for 1 pixel in the display apparatus of 5th Embodiment. It is a manufacturing-process figure of the display apparatus of 5th Embodiment. It is a principal part top view for 1 pixel in the display apparatus of 6th Embodiment to which IPS mode is applied. It is sectional drawing for 1 pixel in the display apparatus of 6th Embodiment.

Explanation of symbols

  1-1, 1-2, 1-3, 1-4, 1-5, 1-6 ... display device (semiconductor device), 3 ... substrate, 5g ... gate electrode, 9 ... gate insulating film, 13sd ... source / Drain, 15 ... partition layer, 15a ... 1st opening, 15b ... 2nd opening, 15c ... 3rd opening, 17 ... semiconductor layer, 17ch ... channel part semiconductor layer, 19 ... 1st insulating film (insulating film), 19a ... 1st connection hole (connection hole), 23 ... Transparent pixel electrode, 27 ... Reflection pixel electrode, 31 ... Opposite substrate, LC ... Liquid crystal layer, Tr ... Thin film transistor (bottom gate type), Tr '... Thin film transistor (top gate type)

Claims (16)

A thin film transistor provided on a substrate;
An insulating partition layer provided with a first opening at a position corresponding to a channel portion of the thin film transistor and a second opening at a position corresponding to a formation region of the pixel electrode;
A channel part semiconductor layer constituting an active layer of the thin film transistor provided at the bottom of the first opening;
An insulating film formed on the partition layer and on the substrate so as to fill the first opening and the second opening;
A display device comprising the pixel electrode formed on the insulating film. The display device according to claim 1,
In the partition layer, a third opening reaching the source electrode or the drain electrode of the thin film transistor is provided,
The display device in which the pixel electrode is connected to the source electrode or the drain electrode through a connection hole provided in the insulating film at a bottom portion of the third opening. The display device according to claim 1,
A display device, wherein a semiconductor layer made of the same material as that of the channel portion semiconductor layer is provided on the partition wall layer. The display device according to claim 1,
The channel part semiconductor layer is a display device made of an organic material. In the display device according to claim 1,
A counter substrate provided to face the substrate;
A display device in which a liquid crystal layer is sandwiched between the substrate and the counter substrate. The display device according to claim 1,
A display device, wherein a reflective pixel electrode connected to the pixel electrode is provided on the insulating film. The display device according to claim 1,
The thin film transistor is a bottom gate type,
A display device in which a gate electrode and a gate insulating film are provided in order from the substrate side between the substrate and the channel portion semiconductor layer. The display device according to claim 1,
The thin film transistor is a top gate type,
A display device, wherein a gate electrode is provided above the channel portion semiconductor layer via a gate insulating film. The display device according to claim 8, wherein
A display device in which a capacitor is provided by an electrode formed in the same layer as a source electrode and a drain electrode of the thin film transistor and an electrode provided in the same layer as a gate electrode above the electrode. Forming a source electrode and a drain electrode of a thin film transistor on a substrate;
Insulation having a first opening exposing the end of the source electrode, an end of the drain electrode, and a second opening separated from the first opening so as to cover the source electrode and the drain electrode on the substrate Forming a partition wall layer of
Forming a channel part semiconductor layer made of the semiconductor layer at the bottom of the first opening;
Forming an insulating film in a state of embedding the first opening and the second opening so as to cover the partition layer and the semiconductor layer above the substrate;
And a step of forming a pixel electrode on the insulating film. In the manufacturing method of the display device according to claim 10,
The step of forming the channel portion semiconductor layer includes forming a semiconductor layer on the bottom of the first opening in a state separated from the upper portion of the partition layer by forming a semiconductor layer from the upper portion of the partition layer. For manufacturing a display device for forming a partial semiconductor layer. In the manufacturing method of the display device according to claim 11,
The step of forming the channel portion semiconductor layer includes forming a semiconductor layer on the bottom of the first opening in a state separated from the upper portion of the partition layer by forming a semiconductor layer from the upper portion of the partition layer. Forming a partial semiconductor layer, forming a semiconductor layer made of the same material as the channel semiconductor layer at the bottom of the second opening,
A method for manufacturing a display device, comprising performing a step of removing the semiconductor layer from a bottom of the second opening after the step of forming the channel portion semiconductor layer. In the manufacturing method of the display device according to claim 10,
The step of forming the channel semiconductor layer forms a channel semiconductor layer made of the semiconductor layer at the bottom of the first opening by a method of selectively forming a solution containing a semiconductor material only on the bottom of the first opening. Manufacturing method of display device. In the manufacturing method of the display device according to claim 10,
In the step of forming the partition layer, a third opening reaching the source electrode or the drain electrode is formed in the partition layer together with the first opening and the second opening,
In the step of forming the insulating film, the insulating film is formed in a state of also embedding the third opening,
After the step of forming the insulating film, a step of forming a connection hole reaching the source electrode or the drain electrode in the insulating film inside the third opening,
In the step of forming the pixel electrode, the pixel electrode is formed in a state of being connected to the source electrode or the drain electrode through the connection hole. In the manufacturing method of the display device according to claim 10,
In the step of forming the partition layer, a third opening reaching the source electrode or the drain electrode is formed in the partition layer together with the first opening and the second opening,
The step of forming the channel portion semiconductor layer includes forming a semiconductor layer on the bottom of the first opening in a state separated from the upper portion of the partition layer by forming a semiconductor layer from the upper portion of the partition layer. Forming a semiconductor layer,
In the step of forming the insulating film, the insulating film is formed in a state of also embedding the third opening,
After the step of forming the insulating film, a connection hole reaching the source electrode or the drain electrode inside the third opening in a state in which the insulating film is insulated from the semiconductor layer on the partition. The process of forming
In the step of forming the pixel electrode, the pixel electrode is formed in a state of being connected to the source electrode or the drain electrode through the connection hole. In the manufacturing method of the display device according to claim 15,
The step of forming the channel portion semiconductor layer includes forming a semiconductor layer on the bottom of the first opening in a state separated from the upper portion of the partition layer by forming a semiconductor layer from the upper portion of the partition layer. Forming a partial semiconductor layer, forming a semiconductor layer made of the same material as the channel semiconductor layer at the bottom of the second opening,
After the step of forming the channel portion semiconductor layer, the semiconductor layer is removed from the bottom of the second opening, thereby maintaining the insulation with respect to the semiconductor layer on the insulating film. A method of manufacturing a display device, comprising: forming a connection hole reaching the source electrode or the drain electrode.

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