JP2009541909A5 - - Google Patents

Download PDF

Info

Publication number
JP2009541909A5
JP2009541909A5 JP2009516619A JP2009516619A JP2009541909A5 JP 2009541909 A5 JP2009541909 A5 JP 2009541909A5 JP 2009516619 A JP2009516619 A JP 2009516619A JP 2009516619 A JP2009516619 A JP 2009516619A JP 2009541909 A5 JP2009541909 A5 JP 2009541909A5
Authority
JP
Japan
Prior art keywords
vpass
reprogramming
storage element
voltage
word lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009516619A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009541909A (ja
JP4994447B2 (ja
Filing date
Publication date
Priority claimed from US11/425,794 external-priority patent/US7489549B2/en
Priority claimed from US11/425,790 external-priority patent/US7486561B2/en
Application filed filed Critical
Priority claimed from PCT/US2007/069711 external-priority patent/WO2007149677A2/en
Publication of JP2009541909A publication Critical patent/JP2009541909A/ja
Publication of JP2009541909A5 publication Critical patent/JP2009541909A5/ja
Application granted granted Critical
Publication of JP4994447B2 publication Critical patent/JP4994447B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2009516619A 2006-06-22 2007-05-25 閾値電圧の分布が緊密化するように不揮発性メモリを非リアルタイムで再プログラミングする方法 Active JP4994447B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/425,794 US7489549B2 (en) 2006-06-22 2006-06-22 System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
US11/425,790 US7486561B2 (en) 2006-06-22 2006-06-22 Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
US11/425,794 2006-06-22
US11/425,790 2006-06-22
PCT/US2007/069711 WO2007149677A2 (en) 2006-06-22 2007-05-25 Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages

Publications (3)

Publication Number Publication Date
JP2009541909A JP2009541909A (ja) 2009-11-26
JP2009541909A5 true JP2009541909A5 (enExample) 2012-02-02
JP4994447B2 JP4994447B2 (ja) 2012-08-08

Family

ID=38834212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009516619A Active JP4994447B2 (ja) 2006-06-22 2007-05-25 閾値電圧の分布が緊密化するように不揮発性メモリを非リアルタイムで再プログラミングする方法

Country Status (6)

Country Link
EP (1) EP2030205B1 (enExample)
JP (1) JP4994447B2 (enExample)
KR (1) KR101075253B1 (enExample)
AT (1) ATE515771T1 (enExample)
TW (1) TWI337746B (enExample)
WO (1) WO2007149677A2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITRM20080114A1 (it) * 2008-02-29 2009-09-01 Micron Technology Inc Compensazione della perdita di carica durante la programmazione di un dispositivo di memoria.
US7924614B2 (en) 2009-01-19 2011-04-12 Macronix International Co., Ltd. Memory and boundary searching method thereof
US8504759B2 (en) * 2009-05-26 2013-08-06 Micron Technology, Inc. Method and devices for controlling power loss
JP2011159364A (ja) * 2010-02-02 2011-08-18 Toshiba Corp 不揮発性半導体記憶装置および不揮発性半導体記憶装置の駆動方法
JP2011198419A (ja) * 2010-03-19 2011-10-06 Toshiba Corp 不揮発性半導体記憶装置およびその書き込み方法
KR20110126408A (ko) 2010-05-17 2011-11-23 삼성전자주식회사 비휘발성 메모리 장치, 그것을 포함한 메모리 시스템 및 그것의 프로그램 방법
JP2012190523A (ja) 2011-03-14 2012-10-04 Toshiba Corp 不揮発性半導体記憶装置
US9092320B2 (en) 2012-10-15 2015-07-28 Hitachi, Ltd. Storage system which includes non-volatile semiconductor storage medium, and storage control method of storage system
US9257203B2 (en) 2012-12-06 2016-02-09 Micron Technology, Inc. Setting a default read signal based on error correction
KR102175039B1 (ko) * 2013-06-25 2020-11-05 삼성전자주식회사 불휘발성 메모리 장치의 데이터 기입 방법
KR20160032910A (ko) 2014-09-17 2016-03-25 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
JP6453718B2 (ja) * 2015-06-12 2019-01-16 東芝メモリ株式会社 半導体記憶装置及びメモリシステム
US10460816B2 (en) 2017-12-08 2019-10-29 Sandisk Technologies Llc Systems and methods for high-performance write operations

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3930074B2 (ja) * 1996-09-30 2007-06-13 株式会社ルネサステクノロジ 半導体集積回路及びデータ処理システム
KR100257868B1 (ko) * 1997-12-29 2000-06-01 윤종용 노어형 플래시 메모리 장치의 소거 방법
JP3957985B2 (ja) * 2001-03-06 2007-08-15 株式会社東芝 不揮発性半導体記憶装置
US6522580B2 (en) * 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
JP3863485B2 (ja) * 2002-11-29 2006-12-27 株式会社東芝 不揮発性半導体記憶装置
US6657891B1 (en) * 2002-11-29 2003-12-02 Kabushiki Kaisha Toshiba Semiconductor memory device for storing multivalued data
JP4410188B2 (ja) * 2004-11-12 2010-02-03 株式会社東芝 半導体記憶装置のデータ書き込み方法
US7212436B2 (en) * 2005-02-28 2007-05-01 Micron Technology, Inc. Multiple level programming in a non-volatile memory device

Similar Documents

Publication Publication Date Title
JP2009541909A5 (enExample)
TWI343579B (en) Charge trap type non-volatile memory device and programe method thereof
CN107818809B (zh) 半导体存储装置及存储器系统
CN106531219B (zh) 存储器装置
US9082503B2 (en) Semiconductor memory device and method of operating the same
TWI570721B (zh) 使用多位準通過信號程式化記憶體
CN102110471B (zh) 非易失性半导体存储装置
US10720215B2 (en) Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming
JP2010519673A5 (enExample)
WO2007089370A3 (en) Self-boosting method for flash memory cells
ATE546782T1 (de) Speichersystem
ATE493735T1 (de) Nand-flash-speicher, der programmstörungen mit einer selbstverstärkenden technik vermeidet
TW201243849A (en) Reducing neighbor read disturb
JP2012221522A5 (enExample)
KR101099835B1 (ko) 반도체 메모리 장치 및 이의 동작 방법
TW200907981A (en) Flash memory devices and operating methods that concurrently apply different predetermined bias voltages to dummy flash memory cells than to regular memory cells during erase
TW201129978A (en) A method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device
TWI281669B (en) Row decoder circuit of NAND flash memory and method of supplying an operating voltage using the same
WO2009057275A1 (ja) 不揮発性記憶装置および不揮発性データ記録メディア
ATE450043T1 (de) Verfahren zur programmierung eines nicht flüchtigen speichers mit verminderter programmstörung über modizifierte durchgangsspannungen
TW200519951A (en) Nonvolatile semiconductor memory
CN101162610A (zh) 对非易失性存储器件生成编程电压的电路和方法
US20140029353A1 (en) Methods and devices for memory reads with precharged data lines
JP2009518766A5 (enExample)
TW200614263A (en) Semiconductor memory device for low power system