JP2009527808A5 - - Google Patents

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Publication number
JP2009527808A5
JP2009527808A5 JP2008555353A JP2008555353A JP2009527808A5 JP 2009527808 A5 JP2009527808 A5 JP 2009527808A5 JP 2008555353 A JP2008555353 A JP 2008555353A JP 2008555353 A JP2008555353 A JP 2008555353A JP 2009527808 A5 JP2009527808 A5 JP 2009527808A5
Authority
JP
Japan
Prior art keywords
computer
instructions
instruction
group
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008555353A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009527808A (ja
Filing date
Publication date
Priority claimed from US11/355,495 external-priority patent/US7904615B2/en
Priority claimed from US11/355,513 external-priority patent/US7904695B2/en
Priority claimed from US11/441,818 external-priority patent/US7934075B2/en
Priority claimed from US11/441,812 external-priority patent/US7913069B2/en
Priority claimed from US11/441,784 external-priority patent/US7752422B2/en
Application filed filed Critical
Priority claimed from PCT/US2007/004029 external-priority patent/WO2007098005A2/en
Publication of JP2009527808A publication Critical patent/JP2009527808A/ja
Publication of JP2009527808A5 publication Critical patent/JP2009527808A5/ja
Pending legal-status Critical Current

Links

JP2008555353A 2006-02-16 2007-02-16 マイクロループコンピュータ命令 Pending JP2009527808A (ja)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US11/355,495 US7904615B2 (en) 2006-02-16 2006-02-16 Asynchronous computer communication
US11/355,513 US7904695B2 (en) 2006-02-16 2006-02-16 Asynchronous power saving computer
US78826506P 2006-03-31 2006-03-31
US79734506P 2006-05-03 2006-05-03
US11/441,818 US7934075B2 (en) 2006-02-16 2006-05-26 Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array
US11/441,812 US7913069B2 (en) 2006-02-16 2006-05-26 Processor and method for executing a program loop within an instruction word
US11/441,784 US7752422B2 (en) 2006-02-16 2006-05-26 Execution of instructions directly from input source
PCT/US2007/004029 WO2007098005A2 (en) 2006-02-16 2007-02-16 Microloop computer instructions

Publications (2)

Publication Number Publication Date
JP2009527808A JP2009527808A (ja) 2009-07-30
JP2009527808A5 true JP2009527808A5 (enExample) 2010-04-08

Family

ID=38066677

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2008555372A Pending JP2009527816A (ja) 2006-02-16 2007-02-16 コンピュータへの入力を監視する方法および装置
JP2008555353A Pending JP2009527808A (ja) 2006-02-16 2007-02-16 マイクロループコンピュータ命令
JP2008555354A Pending JP2009527809A (ja) 2006-02-16 2007-02-16 入力ソースから直接の命令の実行

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2008555372A Pending JP2009527816A (ja) 2006-02-16 2007-02-16 コンピュータへの入力を監視する方法および装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2008555354A Pending JP2009527809A (ja) 2006-02-16 2007-02-16 入力ソースから直接の命令の実行

Country Status (7)

Country Link
EP (3) EP1821202B1 (enExample)
JP (3) JP2009527816A (enExample)
KR (3) KR20090004394A (enExample)
AT (2) ATE495491T1 (enExample)
DE (1) DE602007011841D1 (enExample)
TW (3) TW200809613A (enExample)
WO (3) WO2007098005A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11841822B2 (en) * 2019-04-27 2023-12-12 Cambricon Technologies Corporation Limited Fractal calculating device and method, integrated circuit and board card
WO2020220935A1 (zh) * 2019-04-27 2020-11-05 中科寒武纪科技股份有限公司 运算装置
US11960438B2 (en) 2020-09-08 2024-04-16 Rambus Inc. Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture
GB2609243B (en) * 2021-07-26 2024-03-06 Advanced Risc Mach Ltd A data processing apparatus and method for transmitting triggered instructions between processing elements

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3757306A (en) * 1971-08-31 1973-09-04 Texas Instruments Inc Computing systems cpu
EP0227319A3 (en) * 1985-12-26 1989-11-02 Analog Devices, Inc. Instruction cache memory
JPS62180456A (ja) * 1986-02-03 1987-08-07 Nippon Telegr & Teleph Corp <Ntt> 並列計算機の信号バイパス方式
US4868745A (en) * 1986-05-30 1989-09-19 Hewlett-Packard Company Data processing system and method for the direct and indirect execution of uniformly structured object types
CA2019299C (en) * 1989-06-22 2002-01-15 Steven Frank Multiprocessor system with multiple instruction sources
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
EP0428770B1 (de) * 1989-11-21 1995-02-01 Deutsche ITT Industries GmbH Datengesteuerter Arrayprozessor
US5390304A (en) * 1990-09-28 1995-02-14 Texas Instruments, Incorporated Method and apparatus for processing block instructions in a data processor
JP3102594B2 (ja) * 1991-02-19 2000-10-23 松下電器産業株式会社 キャッシュメモリ装置
US5434989A (en) * 1991-02-19 1995-07-18 Matsushita Electric Industrial Co., Ltd. Cache memory for efficient access with address selectors
JPH04367936A (ja) * 1991-06-17 1992-12-21 Mitsubishi Electric Corp スーパースカラープロセッサ
JPH0863355A (ja) * 1994-08-18 1996-03-08 Mitsubishi Electric Corp プログラム制御装置及びプログラム制御方法
US5680597A (en) * 1995-01-26 1997-10-21 International Business Machines Corporation System with flexible local control for modifying same instruction partially in different processor of a SIMD computer system to execute dissimilar sequences of instructions
US5727194A (en) 1995-06-07 1998-03-10 Hitachi America, Ltd. Repeat-bit based, compact system and method for implementing zero-overhead loops
US5752259A (en) * 1996-03-26 1998-05-12 Advanced Micro Devices, Inc. Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
EP0992894A1 (en) * 1998-10-06 2000-04-12 Texas Instruments Inc. Apparatus and method for loop execution
JP3344345B2 (ja) * 1998-12-15 2002-11-11 日本電気株式会社 共有メモリ型ベクトル処理システムとその制御方法及びベクトル処理の制御プログラムを格納する記憶媒体
GB2370381B (en) * 2000-12-19 2003-12-24 Picochip Designs Ltd Processor architecture
US6938253B2 (en) * 2001-05-02 2005-08-30 Portalplayer, Inc. Multiprocessor communication system and method
JP3900359B2 (ja) * 2001-08-22 2007-04-04 アデランテ テクノロジーズ ベスローテン フェンノートシャップ パイプライン化されたプロセッサ及び命令ループ実行方法
JP3509023B2 (ja) * 2002-06-26 2004-03-22 沖電気工業株式会社 ループ制御回路及びループ制御方法
JP4610218B2 (ja) * 2004-03-30 2011-01-12 ルネサスエレクトロニクス株式会社 情報処理装置

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