KR20090004394A - 입력 소스로부터의 직접적인 명령어들의 실행 - Google Patents

입력 소스로부터의 직접적인 명령어들의 실행 Download PDF

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Publication number
KR20090004394A
KR20090004394A KR1020077009924A KR20077009924A KR20090004394A KR 20090004394 A KR20090004394 A KR 20090004394A KR 1020077009924 A KR1020077009924 A KR 1020077009924A KR 20077009924 A KR20077009924 A KR 20077009924A KR 20090004394 A KR20090004394 A KR 20090004394A
Authority
KR
South Korea
Prior art keywords
instruction
computer
address
instructions
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020077009924A
Other languages
English (en)
Korean (ko)
Inventor
찰스 에이치. 무어
Original Assignee
브이엔에스 포트폴리오 엘엘씨
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/355,495 external-priority patent/US7904615B2/en
Priority claimed from US11/355,513 external-priority patent/US7904695B2/en
Priority claimed from US11/441,812 external-priority patent/US7913069B2/en
Priority claimed from US11/441,818 external-priority patent/US7934075B2/en
Priority claimed from US11/441,784 external-priority patent/US7752422B2/en
Application filed by 브이엔에스 포트폴리오 엘엘씨 filed Critical 브이엔에스 포트폴리오 엘엘씨
Publication of KR20090004394A publication Critical patent/KR20090004394A/ko
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Power Sources (AREA)
KR1020077009924A 2006-02-16 2007-02-16 입력 소스로부터의 직접적인 명령어들의 실행 Withdrawn KR20090004394A (ko)

Applications Claiming Priority (14)

Application Number Priority Date Filing Date Title
US11/355,495 2006-02-16
US11/355,495 US7904615B2 (en) 2006-02-16 2006-02-16 Asynchronous computer communication
US11/355,513 US7904695B2 (en) 2006-02-16 2006-02-16 Asynchronous power saving computer
US11/355,513 2006-02-16
US78826506P 2006-03-31 2006-03-31
US60/788,265 2006-03-31
US79734506P 2006-05-03 2006-05-03
US60/797,345 2006-05-03
US11/441,812 2006-05-26
US11/441,784 2006-05-26
US11/441,812 US7913069B2 (en) 2006-02-16 2006-05-26 Processor and method for executing a program loop within an instruction word
US11/441,818 2006-05-26
US11/441,818 US7934075B2 (en) 2006-02-16 2006-05-26 Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array
US11/441,784 US7752422B2 (en) 2006-02-16 2006-05-26 Execution of instructions directly from input source

Publications (1)

Publication Number Publication Date
KR20090004394A true KR20090004394A (ko) 2009-01-12

Family

ID=38066677

Family Applications (3)

Application Number Title Priority Date Filing Date
KR1020077009924A Withdrawn KR20090004394A (ko) 2006-02-16 2007-02-16 입력 소스로부터의 직접적인 명령어들의 실행
KR1020077009925A Withdrawn KR20090016645A (ko) 2006-02-16 2007-02-16 컴퓨터의 입력을 모니터링하는 방법과 장치
KR1020077009923A Withdrawn KR20090017390A (ko) 2006-02-16 2007-02-16 마이크로 루프 컴퓨터 명령어

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1020077009925A Withdrawn KR20090016645A (ko) 2006-02-16 2007-02-16 컴퓨터의 입력을 모니터링하는 방법과 장치
KR1020077009923A Withdrawn KR20090017390A (ko) 2006-02-16 2007-02-16 마이크로 루프 컴퓨터 명령어

Country Status (7)

Country Link
EP (3) EP1821199B1 (enExample)
JP (3) JP2009527809A (enExample)
KR (3) KR20090004394A (enExample)
AT (2) ATE512400T1 (enExample)
DE (1) DE602007011841D1 (enExample)
TW (3) TW200809613A (enExample)
WO (3) WO2007098005A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020220935A1 (zh) * 2019-04-27 2020-11-05 中科寒武纪科技股份有限公司 运算装置
US11841822B2 (en) * 2019-04-27 2023-12-12 Cambricon Technologies Corporation Limited Fractal calculating device and method, integrated circuit and board card
US11960438B2 (en) 2020-09-08 2024-04-16 Rambus Inc. Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture
GB2609243B (en) * 2021-07-26 2024-03-06 Advanced Risc Mach Ltd A data processing apparatus and method for transmitting triggered instructions between processing elements

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3757306A (en) * 1971-08-31 1973-09-04 Texas Instruments Inc Computing systems cpu
EP0227319A3 (en) * 1985-12-26 1989-11-02 Analog Devices, Inc. Instruction cache memory
JPS62180456A (ja) * 1986-02-03 1987-08-07 Nippon Telegr & Teleph Corp <Ntt> 並列計算機の信号バイパス方式
US4868745A (en) * 1986-05-30 1989-09-19 Hewlett-Packard Company Data processing system and method for the direct and indirect execution of uniformly structured object types
CA2019299C (en) * 1989-06-22 2002-01-15 Steven Frank Multiprocessor system with multiple instruction sources
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
DE58908974D1 (de) * 1989-11-21 1995-03-16 Itt Ind Gmbh Deutsche Datengesteuerter Arrayprozessor.
US5390304A (en) * 1990-09-28 1995-02-14 Texas Instruments, Incorporated Method and apparatus for processing block instructions in a data processor
JP3102594B2 (ja) * 1991-02-19 2000-10-23 松下電器産業株式会社 キャッシュメモリ装置
US5434989A (en) * 1991-02-19 1995-07-18 Matsushita Electric Industrial Co., Ltd. Cache memory for efficient access with address selectors
JPH04367936A (ja) * 1991-06-17 1992-12-21 Mitsubishi Electric Corp スーパースカラープロセッサ
JPH0863355A (ja) * 1994-08-18 1996-03-08 Mitsubishi Electric Corp プログラム制御装置及びプログラム制御方法
US5680597A (en) * 1995-01-26 1997-10-21 International Business Machines Corporation System with flexible local control for modifying same instruction partially in different processor of a SIMD computer system to execute dissimilar sequences of instructions
US5727194A (en) 1995-06-07 1998-03-10 Hitachi America, Ltd. Repeat-bit based, compact system and method for implementing zero-overhead loops
US5752259A (en) * 1996-03-26 1998-05-12 Advanced Micro Devices, Inc. Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
EP0992894A1 (en) * 1998-10-06 2000-04-12 Texas Instruments Inc. Apparatus and method for loop execution
JP3344345B2 (ja) * 1998-12-15 2002-11-11 日本電気株式会社 共有メモリ型ベクトル処理システムとその制御方法及びベクトル処理の制御プログラムを格納する記憶媒体
GB2370381B (en) * 2000-12-19 2003-12-24 Picochip Designs Ltd Processor architecture
US6938253B2 (en) * 2001-05-02 2005-08-30 Portalplayer, Inc. Multiprocessor communication system and method
EP1421476A1 (en) 2001-08-22 2004-05-26 Adelante Technologies B.V. Pipelined processor and instruction loop execution method
JP3509023B2 (ja) * 2002-06-26 2004-03-22 沖電気工業株式会社 ループ制御回路及びループ制御方法
JP4610218B2 (ja) * 2004-03-30 2011-01-12 ルネサスエレクトロニクス株式会社 情報処理装置

Also Published As

Publication number Publication date
EP1821200B1 (en) 2011-06-08
JP2009527808A (ja) 2009-07-30
DE602007011841D1 (de) 2011-02-24
EP1821202B1 (en) 2011-01-12
WO2007098026A2 (en) 2007-08-30
WO2007098026A3 (en) 2009-04-09
TW200809531A (en) 2008-02-16
JP2009527816A (ja) 2009-07-30
ATE512400T1 (de) 2011-06-15
ATE495491T1 (de) 2011-01-15
TW200809609A (en) 2008-02-16
EP1821199A1 (en) 2007-08-22
WO2007098005A2 (en) 2007-08-30
KR20090017390A (ko) 2009-02-18
TW200809613A (en) 2008-02-16
EP1821199B1 (en) 2012-07-04
KR20090016645A (ko) 2009-02-17
WO2007098006A2 (en) 2007-08-30
WO2007098006A3 (en) 2009-01-08
JP2009527809A (ja) 2009-07-30
WO2007098005A3 (en) 2008-10-09
EP1821200A3 (en) 2008-09-24
EP1821202A1 (en) 2007-08-22
EP1821200A2 (en) 2007-08-22

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PA0105 International application

Patent event date: 20070430

Patent event code: PA01051R01D

Comment text: International Patent Application

N231 Notification of change of applicant
PN2301 Change of applicant

Patent event date: 20081009

Comment text: Notification of Change of Applicant

Patent event code: PN23011R01D

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid