JP2009524228A5 - - Google Patents

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Publication number
JP2009524228A5
JP2009524228A5 JP2008550752A JP2008550752A JP2009524228A5 JP 2009524228 A5 JP2009524228 A5 JP 2009524228A5 JP 2008550752 A JP2008550752 A JP 2008550752A JP 2008550752 A JP2008550752 A JP 2008550752A JP 2009524228 A5 JP2009524228 A5 JP 2009524228A5
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JP
Japan
Prior art keywords
functional blocks
outputs
inputs
crossbar
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008550752A
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English (en)
Japanese (ja)
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JP2009524228A (ja
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Publication date
Priority claimed from US11/333,191 external-priority patent/US7274215B2/en
Application filed filed Critical
Publication of JP2009524228A publication Critical patent/JP2009524228A/ja
Publication of JP2009524228A5 publication Critical patent/JP2009524228A5/ja
Withdrawn legal-status Critical Current

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JP2008550752A 2006-01-17 2007-01-17 １つ以上の加算器を含む拡張可能なアーキテクチャを有する再設定可能な集積回路 Withdrawn JP2009524228A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/333,191 US7274215B2 (en) 2006-01-17 2006-01-17 Reconfigurable integrated circuits with scalable architecture including one or more adders
PCT/EP2007/050467 WO2007082902A1 (en) 2006-01-17 2007-01-17 Reconfigurable integrated circuits with scalable architecture including one or more adders

Publications (2)

Publication Number Publication Date
JP2009524228A JP2009524228A (ja) 2009-06-25
JP2009524228A5 true JP2009524228A5 (enExample) 2011-02-17

Family

ID=38109657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008550752A Withdrawn JP2009524228A (ja) 2006-01-17 2007-01-17 １つ以上の加算器を含む拡張可能なアーキテクチャを有する再設定可能な集積回路

Country Status (5)

Country Link
US (2) US7274215B2 (enExample)
EP (1) EP1974285A1 (enExample)
JP (1) JP2009524228A (enExample)
TW (1) TW200805885A (enExample)
WO (1) WO2007082902A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404491B (zh) * 2008-05-23 2012-03-28 雅格罗技（北京）科技有限公司 一种具有交叉链接的可编程互连网络的集成电路
FR2933826B1 (fr) * 2008-07-09 2011-11-18 Univ Paris Curie Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau
US8245177B2 (en) * 2008-10-30 2012-08-14 Meta Systems Crossbar structure with mechanism for generating constant outputs
CA2740792C (en) * 2008-10-31 2016-06-21 Genentech, Inc. Pyrazolopyrimidine jak inhibitor compounds and methods

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5258668A (en) 1992-05-08 1993-11-02 Altera Corporation Programmable logic array integrated circuits with cascade connections between logic modules
US5436574A (en) 1993-11-12 1995-07-25 Altera Corporation Universal logic module with arithmetic capabilities
US6294928B1 (en) * 1996-04-05 2001-09-25 Altera Corporation Programmable logic device with highly routable interconnect
US5631576A (en) 1995-09-01 1997-05-20 Altera Corporation Programmable logic array integrated circuit devices with flexible carry chains
US6289494B1 (en) * 1997-11-12 2001-09-11 Quickturn Design Systems, Inc. Optimized emulation and prototyping architecture
JP3616518B2 (ja) * 1999-02-10 2005-02-02 日本電気株式会社 プログラマブルデバイス
US6947882B1 (en) * 1999-09-24 2005-09-20 Mentor Graphics Corporation Regionally time multiplexed emulation system
US6594810B1 (en) * 2001-10-04 2003-07-15 M2000 Reconfigurable integrated circuit with a scalable architecture
FR2850768B1 (fr) * 2003-02-03 2005-11-18 St Microelectronics Sa Dispositif electronique configurable a granularite mixte
US7042248B1 (en) * 2003-06-03 2006-05-09 Altera Corporation Dedicated crossbar and barrel shifter block on programmable logic resources
US7324537B2 (en) * 2003-07-18 2008-01-29 Intel Corporation Switching device with asymmetric port speeds
JP4804829B2 (ja) * 2005-08-24 2011-11-02 富士通株式会社 回路
US7568064B2 (en) * 2006-02-21 2009-07-28 M2000 Packet-oriented communication in reconfigurable circuit(s)

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