TW200805885A - Reconfigurable integrated circuits with scalable architecture including one or more adders - Google Patents

Reconfigurable integrated circuits with scalable architecture including one or more adders Download PDF

Info

Publication number
TW200805885A
TW200805885A TW096101901A TW96101901A TW200805885A TW 200805885 A TW200805885 A TW 200805885A TW 096101901 A TW096101901 A TW 096101901A TW 96101901 A TW96101901 A TW 96101901A TW 200805885 A TW200805885 A TW 200805885A
Authority
TW
Taiwan
Prior art keywords
crossbar
coupled
adder
functional blocks
output
Prior art date
Application number
TW096101901A
Other languages
English (en)
Chinese (zh)
Inventor
Olivier Lepape
Original Assignee
M2000
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by M2000 filed Critical M2000
Publication of TW200805885A publication Critical patent/TW200805885A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW096101901A 2006-01-17 2007-01-18 Reconfigurable integrated circuits with scalable architecture including one or more adders TW200805885A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/333,191 US7274215B2 (en) 2006-01-17 2006-01-17 Reconfigurable integrated circuits with scalable architecture including one or more adders
PCT/EP2007/050467 WO2007082902A1 (en) 2006-01-17 2007-01-17 Reconfigurable integrated circuits with scalable architecture including one or more adders

Publications (1)

Publication Number Publication Date
TW200805885A true TW200805885A (en) 2008-01-16

Family

ID=38109657

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096101901A TW200805885A (en) 2006-01-17 2007-01-18 Reconfigurable integrated circuits with scalable architecture including one or more adders

Country Status (5)

Country Link
US (2) US7274215B2 (enExample)
EP (1) EP1974285A1 (enExample)
JP (1) JP2009524228A (enExample)
TW (1) TW200805885A (enExample)
WO (1) WO2007082902A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404491B (zh) * 2008-05-23 2012-03-28 雅格罗技（北京）科技有限公司 一种具有交叉链接的可编程互连网络的集成电路
FR2933826B1 (fr) * 2008-07-09 2011-11-18 Univ Paris Curie Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau
US8245177B2 (en) * 2008-10-30 2012-08-14 Meta Systems Crossbar structure with mechanism for generating constant outputs
CA2740792C (en) * 2008-10-31 2016-06-21 Genentech, Inc. Pyrazolopyrimidine jak inhibitor compounds and methods

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5258668A (en) 1992-05-08 1993-11-02 Altera Corporation Programmable logic array integrated circuits with cascade connections between logic modules
US5436574A (en) 1993-11-12 1995-07-25 Altera Corporation Universal logic module with arithmetic capabilities
US6294928B1 (en) * 1996-04-05 2001-09-25 Altera Corporation Programmable logic device with highly routable interconnect
US5631576A (en) 1995-09-01 1997-05-20 Altera Corporation Programmable logic array integrated circuit devices with flexible carry chains
US6289494B1 (en) * 1997-11-12 2001-09-11 Quickturn Design Systems, Inc. Optimized emulation and prototyping architecture
JP3616518B2 (ja) * 1999-02-10 2005-02-02 日本電気株式会社 プログラマブルデバイス
US6947882B1 (en) * 1999-09-24 2005-09-20 Mentor Graphics Corporation Regionally time multiplexed emulation system
US6594810B1 (en) * 2001-10-04 2003-07-15 M2000 Reconfigurable integrated circuit with a scalable architecture
FR2850768B1 (fr) * 2003-02-03 2005-11-18 St Microelectronics Sa Dispositif electronique configurable a granularite mixte
US7042248B1 (en) * 2003-06-03 2006-05-09 Altera Corporation Dedicated crossbar and barrel shifter block on programmable logic resources
US7324537B2 (en) * 2003-07-18 2008-01-29 Intel Corporation Switching device with asymmetric port speeds
JP4804829B2 (ja) * 2005-08-24 2011-11-02 富士通株式会社 回路
US7568064B2 (en) * 2006-02-21 2009-07-28 M2000 Packet-oriented communication in reconfigurable circuit(s)

Also Published As

Publication number Publication date
US20070164783A1 (en) 2007-07-19
EP1974285A1 (en) 2008-10-01
US7274215B2 (en) 2007-09-25
US20070279089A1 (en) 2007-12-06
WO2007082902A1 (en) 2007-07-26
JP2009524228A (ja) 2009-06-25
US7498840B2 (en) 2009-03-03

Similar Documents

Publication Publication Date Title
TWI234737B (en) Integrated circuit device
US10587269B2 (en) Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network
US6693456B2 (en) Interconnection network for a field programmable gate array
Singh et al. PITIA: an FPGA for throughput-intensive applications
US7906987B2 (en) Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus
US20220214888A1 (en) IC including Logic Tile, having Reconfigurable MAC Pipeline, and Reconfigurable Memory
CN112602054A (zh) 乘法器累加器电路、用于乘法累加的逻辑瓦片架构和包括逻辑瓦片阵列的ic
CN104182556B (zh) 芯片的布局方法
CA2461540C (en) A reconfigurable integrated circuit with a scalable architecture
TW200805885A (en) Reconfigurable integrated circuits with scalable architecture including one or more adders
US7768301B2 (en) Reconfigurable integrated circuits with scalable architecture including a plurality of special function elements
Attia et al. Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources
US8438522B1 (en) Logic element architecture for generic logic chains in programmable devices
Cevik et al. CMOS Implementation of Switching Lattices.
CN100495696C (zh) 可编程逻辑器件的对称型连线通道
Meng et al. A Study of Reconfigurable Switch Architecture for Chiplets Interconnection
JP2005116793A (ja) 半導体集積回路及びそのクロック配線方法
Saidi et al. Development and Analysis of Novel Mesh of Tree-based embedded FPGA
Ma et al. Collaborative Routing Architecture for FPGA
JP2020530700A (ja) 再構成可能回路のためのルーティングネットワーク
Wang Building efficient, reconfigurable hardware using hierarchical interconnects
Walkup et al. Routing-directed Placement for the Triptych FPGA
CN119598929A (zh) 一种双输出基本逻辑单元及fpga逻辑打包方法
Xiao et al. Processor tile Shapes and interconnect topologies for dense On-chip networks
Baek et al. Design of Low-Power and Low-Latency 256-Radix Crossbar Switch Using Hyper-X Network Topology