JP2009518717A5 - - Google Patents

Download PDF

Info

Publication number
JP2009518717A5
JP2009518717A5 JP2008543551A JP2008543551A JP2009518717A5 JP 2009518717 A5 JP2009518717 A5 JP 2009518717A5 JP 2008543551 A JP2008543551 A JP 2008543551A JP 2008543551 A JP2008543551 A JP 2008543551A JP 2009518717 A5 JP2009518717 A5 JP 2009518717A5
Authority
JP
Japan
Prior art keywords
design
name
names
view
protected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008543551A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009518717A (ja
Filing date
Publication date
Priority claimed from US11/290,368 external-priority patent/US7437698B2/en
Application filed filed Critical
Publication of JP2009518717A publication Critical patent/JP2009518717A/ja
Publication of JP2009518717A5 publication Critical patent/JP2009518717A5/ja
Pending legal-status Critical Current

Links

JP2008543551A 2005-11-30 2006-10-26 Ｅｄａツール設計ビューにおける情報を保護する方法およびプログラム・プロダクト Pending JP2009518717A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/290,368 US7437698B2 (en) 2005-11-30 2005-11-30 Method and program product for protecting information in EDA tool design views
PCT/US2006/060261 WO2007102887A2 (en) 2005-11-30 2006-10-26 Method and program product for protecting information in eda tool design views

Publications (2)

Publication Number Publication Date
JP2009518717A JP2009518717A (ja) 2009-05-07
JP2009518717A5 true JP2009518717A5 (enExample) 2009-12-10

Family

ID=38088978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008543551A Pending JP2009518717A (ja) 2005-11-30 2006-10-26 Ｅｄａツール設計ビューにおける情報を保護する方法およびプログラム・プロダクト

Country Status (6)

Country Link
US (1) US7437698B2 (enExample)
EP (1) EP1958107A2 (enExample)
JP (1) JP2009518717A (enExample)
KR (1) KR101336516B1 (enExample)
CN (1) CN101395609B (enExample)
WO (1) WO2007102887A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7543265B1 (en) * 2006-04-26 2009-06-02 Altera Corporation Method for early logic mapping during FPGA synthesis
TWI320913B (en) * 2006-08-30 2010-02-21 Via Tech Inc Methods, systems and computer-readable storage medium for shading process compiling of 3d computer graphics
US7784013B2 (en) * 2007-01-03 2010-08-24 PDF Acquisition Corp Method for the definition of a library of application-domain-specific logic cells
US7925940B2 (en) * 2007-10-17 2011-04-12 Synopsys, Inc. Enhancing speed of simulation of an IC design while testing scan circuitry
US7941774B2 (en) * 2008-08-04 2011-05-10 Texas Instruments Incorporated Partial timing modeling for gate level simulation
US20100199233A1 (en) * 2009-01-30 2010-08-05 Petunin Vladimir V Uniquely Marking Products And Product Design Data
US9805221B2 (en) * 2011-12-21 2017-10-31 Intel Corporation Incorporating access control functionality into a system on a chip (SoC)
US9984194B2 (en) * 2015-09-15 2018-05-29 Arm Limited Integrated circuit design
JP6578841B2 (ja) * 2015-09-17 2019-09-25 日本電気株式会社 難読化装置、方法およびプログラム
US9858398B2 (en) * 2015-10-30 2018-01-02 Synopsys, Inc. Deterministic identifiers for source code elements
CN106815387A (zh) * 2015-12-02 2017-06-09 北京华大九天软件有限公司 一种采用指定View进行网表输出的方法
KR101881915B1 (ko) * 2018-06-14 2018-07-26 에스브이디 주식회사 차량 설계를 위한 플러그인 시스템
KR102150335B1 (ko) * 2019-01-17 2020-09-01 주식회사 쓰리데이즈 데이터베이스 관리 시스템
US11023646B2 (en) 2019-06-18 2021-06-01 Samsung Electronics Co., Ltd. Hierarchical clock tree construction based on constraints
CN112560401B (zh) * 2020-12-22 2024-04-09 成都海光微电子技术有限公司 Verilog文件转换方法、装置、存储介质及设备
CN112818616B (zh) * 2021-01-15 2024-03-12 珠海泰芯半导体有限公司 管脚命名方法、寄存器激励源添加方法及电子装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5937190A (en) 1994-04-12 1999-08-10 Synopsys, Inc. Architecture and methods for a hardware description language source level analysis and debugging system
US5963454A (en) * 1996-09-25 1999-10-05 Vlsi Technology, Inc. Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs
JPH10187767A (ja) * 1996-12-24 1998-07-21 Mitsubishi Electric Corp パラメータ化ｈｄｌ記述方法、論理合成装置および論理合成プログラムを記録した媒体
US6263483B1 (en) 1998-02-20 2001-07-17 Lsi Logic Corporation Method of accessing the generic netlist created by synopsys design compilier
JP2002230061A (ja) * 2001-01-30 2002-08-16 Matsushita Electric Ind Co Ltd 半導体回路接続データベース及びこれを用いた半導体回路設計方法
US20030004699A1 (en) 2001-06-04 2003-01-02 Choi Charles Y. Method and apparatus for evaluating an integrated circuit model
US6886140B2 (en) 2002-01-17 2005-04-26 Micron Technology, Inc. Fast algorithm to extract flat information from hierarchical netlists
US7168041B1 (en) * 2002-06-10 2007-01-23 Cadence Design Systems, Inc. Method and apparatus for table and HDL based design entry
US6868531B1 (en) * 2002-12-27 2005-03-15 Unisys Corporation Generation of ordered interconnect output from an HDL representation of a circuit
JP4776172B2 (ja) * 2004-02-17 2011-09-21 株式会社リコー Ｌｓｉ設計・製造システムのセキュリティ方式
US7216317B2 (en) 2004-04-05 2007-05-08 Synopsys, Inc. Hierarchical signal integrity analysis using interface logic models
JP2007026178A (ja) * 2005-07-19 2007-02-01 Canon Inc データ生成装置、及び方法
US7325215B2 (en) * 2005-08-31 2008-01-29 Lsi Logic Corporation Timing violation debugging inside place and route tool

Similar Documents

Publication Publication Date Title
Kulkarni et al. Elements of additive manufacturing technology adoption in small-and medium-sized companies
JP2009514567A5 (enExample)
JP2008287744A5 (enExample)
JP2018524877A5 (enExample)
JP2011248735A5 (enExample)
WO2012143920A3 (en) Access permissions management system and method
CN108446753A (zh) 商品二维码编码方法和系统
JP2008539479A5 (enExample)
JP6537049B2 (ja) ３次元造形物に所望の情報を付加するための方法及びプログラム
JP2013228964A5 (enExample)
CISA et al. Porter five forces vs resource based view-a comparison
JP2008541226A5 (enExample)
JP2008537433A5 (enExample)
CN106095899A (zh) 一种具有专利分析功能的知识产权智能系统
JP2008527712A5 (enExample)
Husár et al. Optimization of the production process and defect identification in the production of face shields using fused deposition modeling technology
Prabu et al. Intellectual Property Rights and its development in India
CN105225134A (zh) 一种可定制的创意艺术图案处理方法和系统
CN106056495A (zh) 一种可进行专利交易的知识产权智能系统
Mazanec et al. Consumer psychology of Tourism, Hospitality and Leisure, Volume 2
Abdul Karim et al. Regional distribution of foreign direct investment inflows in the manufacturing sector in Malaysia
JP2005099913A5 (enExample)
CN105335460B (zh) Xbrl列报链接库转化为定义链接库的方法
CN107545436A (zh) 一种品牌床垫的高保真防伪技术
TH75247S (th) ลวดลายบนแผ่นพับกล่อง