CN101395609B - 用于保护eda工具设计视图中的信息的方法和系统 - Google Patents

用于保护eda工具设计视图中的信息的方法和系统 Download PDF

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Publication number
CN101395609B
CN101395609B CN2006800448986A CN200680044898A CN101395609B CN 101395609 B CN101395609 B CN 101395609B CN 2006800448986 A CN2006800448986 A CN 2006800448986A CN 200680044898 A CN200680044898 A CN 200680044898A CN 101395609 B CN101395609 B CN 101395609B
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design
view
name
title
databases
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CN2006800448986A
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Chinese (zh)
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CN101395609A (zh
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迈克尔·W·迪尔
约翰·W·伍尔西
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NXP USA Inc
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Freescale Semiconductor Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
    • G06F21/12—Protecting executable software
    • G06F21/14—Protecting executable software against software analysis or reverse engineering, e.g. by obfuscation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
    • G06F21/6209—Protecting access to data via a platform, e.g. using keys or access control rules to a single file or object, e.g. in a secure envelope, encrypted and accessed using a key, or with access control rules appended to the object itself
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Technology Law (AREA)
  • Multimedia (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • General Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
CN2006800448986A 2005-11-30 2006-10-26 用于保护eda工具设计视图中的信息的方法和系统 Expired - Fee Related CN101395609B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/290,368 US7437698B2 (en) 2005-11-30 2005-11-30 Method and program product for protecting information in EDA tool design views
US11/290,368 2005-11-30
PCT/US2006/060261 WO2007102887A2 (en) 2005-11-30 2006-10-26 Method and program product for protecting information in eda tool design views

Publications (2)

Publication Number Publication Date
CN101395609A CN101395609A (zh) 2009-03-25
CN101395609B true CN101395609B (zh) 2012-05-30

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CN2006800448986A Expired - Fee Related CN101395609B (zh) 2005-11-30 2006-10-26 用于保护eda工具设计视图中的信息的方法和系统

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Country Link
US (1) US7437698B2 (enExample)
EP (1) EP1958107A2 (enExample)
JP (1) JP2009518717A (enExample)
KR (1) KR101336516B1 (enExample)
CN (1) CN101395609B (enExample)
WO (1) WO2007102887A2 (enExample)

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US7543265B1 (en) * 2006-04-26 2009-06-02 Altera Corporation Method for early logic mapping during FPGA synthesis
TWI320913B (en) * 2006-08-30 2010-02-21 Via Tech Inc Methods, systems and computer-readable storage medium for shading process compiling of 3d computer graphics
US7784013B2 (en) * 2007-01-03 2010-08-24 PDF Acquisition Corp Method for the definition of a library of application-domain-specific logic cells
US7925940B2 (en) * 2007-10-17 2011-04-12 Synopsys, Inc. Enhancing speed of simulation of an IC design while testing scan circuitry
US7941774B2 (en) * 2008-08-04 2011-05-10 Texas Instruments Incorporated Partial timing modeling for gate level simulation
US20100199233A1 (en) * 2009-01-30 2010-08-05 Petunin Vladimir V Uniquely Marking Products And Product Design Data
US9805221B2 (en) * 2011-12-21 2017-10-31 Intel Corporation Incorporating access control functionality into a system on a chip (SoC)
US9984194B2 (en) * 2015-09-15 2018-05-29 Arm Limited Integrated circuit design
JP6578841B2 (ja) * 2015-09-17 2019-09-25 日本電気株式会社 難読化装置、方法およびプログラム
US9858398B2 (en) * 2015-10-30 2018-01-02 Synopsys, Inc. Deterministic identifiers for source code elements
CN106815387A (zh) * 2015-12-02 2017-06-09 北京华大九天软件有限公司 一种采用指定View进行网表输出的方法
KR101881915B1 (ko) * 2018-06-14 2018-07-26 에스브이디 주식회사 차량 설계를 위한 플러그인 시스템
KR102150335B1 (ko) * 2019-01-17 2020-09-01 주식회사 쓰리데이즈 데이터베이스 관리 시스템
US11023646B2 (en) 2019-06-18 2021-06-01 Samsung Electronics Co., Ltd. Hierarchical clock tree construction based on constraints
CN112560401B (zh) * 2020-12-22 2024-04-09 成都海光微电子技术有限公司 Verilog文件转换方法、装置、存储介质及设备
CN112818616B (zh) * 2021-01-15 2024-03-12 珠海泰芯半导体有限公司 管脚命名方法、寄存器激励源添加方法及电子装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6643826B2 (en) * 2001-01-30 2003-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor circuit connection data base and method of designing semiconductor circuit using the data base
US6868531B1 (en) * 2002-12-27 2005-03-15 Unisys Corporation Generation of ordered interconnect output from an HDL representation of a circuit

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Publication number Priority date Publication date Assignee Title
US5937190A (en) 1994-04-12 1999-08-10 Synopsys, Inc. Architecture and methods for a hardware description language source level analysis and debugging system
US5963454A (en) * 1996-09-25 1999-10-05 Vlsi Technology, Inc. Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs
JPH10187767A (ja) * 1996-12-24 1998-07-21 Mitsubishi Electric Corp パラメータ化ｈｄｌ記述方法、論理合成装置および論理合成プログラムを記録した媒体
US6263483B1 (en) 1998-02-20 2001-07-17 Lsi Logic Corporation Method of accessing the generic netlist created by synopsys design compilier
US20030004699A1 (en) 2001-06-04 2003-01-02 Choi Charles Y. Method and apparatus for evaluating an integrated circuit model
US6886140B2 (en) 2002-01-17 2005-04-26 Micron Technology, Inc. Fast algorithm to extract flat information from hierarchical netlists
US7168041B1 (en) * 2002-06-10 2007-01-23 Cadence Design Systems, Inc. Method and apparatus for table and HDL based design entry
JP4776172B2 (ja) * 2004-02-17 2011-09-21 株式会社リコー Ｌｓｉ設計・製造システムのセキュリティ方式
US7216317B2 (en) 2004-04-05 2007-05-08 Synopsys, Inc. Hierarchical signal integrity analysis using interface logic models
JP2007026178A (ja) * 2005-07-19 2007-02-01 Canon Inc データ生成装置、及び方法
US7325215B2 (en) * 2005-08-31 2008-01-29 Lsi Logic Corporation Timing violation debugging inside place and route tool

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6643826B2 (en) * 2001-01-30 2003-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor circuit connection data base and method of designing semiconductor circuit using the data base
US6868531B1 (en) * 2002-12-27 2005-03-15 Unisys Corporation Generation of ordered interconnect output from an HDL representation of a circuit

Also Published As

Publication number Publication date
KR20080072028A (ko) 2008-08-05
EP1958107A2 (en) 2008-08-20
WO2007102887A2 (en) 2007-09-13
US20070124717A1 (en) 2007-05-31
WO2007102887A3 (en) 2008-12-04
KR101336516B1 (ko) 2013-12-03
CN101395609A (zh) 2009-03-25
US7437698B2 (en) 2008-10-14
JP2009518717A (ja) 2009-05-07

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CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120530