JP2009512186A - 分離されたアシストフィーチャを用いたプロセスマージンの向上 - Google Patents
分離されたアシストフィーチャを用いたプロセスマージンの向上 Download PDFInfo
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- JP2009512186A JP2009512186A JP2008534530A JP2008534530A JP2009512186A JP 2009512186 A JP2009512186 A JP 2009512186A JP 2008534530 A JP2008534530 A JP 2008534530A JP 2008534530 A JP2008534530 A JP 2008534530A JP 2009512186 A JP2009512186 A JP 2009512186A
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- pitch
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67276—Production flow monitoring, e.g. for increasing throughput
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
Claims (10)
- マスク上の半隔離されたパターンフィーチャをリソグラフィ結像技術のプロセスマージンに対して制限する可能性のある因子として特定するステップと(1202,1204,1302,1304)、
前記結像技術の解像度の閾値を決定するステップと(1310)、
前記半隔離されたマスクフィーチャの近傍に1つ以上の分離されたサブ解像度アシストフィーチャを配置するステップ(1212)とを含む、
リソグラフィ結像システムのプロセスマージンを向上させる方法。 - 前記1つ以上の分離されたサブ解像度アシストフィーチャは1つ以上の分離されたスキャッタバー(301)を備えている、請求項1記載の方法。
- 前記1つ以上の分離されたスキャッタバーは2つ以上の分離状態のスキャッタバーセグメントを備えている(1212)、請求項2記載の方法。
- 前記決定された結像システムの解像度の閾値および前記解像度の閾値にて発生する既知量のライン端プルバックの少なくとも1つに、少なくとも部分的に基づいて、分離状態のスキャッタバーセグメントの最大サイズ閾値を決定するステップ(1210)と、前記2つ以上の分離状態のスキャッタバーセグメントを前記最大サイズ閾値のライン端プルバックよりも小さくなるように構成するステップ(1212)とをさらに含む、請求項3記載の方法。
- 結像システムによって解像可能なピッチの範囲外のピッチを有する前記2つ以上の分離状態のスキャッタバーセグメントを構成することにより、結像システムによる分離状態のスキャッタバーセグメントの解像を軽減するステップ(1312)をさらに含む、請求項3記載の方法。
- さらに、結像システム(822,824)の双極子照明源の軸に垂直なピッチを形成するステップをさらに含む、請求項5記載の方法。
- 結像システムの焦点深度のシミュレーションを行うステップ(1214,1314)をさらに含む、請求項4記載の方法。
- 1つ以上の半隔離されたマスクフィーチャ(204,300,402,502,512,522,532)と、
前記1つ以上の半隔離されたマスクフィーチャの少なくとも1つの近傍に位置し、前記1つ以上の半隔離されたマスクフィーチャのピッチを変化させ、露光過程後のフォトレジスト残渣を軽減する1つ以上の分離されたスキャッタバー(722,724,822,824)とを備えたフォトマスク。 - 歩留まりを制限する可能性のあるフォトマスク上のパターンフィーチャを特定する手段(1204,1304)と、
前記フォトマスク上には確実にプリント可能だがウェハ上のレジスト層上にフォトマスクフィーチャをプリントするのに使用される露光源による解像は不可能なサブ解像度サイズの複数の分離状態のスキャッタバーセグメントを形成する手段(1212,1312)とを備えた、ウェハ歩留まりの向上及びフォトレジスト露光技術後のレジスト残渣の軽減を支援するシステム。 - 前記複数のスキャッタバーセグメントを前記特定されたパターンフィーチャに隣接して配置し、前記特定されたパターンフィーチャのピッチを調整する手段(1212,1312)と、
前記フォトマスクを介して前記ウェハ上の前記レジスト層を露光する手段(1214,1314)をさらに備えた請求項9記載のシステム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/245,824 US7749662B2 (en) | 2005-10-07 | 2005-10-07 | Process margin using discrete assist features |
PCT/US2006/032916 WO2007044132A1 (en) | 2005-10-07 | 2006-08-23 | Improved process margin using discrete assist features |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009512186A true JP2009512186A (ja) | 2009-03-19 |
Family
ID=37560710
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008534530A Pending JP2009512186A (ja) | 2005-10-07 | 2006-08-23 | 分離されたアシストフィーチャを用いたプロセスマージンの向上 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7749662B2 (ja) |
JP (1) | JP2009512186A (ja) |
KR (1) | KR20080059638A (ja) |
CN (1) | CN101278233B (ja) |
DE (1) | DE112006002656B4 (ja) |
GB (1) | GB2444214B (ja) |
TW (1) | TWI465836B (ja) |
WO (1) | WO2007044132A1 (ja) |
Families Citing this family (29)
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US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
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US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
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US7917879B2 (en) | 2007-08-02 | 2011-03-29 | Tela Innovations, Inc. | Semiconductor device with dynamic array section |
US20070269749A1 (en) * | 2006-05-18 | 2007-11-22 | Richard Elliot Schenker | Methods to reduce the minimum pitch in a pattern |
US7493590B1 (en) * | 2006-07-11 | 2009-02-17 | Kla-Tencor Technologies Corporation | Process window optical proximity correction |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
EP2321748B1 (en) | 2008-07-16 | 2017-10-04 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
KR101195267B1 (ko) * | 2010-12-29 | 2012-11-14 | 에스케이하이닉스 주식회사 | 미세 패턴 형성 방법 |
US8656319B2 (en) * | 2012-02-08 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optical proximity correction convergence control |
US8895211B2 (en) | 2012-12-11 | 2014-11-25 | GlobalFoundries, Inc. | Semiconductor device resolution enhancement by etching multiple sides of a mask |
KR20180123156A (ko) * | 2016-04-04 | 2018-11-14 | 케이엘에이-텐코 코포레이션 | 필 팩터 변조에 의한 공정 호환성 개선 |
WO2018063331A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Fill pattern to enhance ebeam process margin |
WO2020212107A1 (en) * | 2019-04-15 | 2020-10-22 | Asml Netherlands B.V. | Method for determining corrections to features of a mask |
CN113156760A (zh) * | 2021-03-22 | 2021-07-23 | 泉芯集成电路制造(济南)有限公司 | 光刻掩模版以及掩模版图案成型方法 |
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-
2005
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-
2006
- 2006-08-23 CN CN200680036414.3A patent/CN101278233B/zh not_active Expired - Fee Related
- 2006-08-23 DE DE112006002656.9T patent/DE112006002656B4/de active Active
- 2006-08-23 GB GB0805194A patent/GB2444214B/en not_active Expired - Fee Related
- 2006-08-23 JP JP2008534530A patent/JP2009512186A/ja active Pending
- 2006-08-23 KR KR1020087011015A patent/KR20080059638A/ko not_active Application Discontinuation
- 2006-08-23 WO PCT/US2006/032916 patent/WO2007044132A1/en active Search and Examination
- 2006-09-20 TW TW095134718A patent/TWI465836B/zh not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
GB2444214A (en) | 2008-05-28 |
GB2444214B (en) | 2011-03-30 |
TWI465836B (zh) | 2014-12-21 |
US7749662B2 (en) | 2010-07-06 |
DE112006002656B4 (de) | 2020-06-04 |
WO2007044132A1 (en) | 2007-04-19 |
US20070082277A1 (en) | 2007-04-12 |
GB0805194D0 (en) | 2008-04-30 |
TW200720838A (en) | 2007-06-01 |
DE112006002656T5 (de) | 2008-08-21 |
CN101278233A (zh) | 2008-10-01 |
KR20080059638A (ko) | 2008-06-30 |
CN101278233B (zh) | 2014-03-19 |
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