JP2009503727A5 - - Google Patents

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Publication number
JP2009503727A5
JP2009503727A5 JP2008524992A JP2008524992A JP2009503727A5 JP 2009503727 A5 JP2009503727 A5 JP 2009503727A5 JP 2008524992 A JP2008524992 A JP 2008524992A JP 2008524992 A JP2008524992 A JP 2008524992A JP 2009503727 A5 JP2009503727 A5 JP 2009503727A5
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JP
Japan
Prior art keywords
clock
data bit
reproduction circuit
offset
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008524992A
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English (en)
Japanese (ja)
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JP2009503727A (ja
JP5121712B2 (ja
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Publication date
Priority claimed from US11/195,082 external-priority patent/US7688925B2/en
Application filed filed Critical
Publication of JP2009503727A publication Critical patent/JP2009503727A/ja
Publication of JP2009503727A5 publication Critical patent/JP2009503727A5/ja
Application granted granted Critical
Publication of JP5121712B2 publication Critical patent/JP5121712B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008524992A 2005-08-01 2006-07-19 ビット・スキュー防止方法およびシステム Active JP5121712B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/195,082 US7688925B2 (en) 2005-08-01 2005-08-01 Bit-deskewing IO method and system
US11/195,082 2005-08-01
PCT/US2006/028092 WO2007015915A1 (en) 2005-08-01 2006-07-19 Bit-deskewing io method and system

Publications (3)

Publication Number Publication Date
JP2009503727A JP2009503727A (ja) 2009-01-29
JP2009503727A5 true JP2009503727A5 (enExample) 2009-04-23
JP5121712B2 JP5121712B2 (ja) 2013-01-16

Family

ID=37440632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008524992A Active JP5121712B2 (ja) 2005-08-01 2006-07-19 ビット・スキュー防止方法およびシステム

Country Status (6)

Country Link
US (1) US7688925B2 (enExample)
EP (3) EP2533456B1 (enExample)
JP (1) JP5121712B2 (enExample)
KR (1) KR101221303B1 (enExample)
CN (1) CN101253724B (enExample)
WO (1) WO2007015915A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007052212A1 (en) * 2005-11-03 2007-05-10 Nxp B.V. Data interface and method of seeking synchronization
US8122275B2 (en) * 2006-08-24 2012-02-21 Altera Corporation Write-leveling implementation in programmable logic devices
KR100761401B1 (ko) * 2006-09-28 2007-09-27 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동 방법
KR100929845B1 (ko) * 2007-09-28 2009-12-04 주식회사 하이닉스반도체 동기식 반도체 메모리 소자 및 그의 구동방법
KR100894486B1 (ko) * 2007-11-02 2009-04-22 주식회사 하이닉스반도체 디지털 필터, 클록 데이터 복구 회로 및 그 동작방법, 반도체 메모리 장치 및 그의 동작방법
US7924637B2 (en) * 2008-03-31 2011-04-12 Advanced Micro Devices, Inc. Method for training dynamic random access memory (DRAM) controller timing delays
US7961533B2 (en) * 2008-05-27 2011-06-14 Advanced Micro Devices, Inc. Method and apparatus for implementing write levelization in memory subsystems
EP2774151B1 (en) 2011-11-01 2019-08-14 Rambus Inc. Data transmission using delayed timing signals
KR102088453B1 (ko) * 2013-12-02 2020-03-12 에스케이하이닉스 주식회사 반도체 장치
US20170207777A1 (en) * 2016-01-15 2017-07-20 Macronix International Co., Ltd. Integrated circuit device and delay circuit device having varied delay time structure
US9935762B2 (en) 2016-07-19 2018-04-03 Qualcomm Incorporated Apparatus and method for centering clock signal in cumulative data eye of parallel data in clock forwarded links
KR102502236B1 (ko) * 2017-11-20 2023-02-21 삼성전자주식회사 클락 데이터 복구 회로, 이를 포함하는 장치 및 클락 데이터 복구 방법
CN113886300B (zh) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 一种总线接口的时钟数据自适应恢复系统及芯片
US11575494B1 (en) * 2021-12-20 2023-02-07 Nvidia Corporation Link status detection for a high-speed signaling interconnect
CN116486852B (zh) * 2022-01-14 2024-06-28 长鑫存储技术有限公司 一种时钟电路、时钟对齐系统和时钟对齐方法
CN117667815B (zh) * 2023-12-01 2024-10-18 广东高云半导体科技股份有限公司 一种抗扭斜处理的电路、方法、计算机存储介质及终端

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
JP3125348B2 (ja) * 1991-09-11 2001-01-15 日本電気株式会社 パラレルビット同期方式
JPH11112483A (ja) * 1997-10-08 1999-04-23 Nec Eng Ltd データ転送システム
GB0012813D0 (en) * 2000-05-25 2000-07-19 Phoenix Vlsi Consultants Ltd Parallel data interface
US20030081709A1 (en) * 2001-10-30 2003-05-01 Sun Microsystems, Inc. Single-ended IO with dynamic synchronous deskewing architecture
CN1242577C (zh) * 2002-04-26 2006-02-15 上海贝尔有限公司 一种宽带码分多址系统上行信道的部分干扰抵消方法及装置
US20040042504A1 (en) * 2002-09-03 2004-03-04 Khoury John Michael Aligning data bits in frequency synchronous data channels
US7733915B2 (en) * 2003-05-01 2010-06-08 Genesis Microchip Inc. Minimizing buffer requirements in a digital video system
CN100499420C (zh) * 2003-08-19 2009-06-10 华为技术有限公司 一种将异步时钟域转换成同步时钟域的方法
CN100367256C (zh) * 2003-11-26 2008-02-06 北京微辰信息技术有限公司 高速sata接口数据恢复和串并转换的方法及电路模块

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