KR101221303B1 - 비트-스큐 보정 ｉｏ 방법 및 시스템 - Google Patents

비트-스큐 보정 ｉｏ 방법 및 시스템 Download PDF

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KR101221303B1
KR101221303B1 KR1020087004557A KR20087004557A KR101221303B1 KR 101221303 B1 KR101221303 B1 KR 101221303B1 KR 1020087004557 A KR1020087004557 A KR 1020087004557A KR 20087004557 A KR20087004557 A KR 20087004557A KR 101221303 B1 KR101221303 B1 KR 101221303B1
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South Korea
Prior art keywords
clock
data
data bit
clock recovery
forward strobe
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Korean (ko)
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KR20080036208A (ko
Inventor
에드워드 리
아빈드 봄디카
린 첸
클라우드 가우티에르
샘 후인
히오크-티아크 엔지
존 링
제니퍼 호
케이. 시지 엠
긴 이
조세프 마크리
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에이티아이 테크놀러지스 유엘씨
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0004—Initialisation of the receiver

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
KR1020087004557A 2005-08-01 2006-07-19 비트-스큐 보정 ｉｏ 방법 및 시스템 Active KR101221303B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/195,082 US7688925B2 (en) 2005-08-01 2005-08-01 Bit-deskewing IO method and system
US11/195,082 2005-08-01
PCT/US2006/028092 WO2007015915A1 (en) 2005-08-01 2006-07-19 Bit-deskewing io method and system

Publications (2)

Publication Number Publication Date
KR20080036208A KR20080036208A (ko) 2008-04-25
KR101221303B1 true KR101221303B1 (ko) 2013-01-10

Family

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Application Number Title Priority Date Filing Date
KR1020087004557A Active KR101221303B1 (ko) 2005-08-01 2006-07-19 비트-스큐 보정 ｉｏ 방법 및 시스템

Country Status (6)

Country Link
US (1) US7688925B2 (enExample)
EP (3) EP2533456B1 (enExample)
JP (1) JP5121712B2 (enExample)
KR (1) KR101221303B1 (enExample)
CN (1) CN101253724B (enExample)
WO (1) WO2007015915A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007052212A1 (en) * 2005-11-03 2007-05-10 Nxp B.V. Data interface and method of seeking synchronization
US8122275B2 (en) * 2006-08-24 2012-02-21 Altera Corporation Write-leveling implementation in programmable logic devices
KR100761401B1 (ko) * 2006-09-28 2007-09-27 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동 방법
KR100929845B1 (ko) * 2007-09-28 2009-12-04 주식회사 하이닉스반도체 동기식 반도체 메모리 소자 및 그의 구동방법
KR100894486B1 (ko) * 2007-11-02 2009-04-22 주식회사 하이닉스반도체 디지털 필터, 클록 데이터 복구 회로 및 그 동작방법, 반도체 메모리 장치 및 그의 동작방법
US7924637B2 (en) * 2008-03-31 2011-04-12 Advanced Micro Devices, Inc. Method for training dynamic random access memory (DRAM) controller timing delays
US7961533B2 (en) * 2008-05-27 2011-06-14 Advanced Micro Devices, Inc. Method and apparatus for implementing write levelization in memory subsystems
EP2774151B1 (en) 2011-11-01 2019-08-14 Rambus Inc. Data transmission using delayed timing signals
KR102088453B1 (ko) * 2013-12-02 2020-03-12 에스케이하이닉스 주식회사 반도체 장치
US20170207777A1 (en) * 2016-01-15 2017-07-20 Macronix International Co., Ltd. Integrated circuit device and delay circuit device having varied delay time structure
US9935762B2 (en) 2016-07-19 2018-04-03 Qualcomm Incorporated Apparatus and method for centering clock signal in cumulative data eye of parallel data in clock forwarded links
KR102502236B1 (ko) * 2017-11-20 2023-02-21 삼성전자주식회사 클락 데이터 복구 회로, 이를 포함하는 장치 및 클락 데이터 복구 방법
CN113886300B (zh) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 一种总线接口的时钟数据自适应恢复系统及芯片
US11575494B1 (en) * 2021-12-20 2023-02-07 Nvidia Corporation Link status detection for a high-speed signaling interconnect
CN116486852B (zh) * 2022-01-14 2024-06-28 长鑫存储技术有限公司 一种时钟电路、时钟对齐系统和时钟对齐方法
CN117667815B (zh) * 2023-12-01 2024-10-18 广东高云半导体科技股份有限公司 一种抗扭斜处理的电路、方法、计算机存储介质及终端

Citations (1)

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Publication number Priority date Publication date Assignee Title
US20040213067A1 (en) 2001-06-25 2004-10-28 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system

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JP3125348B2 (ja) * 1991-09-11 2001-01-15 日本電気株式会社 パラレルビット同期方式
JPH11112483A (ja) * 1997-10-08 1999-04-23 Nec Eng Ltd データ転送システム
GB0012813D0 (en) * 2000-05-25 2000-07-19 Phoenix Vlsi Consultants Ltd Parallel data interface
US20030081709A1 (en) * 2001-10-30 2003-05-01 Sun Microsystems, Inc. Single-ended IO with dynamic synchronous deskewing architecture
CN1242577C (zh) * 2002-04-26 2006-02-15 上海贝尔有限公司 一种宽带码分多址系统上行信道的部分干扰抵消方法及装置
US20040042504A1 (en) * 2002-09-03 2004-03-04 Khoury John Michael Aligning data bits in frequency synchronous data channels
US7733915B2 (en) * 2003-05-01 2010-06-08 Genesis Microchip Inc. Minimizing buffer requirements in a digital video system
CN100499420C (zh) * 2003-08-19 2009-06-10 华为技术有限公司 一种将异步时钟域转换成同步时钟域的方法
CN100367256C (zh) * 2003-11-26 2008-02-06 北京微辰信息技术有限公司 高速sata接口数据恢复和串并转换的方法及电路模块

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US20040213067A1 (en) 2001-06-25 2004-10-28 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system

Also Published As

Publication number Publication date
EP1915834A1 (en) 2008-04-30
WO2007015915A1 (en) 2007-02-08
EP2533455A3 (en) 2013-03-27
CN101253724A (zh) 2008-08-27
EP2533456B1 (en) 2020-04-01
EP2533456A3 (en) 2013-03-27
KR20080036208A (ko) 2008-04-25
US7688925B2 (en) 2010-03-30
HK1122425A1 (en) 2009-05-15
EP2533456A2 (en) 2012-12-12
JP2009503727A (ja) 2009-01-29
EP1915834B1 (en) 2017-03-01
JP5121712B2 (ja) 2013-01-16
CN101253724B (zh) 2011-08-31
EP2533455A2 (en) 2012-12-12
US20070036020A1 (en) 2007-02-15

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