JP2009503700A - 可変長命令の固定数を持つ命令キャッシュ - Google Patents
可変長命令の固定数を持つ命令キャッシュ Download PDFInfo
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- JP2009503700A JP2009503700A JP2008524216A JP2008524216A JP2009503700A JP 2009503700 A JP2009503700 A JP 2009503700A JP 2008524216 A JP2008524216 A JP 2008524216A JP 2008524216 A JP2008524216 A JP 2008524216A JP 2009503700 A JP2009503700 A JP 2009503700A
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- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
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- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
【選択図】 図3
Description
Claims (8)
- キャッシュラインごとに命令の固定数を記憶することを含む、可変命令長を持つプロセッサにおけるキャッシュ管理の方法。
- それらの長さを決定する命令を検査し、キャッシュにそれらを置く前に予め定められた境界に沿って命令を整列させることをさらに含む請求項1の方法。
- 各キャッシュラインを用いて次のフェッチアドレスを記憶することをさらに含む請求項1の方法。
- キャッシュに命令を置く前に次のフェッチアドレスを決定することをさらに含む請求項3の方法。
- 各キャッシュラインを用いてオフセットを記憶し、オフセットはキャッシュライン・タグに加えられた時、次のフェッチアドレスを生じることをさらに含む請求項1の方法。
- 可変長の命令を実行するように作動する命令実行パイプラインと、
キャッシュラインごとに可変長命令の固定数を記憶するように作動する命令キャッシュと、
キャッシュラインに命令を書き込む前に予め定められた境界に沿って可変長命令を整列させるように作動するプレデコーダを含むプロセッサ。 - 各キャッシュラインに関連した次のフェッチアドレスフィールドをさらに含む請求項6のプロセッサ。
- プレデコーダがキャッシュラインに書き込まれた最後の命令に従う命令のアドレスを計算し、かつキャッシュラインの次のフェッチアドレスフィールドにアドレスを記憶するように作動する、請求項7のプロセッサ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/193,547 US7568070B2 (en) | 2005-07-29 | 2005-07-29 | Instruction cache having fixed number of variable length instructions |
US11/193,547 | 2005-07-29 | ||
PCT/US2006/029523 WO2007016393A2 (en) | 2005-07-29 | 2006-07-26 | Instruction cache having fixed number of variable length instructions |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011237313A Division JP5341163B2 (ja) | 2005-07-29 | 2011-10-28 | 可変長命令の固定数を持つ命令キャッシュ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009503700A true JP2009503700A (ja) | 2009-01-29 |
JP4927840B2 JP4927840B2 (ja) | 2012-05-09 |
Family
ID=37451109
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008524216A Expired - Fee Related JP4927840B2 (ja) | 2005-07-29 | 2006-07-26 | 可変長命令の固定数を持つ命令キャッシュ |
JP2011237313A Expired - Fee Related JP5341163B2 (ja) | 2005-07-29 | 2011-10-28 | 可変長命令の固定数を持つ命令キャッシュ |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011237313A Expired - Fee Related JP5341163B2 (ja) | 2005-07-29 | 2011-10-28 | 可変長命令の固定数を持つ命令キャッシュ |
Country Status (6)
Country | Link |
---|---|
US (1) | US7568070B2 (ja) |
EP (1) | EP1910919A2 (ja) |
JP (2) | JP4927840B2 (ja) |
KR (1) | KR101005633B1 (ja) |
CN (2) | CN104657110B (ja) |
WO (1) | WO2007016393A2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009535743A (ja) * | 2006-05-01 | 2009-10-01 | クゥアルコム・インコーポレイテッド | 可変長命令をキャッシングするための方法及び装置 |
JP2012513067A (ja) * | 2008-12-30 | 2012-06-07 | インテル・コーポレーション | トランザクショナルメモリ(tm)システムにおける読み出し及び書き込み監視属性 |
JP2014006685A (ja) * | 2012-06-25 | 2014-01-16 | Renesas Electronics Corp | 半導体装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8898437B2 (en) * | 2007-11-02 | 2014-11-25 | Qualcomm Incorporated | Predecode repair cache for instructions that cross an instruction cache line |
US9753858B2 (en) * | 2011-11-30 | 2017-09-05 | Advanced Micro Devices, Inc. | DRAM cache with tags and data jointly stored in physical rows |
US10001993B2 (en) | 2013-08-08 | 2018-06-19 | Linear Algebra Technologies Limited | Variable-length instruction buffer management |
US11768689B2 (en) | 2013-08-08 | 2023-09-26 | Movidius Limited | Apparatus, systems, and methods for low power computational imaging |
US10853074B2 (en) * | 2014-05-01 | 2020-12-01 | Netronome Systems, Inc. | Table fetch processor instruction using table number to base address translation |
CN110515658A (zh) * | 2014-07-30 | 2019-11-29 | 莫维迪厄斯有限公司 | 用于管理可变长度指令的方法和设备 |
US9916251B2 (en) | 2014-12-01 | 2018-03-13 | Samsung Electronics Co., Ltd. | Display driving apparatus and cache managing method thereof |
CN106528450B (zh) * | 2016-10-27 | 2019-09-17 | 上海兆芯集成电路有限公司 | 数据预先提取方法及使用此方法的装置 |
CN108415729A (zh) * | 2017-12-29 | 2018-08-17 | 北京智芯微电子科技有限公司 | 一种cpu指令异常的处理方法及装置 |
CN110750303B (zh) * | 2019-09-25 | 2020-10-20 | 支付宝(杭州)信息技术有限公司 | 基于fpga的流水线式指令读取方法及装置 |
Citations (4)
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US6253309B1 (en) * | 1998-09-21 | 2001-06-26 | Advanced Micro Devices, Inc. | Forcing regularity into a CISC instruction set by padding instructions |
JP2003511789A (ja) * | 1999-10-14 | 2003-03-25 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 整列情報をキャッシュするための装置および方法 |
JP2003131945A (ja) * | 2001-10-25 | 2003-05-09 | Hitachi Ltd | キャッシュメモリ装置 |
WO2005041024A2 (en) * | 2003-10-01 | 2005-05-06 | Advanced Micro Devices, Inc. | System and method for handling exceptional instructions in a trace cache based processor |
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EP0498654B1 (en) * | 1991-02-08 | 2000-05-10 | Fujitsu Limited | Cache memory processing instruction data and data processor including the same |
WO1996029645A1 (en) * | 1995-03-23 | 1996-09-26 | International Business Machines Corporation | Object-code compatible representation of very long instruction word programs |
EP0843848B1 (en) * | 1996-05-15 | 2004-04-07 | Koninklijke Philips Electronics N.V. | Vliw processor which processes compressed instruction format |
TW357318B (en) | 1997-03-18 | 1999-05-01 | Ind Tech Res Inst | Branching forecast and reading device for unspecified command length extra-purity pipeline processor |
US6112299A (en) * | 1997-12-31 | 2000-08-29 | International Business Machines Corporation | Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching |
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JP3490007B2 (ja) * | 1998-12-17 | 2004-01-26 | 富士通株式会社 | 命令制御装置 |
US6779100B1 (en) * | 1999-12-17 | 2004-08-17 | Hewlett-Packard Development Company, L.P. | Method and device for address translation for compressed instructions |
-
2005
- 2005-07-29 US US11/193,547 patent/US7568070B2/en active Active
-
2006
- 2006-07-26 WO PCT/US2006/029523 patent/WO2007016393A2/en active Application Filing
- 2006-07-26 CN CN201510049939.1A patent/CN104657110B/zh active Active
- 2006-07-26 CN CNA2006800343645A patent/CN101268440A/zh active Pending
- 2006-07-26 EP EP06788854A patent/EP1910919A2/en not_active Ceased
- 2006-07-26 JP JP2008524216A patent/JP4927840B2/ja not_active Expired - Fee Related
- 2006-07-26 KR KR1020087004751A patent/KR101005633B1/ko active IP Right Grant
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2011
- 2011-10-28 JP JP2011237313A patent/JP5341163B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US6253309B1 (en) * | 1998-09-21 | 2001-06-26 | Advanced Micro Devices, Inc. | Forcing regularity into a CISC instruction set by padding instructions |
JP2003511789A (ja) * | 1999-10-14 | 2003-03-25 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 整列情報をキャッシュするための装置および方法 |
JP2003131945A (ja) * | 2001-10-25 | 2003-05-09 | Hitachi Ltd | キャッシュメモリ装置 |
WO2005041024A2 (en) * | 2003-10-01 | 2005-05-06 | Advanced Micro Devices, Inc. | System and method for handling exceptional instructions in a trace cache based processor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009535743A (ja) * | 2006-05-01 | 2009-10-01 | クゥアルコム・インコーポレイテッド | 可変長命令をキャッシングするための方法及び装置 |
JP4755281B2 (ja) * | 2006-05-01 | 2011-08-24 | クゥアルコム・インコーポレイテッド | 可変長命令をキャッシングするための方法及び装置 |
JP2012513067A (ja) * | 2008-12-30 | 2012-06-07 | インテル・コーポレーション | トランザクショナルメモリ(tm)システムにおける読み出し及び書き込み監視属性 |
JP2014006685A (ja) * | 2012-06-25 | 2014-01-16 | Renesas Electronics Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
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KR101005633B1 (ko) | 2011-01-05 |
JP5341163B2 (ja) | 2013-11-13 |
EP1910919A2 (en) | 2008-04-16 |
CN104657110A (zh) | 2015-05-27 |
US20070028050A1 (en) | 2007-02-01 |
US7568070B2 (en) | 2009-07-28 |
CN104657110B (zh) | 2020-08-18 |
WO2007016393A2 (en) | 2007-02-08 |
JP4927840B2 (ja) | 2012-05-09 |
KR20080031981A (ko) | 2008-04-11 |
CN101268440A (zh) | 2008-09-17 |
WO2007016393A3 (en) | 2007-06-28 |
JP2012074046A (ja) | 2012-04-12 |
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