JP2009303208A5 - - Google Patents

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Publication number
JP2009303208A5
JP2009303208A5 JP2009118360A JP2009118360A JP2009303208A5 JP 2009303208 A5 JP2009303208 A5 JP 2009303208A5 JP 2009118360 A JP2009118360 A JP 2009118360A JP 2009118360 A JP2009118360 A JP 2009118360A JP 2009303208 A5 JP2009303208 A5 JP 2009303208A5
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JP
Japan
Prior art keywords
data
message
logical
control information
flow control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009118360A
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English (en)
Japanese (ja)
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JP2009303208A (ja
Filing date
Publication date
Priority claimed from US12/140,941 external-priority patent/US20090310489A1/en
Application filed filed Critical
Publication of JP2009303208A publication Critical patent/JP2009303208A/ja
Publication of JP2009303208A5 publication Critical patent/JP2009303208A5/ja
Pending legal-status Critical Current

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JP2009118360A 2008-06-17 2009-05-15 シリアルデータインターフェースを使用して複数の論理データストリームのそれぞれに対応するデータを送信／受信する方法及び装置 Pending JP2009303208A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/140,941 US20090310489A1 (en) 2008-06-17 2008-06-17 Methods and apparatus using a serial data interface to transmit/receive data corresponding to each of a plurality of logical data streams

Publications (2)

Publication Number Publication Date
JP2009303208A JP2009303208A (ja) 2009-12-24
JP2009303208A5 true JP2009303208A5 (enExample) 2012-06-28

Family

ID=40833662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009118360A Pending JP2009303208A (ja) 2008-06-17 2009-05-15 シリアルデータインターフェースを使用して複数の論理データストリームのそれぞれに対応するデータを送信／受信する方法及び装置

Country Status (3)

Country Link
US (1) US20090310489A1 (enExample)
JP (1) JP2009303208A (enExample)
GB (1) GB2460920B (enExample)

Families Citing this family (12)

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JP2009182458A (ja) * 2008-01-29 2009-08-13 Sony Corp 通信装置、通信システム、通信方法及びプログラム
JP2014506779A (ja) * 2011-02-23 2014-03-17 ディーア・アンド・カンパニー 位置決定において時間遅延に対する補償を用いて電気モータを制御するための方法およびシステム
US8723460B2 (en) 2011-02-23 2014-05-13 Deere & Company Method and system for controlling an electric motor with compensation for time delay in position determination
JP5840088B2 (ja) * 2012-07-20 2016-01-06 株式会社日立ハイテクノロジーズ 端末通信装置および分散制御システム
US9575768B1 (en) 2013-01-08 2017-02-21 Marvell International Ltd. Loading boot code from multiple memories
EP3028145A1 (en) * 2013-07-31 2016-06-08 Marvell World Trade Ltd. Parallelizing boot operations
GB2539445A (en) * 2015-06-16 2016-12-21 Nordic Semiconductor Asa Data processing
US20170017584A1 (en) * 2015-07-15 2017-01-19 Microchip Technology Incorporated SPI Interface With Less-Than-8-Bit Bytes And Variable Packet Size
EP3539293A1 (en) * 2016-11-09 2019-09-18 Renesas Electronics Corporation Communications network controller module
GB2562259B (en) * 2017-05-09 2020-03-04 Advanced Risc Mach Ltd Electronic communications control
US10191871B2 (en) * 2017-06-20 2019-01-29 Infineon Technologies Ag Safe double buffering using DMA safe linked lists
CN111475460B (zh) * 2020-04-06 2023-08-29 桂林电子科技大学 基于NoC的高速数据采集系统与上位机通信接口控制器

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718773A1 (en) * 1994-12-19 1996-06-26 Advanced Micro Devices, Inc. Bus access arbiter
US6023478A (en) * 1996-03-29 2000-02-08 Hewlett-Packard Method and apparatus for communicating data byte streams
US6098124A (en) * 1998-04-09 2000-08-01 National Instruments Corporation Arbiter for transferring largest accumulated data block output from data buffers over serial bus
US6751228B1 (en) * 1999-03-23 2004-06-15 Yamaha Corporation Packet handler of audio data by isochronous mode
US6684272B1 (en) * 1999-12-23 2004-01-27 Intel Corporation Throughput enhancement for a universal host controller interface in a universal serial bus
US6944617B2 (en) * 2001-12-28 2005-09-13 Intel Corporation Communicating transaction types between agents in a computer system using packet headers including an extended type/extended length field
US20030123393A1 (en) * 2002-01-03 2003-07-03 Feuerstraeter Mark T. Method and apparatus for priority based flow control in an ethernet architecture
US20040249964A1 (en) * 2003-03-06 2004-12-09 Thibault Mougel Method of data transfer and apparatus therefor
JP4489074B2 (ja) * 2003-05-16 2010-06-23 パナソニック株式会社 通信ネットワークシステムにおいて用いられる通信端末、方法、プログラム、記録媒体、及び集積回路
US7295519B2 (en) * 2003-06-20 2007-11-13 Motorola, Inc. Method of quality of service based flow control within a distributed switch fabric network
US8090857B2 (en) * 2003-11-24 2012-01-03 Qualcomm Atheros, Inc. Medium access control layer that encapsulates data from a plurality of received data units into a plurality of independently transmittable blocks
JP4476088B2 (ja) * 2004-09-28 2010-06-09 株式会社リコー データ転送装置及び画像形成システム
US20060101178A1 (en) * 2004-11-08 2006-05-11 Zhong Tina C Arbitration in a multi-protocol environment
JP4457306B2 (ja) * 2005-03-30 2010-04-28 株式会社デンソー 自動車用制御ユニット
US7986700B2 (en) * 2006-09-25 2011-07-26 Futurewei Technologies, Inc. Multiplexed data stream circuit architecture

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