GB2460920B - Method and apparatus using a serial data interface to transmit/receive data corresponding to each of a plurality of logical data streams - Google Patents

Method and apparatus using a serial data interface to transmit/receive data corresponding to each of a plurality of logical data streams

Info

Publication number
GB2460920B
GB2460920B GB0907906.2A GB0907906A GB2460920B GB 2460920 B GB2460920 B GB 2460920B GB 0907906 A GB0907906 A GB 0907906A GB 2460920 B GB2460920 B GB 2460920B
Authority
GB
United Kingdom
Prior art keywords
transmit
logical
interface
data corresponding
streams
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0907906.2A
Other languages
English (en)
Other versions
GB0907906D0 (en
GB2460920A (en
Inventor
Andrew M Bennett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of GB0907906D0 publication Critical patent/GB0907906D0/en
Publication of GB2460920A publication Critical patent/GB2460920A/en
Application granted granted Critical
Publication of GB2460920B publication Critical patent/GB2460920B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4278—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H04L12/5694—

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
GB0907906.2A 2008-06-17 2009-05-08 Method and apparatus using a serial data interface to transmit/receive data corresponding to each of a plurality of logical data streams Active GB2460920B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/140,941 US20090310489A1 (en) 2008-06-17 2008-06-17 Methods and apparatus using a serial data interface to transmit/receive data corresponding to each of a plurality of logical data streams

Publications (3)

Publication Number Publication Date
GB0907906D0 GB0907906D0 (en) 2009-06-24
GB2460920A GB2460920A (en) 2009-12-23
GB2460920B true GB2460920B (en) 2012-10-31

Family

ID=40833662

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0907906.2A Active GB2460920B (en) 2008-06-17 2009-05-08 Method and apparatus using a serial data interface to transmit/receive data corresponding to each of a plurality of logical data streams

Country Status (3)

Country Link
US (1) US20090310489A1 (enExample)
JP (1) JP2009303208A (enExample)
GB (1) GB2460920B (enExample)

Families Citing this family (12)

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JP2009182458A (ja) * 2008-01-29 2009-08-13 Sony Corp 通信装置、通信システム、通信方法及びプログラム
JP2014506779A (ja) * 2011-02-23 2014-03-17 ディーア・アンド・カンパニー 位置決定において時間遅延に対する補償を用いて電気モータを制御するための方法およびシステム
US8723460B2 (en) 2011-02-23 2014-05-13 Deere & Company Method and system for controlling an electric motor with compensation for time delay in position determination
JP5840088B2 (ja) * 2012-07-20 2016-01-06 株式会社日立ハイテクノロジーズ 端末通信装置および分散制御システム
US9575768B1 (en) 2013-01-08 2017-02-21 Marvell International Ltd. Loading boot code from multiple memories
EP3028145A1 (en) * 2013-07-31 2016-06-08 Marvell World Trade Ltd. Parallelizing boot operations
GB2539445A (en) * 2015-06-16 2016-12-21 Nordic Semiconductor Asa Data processing
US20170017584A1 (en) * 2015-07-15 2017-01-19 Microchip Technology Incorporated SPI Interface With Less-Than-8-Bit Bytes And Variable Packet Size
EP3539293A1 (en) * 2016-11-09 2019-09-18 Renesas Electronics Corporation Communications network controller module
GB2562259B (en) * 2017-05-09 2020-03-04 Advanced Risc Mach Ltd Electronic communications control
US10191871B2 (en) * 2017-06-20 2019-01-29 Infineon Technologies Ag Safe double buffering using DMA safe linked lists
CN111475460B (zh) * 2020-04-06 2023-08-29 桂林电子科技大学 基于NoC的高速数据采集系统与上位机通信接口控制器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796961A (en) * 1994-12-19 1998-08-18 Advanced Micro Devices, Inc. Heuristic bus access arbiter
US6023478A (en) * 1996-03-29 2000-02-08 Hewlett-Packard Method and apparatus for communicating data byte streams
US6098124A (en) * 1998-04-09 2000-08-01 National Instruments Corporation Arbiter for transferring largest accumulated data block output from data buffers over serial bus
US20030123393A1 (en) * 2002-01-03 2003-07-03 Feuerstraeter Mark T. Method and apparatus for priority based flow control in an ethernet architecture
US6684272B1 (en) * 1999-12-23 2004-01-27 Intel Corporation Throughput enhancement for a universal host controller interface in a universal serial bus
US20040264485A1 (en) * 1999-03-23 2004-12-30 Yamaha Corporation Packet handler of audio data by isochronous mode

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6944617B2 (en) * 2001-12-28 2005-09-13 Intel Corporation Communicating transaction types between agents in a computer system using packet headers including an extended type/extended length field
US20040249964A1 (en) * 2003-03-06 2004-12-09 Thibault Mougel Method of data transfer and apparatus therefor
JP4489074B2 (ja) * 2003-05-16 2010-06-23 パナソニック株式会社 通信ネットワークシステムにおいて用いられる通信端末、方法、プログラム、記録媒体、及び集積回路
US7295519B2 (en) * 2003-06-20 2007-11-13 Motorola, Inc. Method of quality of service based flow control within a distributed switch fabric network
US8090857B2 (en) * 2003-11-24 2012-01-03 Qualcomm Atheros, Inc. Medium access control layer that encapsulates data from a plurality of received data units into a plurality of independently transmittable blocks
JP4476088B2 (ja) * 2004-09-28 2010-06-09 株式会社リコー データ転送装置及び画像形成システム
US20060101178A1 (en) * 2004-11-08 2006-05-11 Zhong Tina C Arbitration in a multi-protocol environment
JP4457306B2 (ja) * 2005-03-30 2010-04-28 株式会社デンソー 自動車用制御ユニット
US7986700B2 (en) * 2006-09-25 2011-07-26 Futurewei Technologies, Inc. Multiplexed data stream circuit architecture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796961A (en) * 1994-12-19 1998-08-18 Advanced Micro Devices, Inc. Heuristic bus access arbiter
US6023478A (en) * 1996-03-29 2000-02-08 Hewlett-Packard Method and apparatus for communicating data byte streams
US6098124A (en) * 1998-04-09 2000-08-01 National Instruments Corporation Arbiter for transferring largest accumulated data block output from data buffers over serial bus
US20040264485A1 (en) * 1999-03-23 2004-12-30 Yamaha Corporation Packet handler of audio data by isochronous mode
US6684272B1 (en) * 1999-12-23 2004-01-27 Intel Corporation Throughput enhancement for a universal host controller interface in a universal serial bus
US20030123393A1 (en) * 2002-01-03 2003-07-03 Feuerstraeter Mark T. Method and apparatus for priority based flow control in an ethernet architecture

Also Published As

Publication number Publication date
GB0907906D0 (en) 2009-06-24
JP2009303208A (ja) 2009-12-24
GB2460920A (en) 2009-12-23
US20090310489A1 (en) 2009-12-17

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