JP2009295937A - Dummy exposure substrate and method of manufacturing the same, immersion exposure apparatus, and method of manufacturing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus which prevents causes of a pseudo-color, color mixture, an afterimage and noise, and which has an improved aperture ratio and improved sensitivity, and to provide an electronic apparatus using the solid-state imaging apparatus. <P>SOLUTION: The solid-state imaging apparatus is constituted of a plurality of photodiodes PD1-PD3 formed in different depth and a plurality of vertical transistors Tr1-Tr3 in a substrate 21 in a unit pixel region 20. The plurality of vertical transistors Tr1-Tr3 are the ones for reading signal electric charges photoelectrically converted by the plurality of photodiodes PD1-PD3. Then, the plurality of vertical transistors Tr1-Tr3 are formed in the depth direction from one surface side of the substrate 21 in such a way that their gate parts are formed in depths corresponding to the plurality of respective photodiodes PD1-PD3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device having a plurality of photodiodes in a unit pixel region, a driving method thereof, and an electronic apparatus using the solid-state imaging device.

  Color spectroscopy in a CCD image sensor or a CMOS image sensor that is a solid-state imaging device is realized mainly by using a color filter. In an image sensor using a color filter, one type of color filter is mounted on one pixel, and three pixel circuits mainly having red, green, and blue color filters are arranged next to each other. Therefore, strictly speaking, light that can be received in one pixel is only one color corresponding to the color filter. Therefore, in an image sensor using color filters, color generation is performed by using information of light incident on adjacent pixels on which color filters of different colors are mounted.

  Therefore, in an image sensor using a color filter, a false color is generated in which a color generated in an arbitrary pixel is different from a color of light actually incident on the pixel. Further, by using a color filter, for example, in the case of a red color filter, incident light of green and blue is absorbed by the color filter and does not reach the light receiving unit. For this reason, 2/3 or more of the incident light quantity is lost. The loss of the incident light amount occurs similarly in the green and blue color filters.

  Therefore, in order to efficiently use the amount of incident light and prevent the occurrence of false colors, a method of performing spectroscopy by forming a plurality of photodiodes in the depth direction in the substrate in one pixel has been developed. .

  In Patent Document 1, for example, as shown in FIG. 9, a three-layer structure of n-type semiconductor layer 102 / p-type semiconductor layer 104 / n-type semiconductor layer 106 is formed in a p-type Si substrate 100, and the depth is increased. A color separation method is described in which blue, green, and red light are photoelectrically converted and extracted from the shallower side. In this method, on the surface of the Si substrate 100, blue, green, and red signals are output to the outside by the respective terminals connected to the respective layers. This utilizes the wavelength length and the light absorption property in the depth direction. As a result, color spectroscopy can be performed with one pixel, and generation of false colors can be suppressed. Therefore, a low-pass filter is not necessary. Further, since no color filter is used, colors having different wavelengths of red, green, and blue enter the unit pixel. For this reason, the loss of light quantity is also reduced.

JP 2002-513145 A

  However, as in Patent Document 1, in the case of utilizing the light absorption property in the wavelength length and depth direction, a photodiode that photoelectrically converts red light having a long wavelength and accumulates charges is the surface of the Si substrate 100. To a depth of about 2 μm. For this reason, the distance to the output terminal on the surface of the Si substrate 100 is long, and it is very difficult to completely transfer the charges accumulated in the photodiode, which causes afterimages. In addition, light enters from the surface direction of the Si substrate 100, and charges generated by photoelectric conversion are accumulated in a photodiode formed of several well layers. In this case, the photodiode end has a structure reaching the surface of the Si substrate 100, and the depth of the PN junction at that portion is different from the depth of the PN junction at the center of the photodiode. This causes color mixing and causes noise on the surface of the Si substrate 100.

  In view of the above-described points, the present invention provides a solid-state imaging device and a driving method thereof that prevent false color, afterimage, noise, and color mixing and improve the aperture ratio and sensitivity of pixels. In addition, the present invention provides an electronic device using the solid-state imaging device.

  In order to solve the above problems and achieve the object of the present invention, a solid-state imaging device of the present invention includes a plurality of photodiodes formed at different depths in a substrate in a unit pixel region, a plurality of vertical transistors, Consists of The plurality of vertical transistors are transistors for reading signal charges photoelectrically converted by a plurality of photodiodes. The plurality of vertical transistors are formed in the depth direction from one surface side of the substrate so that the gate portions thereof are formed at depths corresponding to the plurality of photodiodes.

  In the solid-state imaging device of the present invention, since a plurality of photodiodes are formed in the unit pixel region, a plurality of colors are read from the unit pixel region. In addition, since the vertical transistor is formed so that the gate portion thereof has a depth corresponding to each of the plurality of photodiodes, all signal charges of the target photodiode are read out. Each gate portion has a different gate length.

An electronic apparatus according to the present invention includes a solid-state imaging device, an optical lens system, and a signal processing device that processes an output signal of the solid-state imaging device.
In particular, the solid-state imaging device includes a plurality of photodiodes formed at different depths and a plurality of vertical transistors in a substrate in a unit pixel region. The plurality of vertical transistors are transistors for reading signal charges photoelectrically converted by a plurality of photodiodes. The plurality of vertical transistors are formed in the depth direction from one surface side of the substrate so that the gate length is formed to a depth corresponding to each of the plurality of photodiodes.

  In the electronic apparatus of the present invention, light that has entered the solid-state imaging device via the optical lens system is photoelectrically converted by a plurality of photodiodes in the unit pixel region. Then, the photoelectrically converted signal charge is read out by a vertical transistor formed at the photodiode depth, and forms an image.

  According to the solid-state imaging device and the driving method thereof of the present invention, it is possible to reduce false color, afterimage, noise, and color mixing and improve sensitivity. In addition, a color filter and a low-pass filter are not necessary.

  In addition, according to the electronic device of the present invention, an image with reduced false color, afterimage, noise, and color mixture and improved sensitivity can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic configuration of an embodiment of a solid-state imaging device, that is, a CMOS image sensor to which the present invention is applied. A solid-state imaging device 1 according to this embodiment includes an imaging region 3 in which pixels 2 including photodiodes as a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate, for example, a Si substrate 11. And a vertical drive circuit 4 as a peripheral circuit thereof, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. Then, the clock signal and control signal generated there are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6 and the like.

  The vertical drive circuit 4 is constituted by a shift register, for example, and selectively scans each pixel 2 in the imaging region 3 in the vertical direction sequentially in units of rows. Then, a pixel signal based on a signal charge generated according to the amount of received light in the photoelectric conversion unit (hereinafter referred to as a photodiode) of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line 9.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and outputs a signal output from the pixels 2 for one row for each pixel column to a black reference pixel (not shown, but around the effective pixel region). Signal processing such as noise removal and signal amplification is performed by the signal from At the output stage of the column signal processing circuit 5, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.

The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.

  The solid-state imaging device in the first to fifth embodiments described below constitutes the solid-state imaging device 1 in FIG. 1, and in particular, the cross-sectional configuration of the pixel 2 in the effective pixel region is different. Since other configurations are the same as those in FIG. 1, in the first to fifth embodiments, only the cross-sectional configuration of the main part is shown, and the description of the other configurations is omitted.

[First Embodiment]
FIG. 2 shows a cross-sectional configuration of the pixel portion of the solid-state imaging device according to the first embodiment of the present invention. FIG. 2 shows a cross-sectional configuration for one pixel, that is, in the unit pixel region 20.

  The solid-state imaging device according to the present embodiment is formed in such a manner that a plurality of layers are alternately stacked in the depth direction from one surface (hereinafter referred to as the front surface) side in the first conductivity type silicon substrate 21. A conductive semiconductor layer and a second conductive semiconductor layer are included. In addition, a plurality of vertical transistors Tr1, Tr2, Tr3 are formed to a desired depth from the surface side of the silicon substrate 21. The vertical transistors Tr1, Tr2, Tr3 correspond to charge transfer transistors described later. A wiring layer 47 is formed on the front surface side of the silicon substrate 21, and an on-chip lens 31 is formed on the back surface side of the silicon substrate 21. That is, the solid-state imaging device of the present embodiment is an example of a back-illuminated solid-state imaging device configured so that light enters from the side opposite to the wiring layer 47.

  In the following description, the first conductivity type is p-type, the second conductivity type is n-type, the first conductivity type semiconductor layer formed to be stacked is a p-type semiconductor layer, and the second conductivity type semiconductor is The layer is an n-type semiconductor layer.

  The p-type semiconductor layer and the n-type semiconductor layer formed so as to be alternately stacked in the silicon substrate 21 are formed in the unit pixel region 20 in a region to be a photodiode. In the present embodiment, the first p-type semiconductor layer 28, the first n-type semiconductor layer 27, the second p-type semiconductor layer 26, and the second n-type semiconductor layer 25 are arranged from the surface side of the silicon substrate 21. The third p-type semiconductor layer 24 and the third n-type semiconductor layer 23 are stacked in this order. A plurality of photodiodes are formed in the unit pixel region 20 by the p-type semiconductor layer and the n-type semiconductor layer formed so as to be alternately stacked. The first to third p-type semiconductor layers 28, 26, and 24 and the first to third n-type semiconductor layers 27, 25, and 23 are formed in a flat plate shape and stacked. . In the present embodiment, the first to third p-type semiconductor layers 28, 26, and 24 to be stacked have a higher impurity concentration than the p-type silicon substrate 21.

  Here, the first n-type semiconductor layer 27 formed on the top surface side has a pn junction j1 depth in the first p-type semiconductor layer 28 and the first n-type semiconductor layer 27 that is light from the back side. When irradiated, it is formed to have a depth corresponding to the position where red light is absorbed. The second n-type semiconductor layer 25 formed at the second depth from the front surface side has a pn junction j2 depth in the second p-type semiconductor layer 26 and the second n-type semiconductor layer 25 from the back surface side. When irradiated, it is formed to have a depth corresponding to the position where green light is absorbed. The third n-type semiconductor layer 23 formed on the rearmost surface side has a pn junction j3 depth in the third p-type semiconductor layer 24 and the third n-type semiconductor layer 23 irradiated with light from the rear surface side. And a depth corresponding to the position where blue light is absorbed.

The first p-type semiconductor layer 28 and the first n-type semiconductor layer 27 form a first photodiode PD1 that photoelectrically converts red light.
The second p-type semiconductor layer 26 and the second n-type semiconductor layer 25 form a second photodiode PD2 that photoelectrically converts green light.
The third p-type semiconductor layer 24 and the third n-type semiconductor layer 23 form a third photodiode PD3 that photoelectrically converts blue light.

  In the first to third photodiodes PD1 to PD3, the pn junctions j1 to j3 are formed, so that the first to third n-type semiconductor layers 27, 25, and 23 constitute potential wells, respectively. Therefore, in the first to third photodiodes PD1 to PD3, the signal charges photoelectrically converted in the first to third n-type semiconductor layers 27, 25, and 23 in the vicinity thereof are respectively first to first. 3 n-type semiconductor layers 27, 25, and 23 are accumulated in the potential well formed. That is, each of the first to third n-type semiconductor layers 27, 25, and 23 corresponds to a signal storage region. The signal charge storage capacity is determined by the potential difference between the n-type semiconductor layer and the p-type semiconductor layer and the depletion layer capacity. In the present embodiment, since the first to third p-type semiconductor layers 28, 26, and 24 have a higher impurity concentration than the silicon substrate 21, the signals in the first to third photodiodes PD1 to PD3. The charge storage capacity is sufficiently secured.

In this embodiment, transfer transistors Tr1, Tr2, Tr3 having gate electrodes 33, 37, 42 corresponding to the first to third photodiodes PD1 to PD3 described above are formed.
First, the gate electrode 33 of the first transfer transistor Tr1 is formed to a depth reaching the pn junction j1 of the first photodiode PD1 from the surface side of the silicon substrate 21. The gate electrode 37 of the second transfer transistor Tr2 is formed to a depth reaching the pn junction j2 of the second photodiode PD2 from the surface side of the silicon substrate 21. The gate electrode 42 of the third transfer transistor Tr3 is formed to a depth reaching the pn junction j3 of the third photodiode PD3 from the surface side of the silicon substrate 21.

  The gate electrodes 33, 37, and 42 are provided with vertical openings in the silicon substrate 21 on which the first to third photodiodes PD1 to PD3 are formed, and the openings are electrodes through the gate insulating film 34. Formed by embedding material. The gate electrodes 33, 37, and 42 are formed in a columnar shape or a prismatic shape, and are formed in a vertical shape that is long in the depth direction of the silicon substrate 21. In each of the vertical transfer transistors Tr1, Tr2, and Tr3, a gate portion is configured by the gate electrodes 33, 37, and 42, the gate insulating film 34, and a channel portion described later.

  Here, the gate length of the gate portion including the gate electrode 42 of the third transfer transistor Tr3 is longer than the gate length of the gate portion including the gate electrode 37 of the second transfer transistor Tr2, and the second transfer transistor Tr2 The gate length of the gate portion including the gate electrode 37 is longer than the gate length of the gate portion including the gate electrode 33 of the first transfer transistor Tr1.

  Further, on the surface of the silicon substrate 21 and in contact with the gate portions corresponding to the respective gate electrodes 33, 37, 42, high impurity concentration n-type semiconductor regions, so-called n + source / drain regions 46, 41 are provided. 45 are individually formed. As described above, the first to third transfer transistors Tr1, Tr2, Tr3 constituting the solid-state imaging device according to the present embodiment have the vertical gate electrodes 33, 37 in which the signal charges are embedded in the silicon substrate 21. , 42 is a vertical transistor transferred in the vertical direction.

  With this configuration, the channel portion 39 of the first transfer transistor Tr1 is formed from the first n-type semiconductor layer 27 to the n + source / drain region 46 along the vertical gate electrode 33. The channel portion 40 of the second transfer transistor Tr 2 is formed from the second n-type semiconductor layer 25 to the n + source / drain region 41 along the vertical gate electrode 37. The channel portion 44 of the third transfer transistor Tr3 is formed from the third n-type semiconductor layer 23 to the n + source / drain region 45 along the vertical gate electrode 42. These channel portions 39, 40, and 44 are preferably formed in a direction perpendicular to the surface of the silicon substrate 21 along the respective gate electrodes 33, 37, and 42.

In the first transfer transistor Tr1, the first n-type semiconductor layer 27 constituting the first photodiode PD1 also serves as a source / drain region. As a result, the signal charge accumulated in the first n-type semiconductor layer 27 passes through the channel portion 39 and is transferred to the n + source / drain region 46.
In the second transfer transistor Tr2, the second n-type semiconductor layer 25 constituting the second photodiode PD2 also serves as a source / drain region. As a result, the signal charge accumulated in the second n-type semiconductor layer 25 passes through the channel portion 40 and is transferred to the n + source / drain region 41.
In the third transfer transistor Tr3, the third n-type semiconductor layer 23 constituting the third photodiode PD3 also serves as a source / drain region. As a result, the signal charge accumulated in the third n-type semiconductor layer 23 passes through the channel portion 44 and is transferred to the n + source / drain region 45.

  In the first to third transfer transistors Tr1 to Tr3, n + source / drain regions 46, 41, 45 formed on the surface of the silicon substrate 21 and in contact with the gate electrodes 33, 37, 42, respectively, This is a floating diffusion FD.

  A wiring layer 47 is formed on the surface side of the silicon substrate 21. A desired wiring is formed on the wiring layer 47 through the interlayer insulating film 30. The present embodiment is an example having wirings M1 to M3 configured in three layers, and these wirings M1 to M3 are connected to a desired gate electrode or a power source. The wirings M1 to M3 are connected by providing, for example, contacts 49 and VIA.

  An on-chip lens 31 is configured on the back side of the silicon substrate 21. Then, the light irradiated from the back surface side of the silicon substrate 21 is collected by the on-chip lens 31 and is incident on the unit pixel region 20 through the silicon oxide film 32, for example.

  In the solid-state imaging device having the above configuration, light incident from the back side of the silicon substrate 21 is photoelectrically converted by the first to third photodiodes PD1 to PD3, and signal charges are accumulated. Since the first to third photodiodes PD1 to PD3 are formed at different depths in the silicon substrate 21, the first to third photodiodes PD1 to PD3 absorb light having different wavelengths. Is done. The first photodiode PD1 absorbs red light, the second photodiode PD2 absorbs green light, and the third photodiode PD3 absorbs blue light.

  Then, each light incident on the first to third photodiodes PD1 to PD3 is photoelectrically converted, and signal charges due to the photoelectric conversion are applied to the first to third n-type semiconductor layers 27, 25, and 23. Each is accumulated. That is, signal charges due to photoelectric conversion of red light are accumulated in the first n-type semiconductor layer 27, and signal charges due to photoelectric conversion of green light are accumulated in the second n-type semiconductor layer 25. The third n-type semiconductor layer 23 accumulates signal charges due to photoelectric conversion of blue light.

  As described above, the solid-state imaging device according to the present embodiment includes the first to third photodiodes PD1 to PD3 in the unit pixel region 20, and thus can store signal charges of three colors of light.

  By the way, in the solid-state imaging device of the present embodiment, the gate electrode 42 of the third transfer transistor Tr3 having the longest channel length is connected to the first to third n-type semiconductor layers 27 and 25 via the gate insulating film 34. , 23 are all in contact. Further, the gate electrode 37 of the second transfer transistor Tr2 having the second longest channel length is in contact with the first and second n-type semiconductor layers 27 and 25 through the gate insulating film.

  FIG. 3 shows an equivalent circuit of unit pixels in the solid-state imaging device according to the present embodiment. The unit pixel includes a first photodiode PD1, a second photodiode PD2, and a third photodiode PD3, and each of the photodiodes PD1, PD2, and PD3 includes the first, second, and third photodiodes, respectively. The floating diffusions FD1, FD2, and FD3 are connected through the transfer transistors Tr1, Tr2, and Tr3. The second transfer transistor Tr2 includes two transistors Q2 and Q3 that are equivalently connected in series. The third transfer transistor Tr3 includes three transistors Q4, Q5, and Q6 that are equivalently connected in series. The gates of the two transistors Q2 and Q3 constituting the second transfer transistor Tr2 are connected to each other. The gates of the three transistors Q4, Q5, Q6 constituting the third transfer transistor Tr3 are connected to each other. Further, the source of the first transfer transistor Tr1, the source of the transistor Q3 constituting the second transistor Tr2, and the source of the transistor Q6 constituting the third transfer transistor Tr3 are connected to each other. The source of the transistor Q2 constituting the second transfer transistor Tr2 and the source of the transistor Q5 constituting the third transfer transistor Tr3 are connected to each other.

  As can be seen from FIG. 3, in the configuration of the present embodiment, the red signal charge of the first photodiode PD1 is transferred to the first to third floating diffusions by the first to third transfer transistors Tr1 to Tr3. The green signal charge from the second photodiode PD2 is transferred to the FD1 to FD3 and transferred to the second and third floating diffusions FD2 and FD3 by the second and third transfer transistors Tr2 and Tr3. .

  Then, except for the gate electrode 33 of the first transfer transistor Tr1, signal charges due to photoelectric conversion of light of various colors are read together by the same transfer transistor, which causes color mixing.

  Hereinafter, in the solid-state imaging device according to this embodiment, a method for reading the signal charges accumulated in each of the first to third photodiodes PD1 to PD3 so as not to cause color mixing will be described.

First, light is irradiated from the back side of the solid-state imaging device, and signal charges are accumulated in the first to third photodiodes PD1 to PD3.
Next, the signal charge is read using the third transfer transistor Tr3. As described above, the gate electrode 42 of the third transfer transistor Tr3 is in contact with the first to third n-type semiconductor layers 27, 25, and 23 via the gate insulating film 34. For this reason, the signal charges accumulated in the first to third n-type semiconductor layers 27, 25, and 23 are transferred along the channel portion 44 formed under the gate electrode 42 of the third transfer transistor Tr3. Is read out to the n + source / drain region 45 of the third transfer transistor Tr3 to be the floating diffusion FD3. That is, all the signal charges accumulated in the first to third photodiodes PD1 to PD3 are read out by the gate electrode 42 of the third transfer transistor Tr3. The output potential due to the signal charge read to the n + source / drain region 45 of the third transfer transistor Tr3 is an output potential due to red, green, and blue light.
This output potential is V _RGB .

Next, light is irradiated again from the back side of the solid-state imaging device, and signal charges are accumulated in the first to third photodiodes PD1 to PD3.
Then, the signal charge is read using the second transfer transistor Tr2. As described above, the gate electrode 37 of the second transfer transistor Tr2 is in contact with the first and second n-type semiconductor layers 27 and 25 via the gate insulating film. Therefore, the signal charges accumulated in the first and second n-type semiconductor layers 27 and 25 are second floating along the channel portion 40 formed below the gate electrode 37 of the second transfer transistor Tr2. Data is read out to the n + source / drain region 41 of the second transfer transistor Tr2 to be the diffusion FD2. That is, the signal charges accumulated in the first and second photodiodes PD1 and PD2 are read out by the gate electrode 37 of the second transfer transistor Tr2. The output potential due to the signal charge read to the n + source / drain region 41 of the second transfer transistor Tr2 is an output potential due to red and green light.
This output potential is set to _VRG .

Next, light is irradiated again from the back side of the solid-state imaging device, and signal charges are accumulated in the first to third photodiodes PD1 to PD3.
Then, the signal charge is read using the first transfer transistor Tr1. The gate electrode 33 of the first transfer transistor Tr1 is in contact with only the first n-type semiconductor layer 27 through the gate insulating film 34. For this reason, the signal charge accumulated in the first n-type semiconductor layer 27 becomes the first floating diffusion FD1 along the channel portion 39 formed under the gate electrode 33 of the first transfer transformer Tr1. Data is read out to the n + source / drain region 46 of the first transfer transistor Tr1. The output potential due to the signal charge read to the n + source / drain region 46 of the first transfer transistor Tr1 is an output potential caused only by red light.
The output potential and _{V R.}

Then, three of the output potential _V RGB read by the above _procedure, V RG, than _{V R,} the output potential _V R corresponding to the respective _colors, V G, to calculate the _{V B.}
For example, the output potential V _B due to blue light is detected by the following arithmetic expression.
V _RGB -V _RG = V _B
Further, the output potential V _G due to green light is detected by the following arithmetic expression.
V _RG −V _R = V _G
On the other hand, the output potential V _R by the red light is detected output potential itself by using the first transfer transistor Tr1.

  The above calculation is performed by signal processing by an external circuit, and thus, color spectroscopy of three colors can be performed.

According to the present embodiment, the charge accumulated in the photodiode formed deep in the silicon substrate 21 by using the vertical transfer transistor in which the gate electrode is embedded to the depth of each of the plurality of photodiodes. Can be read efficiently without any remaining transfer. Thereby, an afterimage can be suppressed.
Further, by using a vertical transfer transistor in which the gate electrodes 33, 37, and 42 are embedded in the silicon substrate 21, the n-type semiconductor that becomes the charge storage region of each of the first to third photodiodes PD1 to PD3. It is not necessary to expose the layers 27, 25, and 23 on the surface of the silicon substrate 21. For this reason, it is possible to prevent noise on the surface of the silicon substrate 21 that occurs while signal charges are accumulated in the first to third photodiodes PD1 to PD3.

  Furthermore, according to the present embodiment, the first to third photodiodes PD1 to PD3 are configured by laminating a plurality of flat p-type semiconductor layers and n-type semiconductor layers, and each of the photodiodes. The pn junction depth is a certain depth position in the substrate. Thereby, the color mixture in each photodiode is suppressed.

  Further, by alternately laminating a flat p-type semiconductor layer and an n-type semiconductor layer, a plurality of photodiodes different in the depth direction are formed, and the PD1 to PD3 of the first to third photodiodes are further formed. The gate electrodes 33, 37, and 42 are embedded to their respective depths. Therefore, it is easy to design a structure in which a p-type semiconductor layer and an n-type semiconductor layer are further stacked to increase the number of photodiodes, and to design a corresponding embedded gate electrode. Therefore, in the present embodiment example, three photodiodes are configured in the unit pixel region 20, but the present invention is not limited to this, and four or more photodiodes may be configured.

  Further, in a plurality of photodiodes configured by laminating a flat p-type semiconductor layer and an n-type semiconductor layer, all the aperture ratios can be configured to be equal in the unit pixel region, and the aperture ratio of each photodiode is reduced. do not do. Therefore, in the unit pixel region, it is possible to perform spectroscopy without reducing the aperture ratio of the plurality of photodiodes.

  In the present embodiment, the back-illuminated type can increase the aperture ratio and improve the sensitivity.

  By the way, in the method of reading the signal charges sequentially from the third transfer transistor Tr3 having the gate electrode 42 having the longest gate length among the first to third transfer transistors Tr1 to Tr3 as in this embodiment. Every time the signal charge is read, a time for accumulating the signal charge is required.

[Second Embodiment]
Next, as a solid-state imaging device according to the second embodiment of the present invention, a solid-state imaging device capable of simultaneously reading the signal charges of the first to third photodiodes PD1 to PD3 and a reading method thereof will be described. The cross-sectional configuration in the unit pixel region 20 of the solid-state imaging device of this embodiment is the same as that of the first embodiment shown in FIG. In addition, the circuit configuration of the transfer transistor portion in the solid-state imaging device according to the present embodiment is also the same as that in FIG.
The present embodiment is an example of defining the positions where the gate electrodes 33, 37, and 42 are formed in the first to third transfer transistors Tr1 to Tr3 in the solid-state imaging device according to the first embodiment.

  In the present embodiment, for example, the signal charge amount accumulated in the third photodiode PD3 is read by 1/3 by the first to third transfer transistors Tr1 to Tr3. For that purpose, for example, the signal charge amount accumulated in the third photodiode PD3 is read out by 1/3 at the positions where the gate electrodes 33, 37, 42 of the first to third transfer transistors Tr1 to Tr3 are formed. Stipulate where you can.

  In addition, the signal charge amount accumulated in the second photodiode PD2 is read by 1/2 by the first and second transfer transistors Tr1 and Tr2. For this purpose, for example, the signal charge amount accumulated in the second photodiode PD2 is read out by 1/2 from the position where the gate electrodes 33 and 37 of the first and second transfer transistors Tr1 and Tr2 are formed. It is defined in a possible position.

In the solid-state imaging device according to this embodiment, signal charges are simultaneously read by the first to third transfer transistors Tr1 to Tr3.
The signal charge caused by the red light accumulated in the first photodiode PD1 is caused by the channel portions 39, 40, 44 of the first to third transfer transistors Tr1-Tr3 to be n + source / drain regions 46, 41, 45 is read by 1/3 at a time. That is, in the circuit diagram shown in FIG. 3, the red signal charges transferred from the first photodiode PD1 are transferred by 1/3 by the first to third transfer transistors Tr1 to Tr3, respectively. Further, the green signal charges transferred from the second photodiode PD2 are transferred by 1/2 by the second and third transfer transistors Tr2 and Tr3, respectively. In addition, all the blue signal charges transferred from the third photodiode PD3 are transferred by the third transfer transistor Tr3.
Based on the same principle, the signal charge caused by the green light accumulated in the second photodiode PD2 is caused by the n + source / drain region 46 by the channel portions 39, 40 of the first and second transfer transistors Tr1, Tr2. , 41 are read out by 1/2.
Further, the signal charge caused by the blue light accumulated in the third photodiode PD3 is read out to the n + source / drain region 45 only by the channel portion 44 of the third transfer transistor Tr3.

Here, E _R is the signal charge stored in the first photodiode PD1, E _G is the signal charge stored in the second photodiode PD2, and E _B is the signal charge stored in the third photodiode PD3. And
Then, the third transfer transistor Tr3, the signal charges are read out to the n + source and drain regions _45, indicated by the (1/3) E R + (1/2 ) E G + E B. Further, the second transfer transistor Tr2, the signal charges are read out to the n + source and drain regions _41, indicated by the (1/3) E R + (1/2 ) E G. Further, the first transfer transistor, the signal charge read out to the n + source and drain regions 46, indicated by the (1/3) _{E R.}

The signal charges read out in this way are calculated in an external circuit, and the respective signal charges E _R , E _G , and E _B are calculated, so that color spectroscopy of three colors can be performed.

In the present embodiment example, the position where the gate electrodes 33, 37, and 42 are formed in the first to third transfer transistors Tr1 to Tr3 is described as an example, but the present invention is not limited to this. The amount of charge that can be read out in each of the first to third transfer transistors Tr1 to Tr3 is checked in advance, and the signal charges E _R , E _G , and E _B are calculated in consideration of the value. Also good.

  In addition to the same effects as those of the first embodiment, this embodiment has the effect of simultaneously reading out signal charges of a plurality of photodiodes formed in the unit pixel region.

[Third Embodiment]
Next, FIG. 4A shows a cross-sectional configuration of the pixel portion of the solid-state imaging device according to the third embodiment of the present invention. FIG. 2 shows a cross-sectional configuration for one pixel, that is, in the unit pixel region 20. In FIG. 4, the same parts as those in FIG. The circuit diagram of the transfer transistor portion of the solid-state imaging device in this embodiment is the same as that in FIG.

  This embodiment is an example in which the mechanical shutter 50 is configured on the light incident side of the solid-state imaging device, that is, on the back side. Other configurations are the same as those of the first embodiment.

  The mechanical shutter 50 used in this embodiment is configured to be opened when light is incident and closed when light is not necessary.

  Hereinafter, a method of reading signal charges accumulated in the first to third photodiodes PD1 to PD3 in the solid-state imaging device according to the present embodiment will be described.

First, in a state where the mechanical shutter 50 is opened, light is incident on the first to third photodiodes PD1 to PD3 to accumulate signal charges by photoelectric conversion.
Next, the mechanical shutter 50 is closed to block external light from entering the first to third photodiodes PD1 to PD3. In this case, the first to third photodiodes PD1 to PD3 hold a state where signal charges are accumulated.

  Next, the signal charge accumulated in the first photodiode PD1 is read out to the n + source / drain region 46 by the first transfer transistor Tr1. Since the signal charge corresponding to the red light is accumulated in the first photodiode PD1, the signal charge read to the n + source / drain region 46 of the first transfer transistor Tr1 is a photoelectric conversion of the red light. Is due to.

Next, the signal charges accumulated in the second photodiode PD2 are read out to the n + source / drain region 41 by the second transfer transistor Tr2. Here, since the gate electrode 37 in the second transfer transistor Tr2 is in contact with the first n-type semiconductor layer 27 constituting the first photodiode PD1 via the gate insulating film 34, the second transfer transistor Tr2 The channel portion 40 of the transfer transistor Tr2 connects the first n-type semiconductor layer 27 and the n + source / drain region 41 of the second transfer transistor Tr2. However, the signal charges accumulated in the first photodiode PD1 (first n-type semiconductor layer 27) have already been read out in the previous stage. Therefore, only the signal charge accumulated in the second photodiode PD2 is read out to the n + source / drain region 41 of the second transfer transistor Tr2. That is, in the circuit diagram of FIG. 3, the signal transferred from the first photodiode PD1 to the second transfer transistor Tr2 is zero.
Since the signal charge corresponding to green light is accumulated in the second photodiode PD2, the signal charge read to the n + source / drain region 41 of the second transfer transistor Tr2 is photoelectrically converted to green light. Is due to.

  Next, the signal charge accumulated in the third photodiode PD3 is read out to the n + source / drain region 45 by the third transfer transistor Tr3. Here, the gate electrode 42 of the third transfer transistor Tr3 is connected to the first and second n-type semiconductor layers 27, 27 constituting the first and second photodiodes PD1, PD2 via the gate insulating film 34. 25 is in contact. Therefore, the first n-type semiconductor layer 27, the second n-type semiconductor layer 25, and the n + source / drain region 45 of the third transfer transistor Tr3 are formed by the channel portion 44 of the third transfer transistor Tr3. It will be connected. However, the signal charges accumulated in the first and second photodiodes PD1 and PD2 (first and second n-type semiconductor layers 27 and 25) in the previous stage have already been read out. Therefore, only the signal charge accumulated in the third photodiode PD3 is read out to the n + source / drain region 45 of the third transfer transistor Tr3. That is, in the circuit diagram of FIG. 3, the signal transferred from the first and second photodiodes PD1 and PD2 to the third transfer transistor Tr3 is zero. Since the signal charge corresponding to the blue light is accumulated in the third photodiode PD3, the signal charge read to the n + source / drain region 45 of the third transfer transistor Tr3 is the blue light. This is due to photoelectric conversion.

  In the present embodiment, the signal charges are read in order from the photodiode connected to the shallowly formed gate electrode, so that color spectroscopy of three colors of red, green, and blue can be performed. In the present embodiment, the external light is blocked by the mechanical shutter 50 when reading the signal charge. Thereby, for example, it is possible to prevent signal charges from being accumulated in other photodiodes while reading the signal charges of a certain photodiode.

  When the mechanical shutter 50 having the above configuration is actually used, as shown in FIG. 4B, the solid-state imaging device 1 in which the pixels 2 are formed in an array and the optical signal 70 are collected on the solid-state imaging device 1. It arrange | positions between the optical lens systems 71 for light-emitting. And it is set as the structure which controls the optical signal which injects into the whole imaging area | region of the solid-state imaging device 1. FIG.

In this embodiment, the same effect as that of the first embodiment can be obtained, and the signal charges of a plurality of photodiodes formed in the unit pixel region can be simultaneously read by using the mechanical shutter 50. Play.
In the present embodiment, the example using the mechanical shutter 40 has been shown. However, if the time required for reading out the charge is sufficiently shorter than the exposure time, the above-described effect can be obtained even when there is no mechanical shutter.

[Fourth Embodiment]
Next, FIG. 5 shows a cross-sectional configuration in a pixel portion of a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 5 shows a cross-sectional configuration for one pixel, that is, in the unit pixel region 20. In FIG. 5, the same parts as those in FIG.

  The solid-state imaging device according to the present embodiment is an example in which the configuration of the contact portion between the gate portion and the n-type semiconductor layer constituting the photodiode is partially modified in the solid-state imaging device according to the first embodiment.

As shown in FIG. 5, in the present embodiment, the gate electrode 37 constituting the second transfer transistor Tr2 is surrounded by the gate electrode 37 located at the depth of the first n-type semiconductor layer 27. A p-type semiconductor region 51 is formed. That is, the p-type semiconductor region 51 is formed in a portion of the first n-type semiconductor layer 27 that becomes the charge storage region of the first photodiode in contact with the gate portion of the second transfer transistor Tr2.
In addition, among the gate electrodes 42 constituting the third transfer transistor Tr3, the gate electrode 42 located at the depth of the first n-type semiconductor layer 27 and the second n-type semiconductor layer 25 has a p-type. A semiconductor region 52 is formed. That is, the portion of the first and second n-type semiconductor layers 27 and 25 that are to be the charge storage regions of the first and second photodiodes PD1 and PD2 is in contact with the gate portion of the third transfer transistor Tr3. A type semiconductor region 52 is formed.

  As described above, the n-type semiconductor in which the contact portions of the gate electrodes 37 and 42 constituting the second and third transfer transistors Tr2 and Tr3 with the photodiodes other than the photodiodes to be read are charge storage regions. Covered with a p-type semiconductor region having the opposite properties of the layer. Where the p-type semiconductor region is formed, the movement of the signal charges accumulated in the n-type semiconductor layer to the channel portion can be suppressed.

  FIG. 6 shows an equivalent circuit of unit pixels in the solid-state imaging device according to the present embodiment. In this embodiment, the signals accumulated in the first to third photodiodes PD1 to PD3 are formed by forming the p-type semiconductor layers 51 and 52 at required positions of the gate electrode 37 and the gate electrode 42, respectively. Charges can be transferred by independent circuits.

  Accordingly, in the second transfer transistor Tr2, only the signal charge accumulated in the second photodiode PD2 is read out. Similarly, also in the third transfer transistor Tr3, only the signal charge accumulated in the third photodiode PD3 is read out. Also, the gate electrode 33 constituting the first transfer transistor Tr1 is originally configured to be in contact with only the first photodiode PD1. Therefore, also in the first transfer transistor Tr1, only the signal charge accumulated in the first photodiode PD1 is read out.

  According to the present embodiment example, since the circuit for transferring the signal charge becomes independent, the signal charge for one color can be read out by one transfer transistor. Therefore, the signal charges accumulated in the first to third photodiodes PD1 to PD3 in the unit pixel region 20 can be read out simultaneously and separately.

  In this embodiment, the same effect as that of the first embodiment is obtained, and signal charges are read out by one transfer transistor for each photodiode. Therefore, the signal charges accumulated in each photodiode are used. They can be read simultaneously.

[Fifth Embodiment]
Next, FIG. 7 shows a cross-sectional configuration in a pixel portion of a solid-state imaging device according to the fifth embodiment of the present invention. FIG. 7 shows a cross-sectional configuration in one pixel, that is, in the unit pixel region 20. In FIG. 7, the same parts as those in FIG. The circuit configuration of the transfer transistor portion of the solid-state imaging device in this embodiment is the same as that in FIG.

  In the solid-state imaging device according to the present embodiment, the configurations of the n-type semiconductor layer and the p-type semiconductor layer that constitute the photodiode are modified in the solid-state imaging device according to the first embodiment.

  In the present embodiment example, as shown in FIG. 7, three photodiodes each composed of a flat p-type semiconductor layer and an n-type semiconductor layer are formed at different depths in the silicon substrate 21 in the unit pixel region 20. It is configured separately. Each of the photodiodes is stacked in order of a p-type semiconductor layer, an n-type semiconductor layer, and a p-type semiconductor layer from the surface side.

  In the present embodiment, a photodiode configured by stacking a p-type semiconductor layer 56, an n-type semiconductor layer 55, and a p-type semiconductor layer 54 located on the outermost surface side in the silicon substrate 21 is referred to as a first photodiode. It is assumed that the photodiode PD1. In addition, the photodiode formed by stacking the p-type semiconductor layer 59, the n-type semiconductor layer 58, and the p-type semiconductor layer 57 located in the middle in the silicon substrate 21 is referred to as a second photodiode PD2. Then, a photodiode configured by stacking the p-type semiconductor layer 62, the n-type semiconductor layer 62, and the p-type semiconductor layer 60 located on the rearmost surface side in the silicon substrate 21 is referred to as a third photodiode PD3. To do.

The pn junction j1 between the p-type semiconductor layer 56 and the n-type semiconductor layer 55 constituting the first photodiode PD1 is formed to a depth that absorbs red light when light is irradiated from the back side.
The pn junction j2 between the p-type semiconductor layer 59 and the n-type semiconductor layer 58 constituting the second photodiode PD2 is formed to a depth that absorbs green light when irradiated with light from the back surface side.
The pn junction j3 between the p-type semiconductor layer 62 and the n-type semiconductor layer 61 constituting the third photodiode PD3 is formed to a depth that absorbs blue light when irradiated with light from the back surface side.

Also in the present embodiment example, similarly to the first to fourth embodiments, the gate electrodes 33, 37, and 42 of the transfer transistors corresponding to the first to third photodiodes PD1 to PD3 described above are formed. The
First, the gate electrode 33 of the first transfer transistor Tr1 is formed to a depth reaching the pn junction j1 of the first photodiode PD1 from the surface side of the silicon substrate 21. The gate electrode 37 of the second transfer transistor Tr2 is formed to a depth reaching the pn junction j2 of the second photodiode PD2 from the surface side of the silicon substrate 21. The gate electrode 42 of the third transfer transistor Tr3 is formed to a depth reaching the pn junction j3 of the third photodiode PD3 from the surface side of the silicon substrate 21. Since the other configurations of the first to third transfer transistors Tr1 to Tr3 are the same as those of the first to fourth embodiments, a duplicate description is omitted.

  In the present embodiment, the signal charge accumulated in the first photodiode PD1 is read out by the first transfer transistor Tr1. The signal charge accumulated in the second photodiode PD2 is read by the second transfer transistor Tr2. Then, the signal charge accumulated in the third photodiode PD3 is read out by the third transfer transistor Tr3.

  According to the solid-state imaging device of the present embodiment example, the first to third photodiodes PD1 to PD3 are formed separately, and the gate electrodes 33, 37, 42 is configured to be in contact with only a desired photodiode through the gate insulating film 34. The fixed imaging apparatus having such a configuration has a circuit configuration as shown in FIG. As shown in FIG. 5, also in this embodiment, the signal charges accumulated in the first to third photodiodes PD1 to PD3 are transferred by independent circuits. Therefore, each of the first to third transfer transistors Tr1 to Tr3 can read only the signal charges due to light of one color. Thereby, color mixing can be prevented.

  The solid-state imaging device according to the first to fifth embodiments described above constitutes, for example, the solid-state imaging device 1 shown in FIG. The solid-state imaging device 1 shown in FIG. 1 has a configuration in which pixels are arranged in a two-dimensional array, but the configuration to which the solid-state imaging device according to the first to fifth embodiments described above can be applied is limited to this. is not. For example, it may be a solid-state imaging device having a structure in which pixels are linearly arranged.

  Moreover, although the above-mentioned embodiment showed the solid-state imaging device when applied to a CMOS image sensor, it can also be applied to a CCD image sensor. Furthermore, although the first to fifth solid-state imaging devices are exemplified by the backside illumination type configured so that light is incident from the side opposite to the wiring layer 47, the present invention is not limited to this. That is, a surface irradiation type solid-state imaging device in which light is irradiated from the same surface side as the wiring layer can be provided.

  In the case of the surface irradiation type solid-state imaging device, blue light is absorbed when the pn junction j1 depth is irradiated from the surface side in the solid-state imaging device in the first to fourth embodiments. The depth may correspond to the position of the target. Moreover, what is necessary is just to make it the depth corresponding to the position where green light is absorbed, when the pn junction j2 depth is irradiated from the surface side. Further, the depth of the pn junction j3 may be set to a depth corresponding to a position where red light is absorbed when light is irradiated from the surface side. The gate lengths of the gate electrodes 33, 37, and 42 of the first to third transfer transistors Tr1, Tr2, and Tr3 may be configured accordingly. That is, in the case of a surface irradiation type solid-state imaging device, the gate electrodes 33, 37, and 42 of the first to third transfer transistors Tr1 to Tr3 in FIG. 2 are respectively blue, green, and red photo diodes. It will correspond.

  The above example is a case where the present invention is applied to a solid-state imaging device in which signal charges are electrons. The present invention can also be applied to a solid-state imaging device when signal charges are holes. In this case, in the above-described embodiment, the semiconductor substrate and the semiconductor layer can be configured with the conductivity types reversed.

  The solid-state imaging device according to the above-described embodiment can be applied to electronic devices such as a camera, a mobile phone with a camera, and other devices having an imaging function.

  Next, FIG. 8 shows an embodiment of an electronic apparatus in which the solid-state imaging device of the first to fifth embodiments is used. In this embodiment, a camera is used as an example of an electronic device.

  As shown in FIG. 8, the electronic device 80 according to the present embodiment may be an electronic device 85 including a solid-state imaging device 82, an optical lens system 81, an input / output unit 84, and a signal processing device 83. Alternatively, the electronic device 86 may include a solid-state imaging device 82, an optical lens system 81, and an input / output unit 84. As the solid-state imaging device 82, the solid-state imaging device according to the first to fifth embodiments is used.

According to the electronic apparatus 80 of the present embodiment example, by providing the solid-state imaging devices of the first to fifth embodiments described above, mixed colors, false colors, afterimages, and noise are reduced, and an image with good color sensitivity is obtained. can get.
8 can be configured as a camera module or an imaging module having an imaging function. The present invention includes such a module, and can constitute an electronic device such as a mobile phone with a camera and other devices having an imaging function.

1 is a schematic configuration diagram of a solid-state imaging device according to an embodiment of the present invention. 1 is a schematic cross-sectional configuration diagram of a solid-state imaging device according to a first embodiment of the present invention. 2 is an equivalent circuit diagram of a unit pixel of the solid-state imaging device according to the first embodiment. FIG. FIGS. 4A and 4B are a schematic cross-sectional configuration diagram of a solid-state imaging device according to a third embodiment of the present invention, and a schematic configuration diagram illustrating the entire solid-state imaging device. It is a schematic sectional block diagram of the solid-state imaging device in the 4th Embodiment of this invention. It is an equivalent circuit diagram of the unit pixel of the solid-state imaging device in the fourth embodiment. It is a schematic sectional block diagram of the solid-state imaging device in the 5th Embodiment of this invention. It is a schematic block diagram of the electronic device in one embodiment of this invention. It is a schematic sectional block diagram of the photodiode used for the image pick-up element in a prior art example.

Explanation of symbols

  1 .... Solid-state imaging device 2 .... Pixel 3 .... Imaging area 4 .... Vertical drive circuit 5 .... Column signal processing circuit 6 .... Horizontal drive circuit 8 .... Control circuit 9 .... Vertical Signal line 10... Horizontal signal line 11 .. Substrate 20.. Unit pixel region 21... Silicon substrate 22... Fourth p-type semiconductor layer 23... Third n-type semiconductor layer 24..Third p-type semiconductor layer, 25..Second n-type semiconductor layer, 26..Second p-type semiconductor layer, 27..First n-type semiconductor layer, 28..First p-type semiconductor layer, 30 .. interlayer insulating film, 31 .. on-chip lens, 32 .. silicon oxide film, 33, 37, 42 .. gate electrode, 34 .. gate insulating film, 39, 40, 44. Channel portion, 46, 41, 45,... N + source / drain region, first photodiode, PD1, second Photodiode ·· PD2, the third photo diode ·· PD3,50 ·· mechanical shutter

Claims (10)

A plurality of photodiodes formed at different depths in the substrate in the unit pixel region;
A gate portion for reading signal charges photoelectrically converted by the plurality of photodiodes is formed in a depth direction from one surface side of the substrate so that a gate portion is formed at a depth corresponding to each of the plurality of photodiodes. A plurality of vertical transistors formed;
A solid-state imaging device comprising: The solid-state imaging device according to claim 1, wherein the plurality of photodiodes are formed by alternately laminating a plurality of first conductive semiconductor layers and second conductive semiconductor layers in the substrate.   3. The solid-state imaging device according to claim 2, wherein the stacked first conductive semiconductor layer and second conductive semiconductor layer are formed in a flat plate shape. 2. The solid-state imaging device according to claim 1, wherein a portion of the charge accumulation region of the photodiode other than a read target that is in contact with a gate portion of the vertical transistor is covered with a conductive semiconductor layer opposite to the charge accumulation region.   The solid-state imaging device according to claim 1, wherein light is incident on the photodiode from the other surface side facing the one surface side.   The solid-state imaging device according to claim 1, further comprising: a mechanical shutter that blocks light incident on the photodiode for a desired time on the other surface side on which the light is incident. A plurality of photodiodes formed at different depths in a substrate in the unit pixel region, and a gate portion for reading signal charges photoelectrically converted by the plurality of photodiodes are provided in each of the plurality of photodiodes. Forming a solid-state imaging device including a plurality of vertical transistors formed in a depth direction from one surface side of the substrate so as to be formed to a corresponding depth;
A step of reading out signal charges accumulated in a plurality of photodiodes formed at different depths by a plurality of vertical transistors formed at a depth corresponding to each of the photodiodes;
A method for driving a solid-state imaging device. In the step of reading out the signal charges, the signal charges accumulated in the plurality of photodiodes formed at the different depths are individually separated by a plurality of vertical transistors formed at the depths corresponding to the photodiodes. The method for driving a solid-state imaging device according to claim 7, wherein In the step of reading out the signal charges, the signal charges accumulated in the plurality of photodiodes formed at different depths are simultaneously processed by the plurality of vertical transistors formed at the depths corresponding to the photodiodes. The method for driving a solid-state imaging device according to claim 7, wherein the driving method is a reading step. An optical lens system;
In the substrate in the unit pixel region, a plurality of photodiodes formed at different depths, and a gate portion of a transistor for reading out signal charges photoelectrically converted by the plurality of photodiodes, the plurality of photodiodes A solid-state imaging device having a vertical transistor formed in a depth direction from one surface side of the substrate so as to have a depth corresponding to each, and a signal processing device for processing an output signal of the solid-state imaging device And electronic equipment.

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