JP2009283478A - Resin sealed semiconductor device, and method of manufacturing the same - Google Patents

Resin sealed semiconductor device, and method of manufacturing the same Download PDF

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JP2009283478A
JP2009283478A JP2008130776A JP2008130776A JP2009283478A JP 2009283478 A JP2009283478 A JP 2009283478A JP 2008130776 A JP2008130776 A JP 2008130776A JP 2008130776 A JP2008130776 A JP 2008130776A JP 2009283478 A JP2009283478 A JP 2009283478A
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lead
resin
die pad
mold resin
notch
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JP5125758B2 (en
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Hisashi Kawato
寿 川藤
Shinya Nakagawa
信也 中川
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resin sealed semiconductor device whose package is made compact while insulation of a suspension lead is secured, and to provided a method of manufacturing the same. <P>SOLUTION: Semiconductor chips 20 and 22 are mounted on die pads 10 and 12. A lead terminal 16 is disposed apart from the die pad 12. The semiconductor chip 22 and lead terminal 16 are connected by a wire 24. The suspension lead 18 is connected to the die pad 10. The die pads 10 and 12, the semiconductor chips 20 and 22, and a part of the lead terminal 16, the wire 24, and a part of the suspension lead 18 are sealed with mold resin 30. The lead terminal 16 projects outward from a side face of the mold resin 30. A cut 36 is formed on the side face of the mold resin 30. The cut 36 is narrower at an opening-side part 42 than at an inner part 44. The suspension lead 18 projects out of the mold resin 30 from the inner part of the cut 36. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、モールド樹脂の側面からリード端子と吊りリードが外部に突出した樹脂封止型半導体装置及びその製造方法に関するものである。   The present invention relates to a resin-encapsulated semiconductor device in which a lead terminal and a suspension lead protrude outside from a side surface of a mold resin, and a method for manufacturing the same.

隣接するリード端子と吊りリードの絶縁距離を確保するために、モールド樹脂の側面に切り欠きを形成し、この切り欠きに吊りリードを配置した樹脂封止型半導体装置が提案されている（例えば、特許文献１参照）。
特開２００３−１２４４３７号公報 In order to secure an insulation distance between the adjacent lead terminal and the suspension lead, a resin-encapsulated semiconductor device in which a notch is formed in the side surface of the mold resin and the suspension lead is disposed in the notch has been proposed (for example, Patent Document 1).
JP 2003-124437 A

しかし、吊りリードの絶縁性を確保するためには、切り欠きを深くしなければならず、パッケージを小型化することができなかった。   However, in order to ensure the insulation of the suspension leads, the notch has to be deepened, and the package cannot be reduced in size.

本発明は、上述のような課題を解決するためになされたもので、その目的は、吊りリードの絶縁性を確保しつつ、パッケージを小型化することができる樹脂封止型半導体装置及びその製造方法を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a resin-encapsulated semiconductor device capable of reducing the size of a package while ensuring the insulation of the suspension leads and the manufacture thereof. Get the method.

第１の発明は、ダイパッドと、ダイパッド上に搭載された半導体チップと、前記ダイパッドから離れて配置されたリード端子と、前記半導体チップと前記リード端子を接続するワイヤと、前記ダイパッドに接続された吊りリードと、前記ダイパッド、前記半導体チップ、前記リード端子の一部、前記ワイヤ、及び前記吊りリードの一部を封止するモールド樹脂とを備え、前記リード端子は、前記モールド樹脂の側面から外部に突出し、前記モールド樹脂の前記側面には、開口側の部分が奥側の部分よりも狭い切り欠きが形成され、前記吊りリードは、前記切り欠きの奥から前記モールド樹脂の外部に突出していることを特徴とする樹脂封止型半導体装置である。   1st invention is connected to the die pad, the semiconductor chip mounted on the die pad, the lead terminal arranged away from the die pad, the wire which connects the semiconductor chip and the lead terminal, and the die pad A suspension lead; and a die resin that seals the die pad, the semiconductor chip, a part of the lead terminal, the wire, and a part of the suspension lead, and the lead terminal is externally provided from a side surface of the mold resin. The side surface of the mold resin is formed with a notch whose opening side portion is narrower than the back side portion, and the suspension lead protrudes from the back of the notch to the outside of the mold resin. This is a resin-encapsulated semiconductor device.

第２の発明は、ダイパッドと、ダイパッド上に搭載された半導体チップと、前記ダイパッドから離れて配置されたリード端子と、前記半導体チップと前記リード端子を接続するワイヤと、前記ダイパッドに接続された吊りリードと、前記ダイパッド、前記半導体チップ、前記リード端子の一部、前記ワイヤ、及び前記吊りリードの一部を封止するモールド樹脂とを備え、前記リード端子は、前記モールド樹脂の側面から外部に突出し、前記モールド樹脂の前記側面には切り欠きが形成され、前記吊りリードは、前記切り欠きの奥から前記モールド樹脂の外部に突出し、前記吊りリードの前記モールド樹脂の外部に突出した部分は、ポッティング樹脂により覆われていることを特徴とする樹脂封止型半導体装置である。   2nd invention is connected to the die pad, the semiconductor chip mounted on the die pad, the lead terminal arranged away from the die pad, the wire connecting the semiconductor chip and the lead terminal, and the die pad A suspension lead; and a die resin that seals the die pad, the semiconductor chip, a part of the lead terminal, the wire, and a part of the suspension lead, and the lead terminal is externally provided from a side surface of the mold resin. A notch is formed in the side surface of the mold resin, the suspension lead projects from the back of the notch to the outside of the mold resin, and a portion of the suspension lead that projects to the outside of the mold resin is The resin-encapsulated semiconductor device is covered with potting resin.

第３の発明は、ダイパッドと、前記ダイパッドから離れて配置されたリード端子と、前記ダイパッドに接続された吊りリードとを有するリードフレームを形成する工程と、前記ダイパッド上に半導体チップを搭載し、前記半導体チップと前記リード端子をワイヤで接続する工程と、前記ダイパッド、前記半導体チップ、前記リード端子の一部、前記ワイヤ、及び前記吊りリードの一部をモールド金型のキャビティ内に入れ、モールド樹脂で封止する工程とを備え、前記リード端子を、前記モールド樹脂の側面から外部に突出させ、前記モールド樹脂の前記側面に、開口側の部分が奥側の部分よりも狭い切り欠きを形成し、前記吊りリードを、前記切り欠きの奥から前記モールド樹脂の外部に突出させ、前記吊りリードに、前記切り欠きの開口側の部分から外側に延びる溝を形成し、前記モールド樹脂で封止する工程において、前記溝を、前記キャビティから外部に空気を抜くエアベントとして用いることを特徴とする樹脂封止型半導体装置の製造方法である。   According to a third aspect of the present invention, there is provided a step of forming a lead frame having a die pad, a lead terminal disposed away from the die pad, and a suspension lead connected to the die pad, and mounting a semiconductor chip on the die pad. A step of connecting the semiconductor chip and the lead terminal with a wire; and placing the die pad, the semiconductor chip, a part of the lead terminal, the wire, and a part of the suspension lead into a cavity of a mold, A step of sealing with resin, and projecting the lead terminal to the outside from the side surface of the mold resin, and forming a notch in which the opening side portion is narrower than the back side portion on the side surface of the mold resin And projecting the suspension lead from the back of the notch to the outside of the mold resin, and opening the notch into the suspension lead. Forming a groove extending outward from the portion and sealing with the mold resin, wherein the groove is used as an air vent for extracting air from the cavity to the outside. It is.

本発明により、吊りリードの絶縁性を確保しつつ、パッケージを小型化することができる。   According to the present invention, the package can be reduced in size while ensuring the insulation of the suspension leads.

実施の形態１．
図１は、本発明の実施の形態１に係る樹脂封止型半導体装置を示す平面図であり、図２はその内部を示す平面図であり、図３は断面図である。 Embodiment 1 FIG.
1 is a plan view showing a resin-encapsulated semiconductor device according to Embodiment 1 of the present invention, FIG. 2 is a plan view showing the inside thereof, and FIG. 3 is a cross-sectional view.

ダイパッド１０，１２、出力リード１４、制御リード１６（リード端子）及び吊りリード１８を有するリードフレームは、大きな電流容量を確保するため、０．７ｍｍ厚のＣｕ材により形成されている。ダイパッド１０上に電力用チップ２０（半導体チップ）が搭載され、ダイパッド１２上に集積回路チップ２２（半導体チップ）が搭載されている。ダイパッド１０から離れて出力リード１４が配置され、ダイパッド１２から離れて制御リード１６が配置されている。電力用チップ２０と出力リード１４、集積回路チップ２２と制御リード１６は、それぞれワイヤ２４により接続されている。ダイパッド１０に吊りリード１８が接続されている。   The lead frame having the die pads 10 and 12, the output lead 14, the control lead 16 (lead terminal) and the suspension lead 18 is formed of a 0.7 mm thick Cu material in order to ensure a large current capacity. A power chip 20 (semiconductor chip) is mounted on the die pad 10, and an integrated circuit chip 22 (semiconductor chip) is mounted on the die pad 12. An output lead 14 is disposed away from the die pad 10 and a control lead 16 is disposed away from the die pad 12. The power chip 20 and the output lead 14, and the integrated circuit chip 22 and the control lead 16 are connected by wires 24, respectively. A suspension lead 18 is connected to the die pad 10.

ダイパッド１０はリードフレームの他の部分に比べて０．５ｍｍ沈められている。そして、電力用チップ２０の放熱性及び絶縁性を確保するために、ダイパッド１０の裏面に絶縁シート２６を介してＡｌ板２８が配置されている。   The die pad 10 is submerged by 0.5 mm as compared with other portions of the lead frame. In order to ensure heat dissipation and insulation of the power chip 20, an Al plate 28 is disposed on the back surface of the die pad 10 via an insulating sheet 26.

これらのダイパッド１０，１２、電力用チップ２０、集積回路チップ２２、出力リード１４の一部、制御リード１６の一部、ワイヤ２４、吊りリード１８の一部、絶縁シート２６、及びＡｌ板２８の表面と側面は、モールド樹脂３０により封止されている。出力リード１４は、モールド樹脂３０の側面３２から外部に突出している。制御リード１６は、モールド樹脂３０の側面３２とは反対側の側面３４から外部に突出している。さらに、モールド樹脂３０の側面３４には切り欠き３６が形成されている。   These die pads 10 and 12, power chip 20, integrated circuit chip 22, part of output lead 14, part of control lead 16, wire 24, part of suspension lead 18, insulating sheet 26, and Al plate 28 The surface and side surfaces are sealed with a mold resin 30. The output lead 14 protrudes from the side surface 32 of the mold resin 30 to the outside. The control lead 16 protrudes outside from a side surface 34 opposite to the side surface 32 of the mold resin 30. Further, a cutout 36 is formed in the side surface 34 of the mold resin 30.

図４は、本発明の実施の形態１に係る樹脂封止型半導体装置の切り欠きを拡大した平面図である。切り欠き３６は、切り欠き３６の奥に存在する底面３８と、切り欠き３６の奥と開口の間に存在し、互いに向かい合う２つの側面４０とを有する。切り欠き３６は、開口側の部分４２が奥側の部分４４よりも狭い。吊りリード１８は、切り欠き３６の奥から１ｍｍ程度の箇所がカットされ、モールド樹脂３０の外部に突出している。   FIG. 4 is an enlarged plan view of the notch of the resin-encapsulated semiconductor device according to the first embodiment of the present invention. The notch 36 has a bottom surface 38 that exists in the back of the notch 36, and two side surfaces 40 that exist between the back of the notch 36 and the opening and face each other. In the notch 36, the opening-side portion 42 is narrower than the back-side portion 44. The suspension lead 18 is cut about 1 mm from the back of the notch 36 and protrudes outside the mold resin 30.

本実施の形態に係る樹脂封止型半導体装置の製造方法について説明する。まず、図５に示すように、ダイパッド１０，１２、出力リード１４、制御リード１６、及び吊りリード１８を有するリードフレームを形成する。そして、ダイパッド１０上に電力用チップ２０を搭載し、ダイパッド１２上に集積回路チップ２２を搭載する。さらに、電力用チップ２０と出力リード１４、集積回路チップ２２と制御リード１６を、それぞれワイヤ２４により接続する。その後、ダイパッド１０の裏面に絶縁シート２６を介してＡｌ板２８を配置する。   A method for manufacturing the resin-encapsulated semiconductor device according to the present embodiment will be described. First, as shown in FIG. 5, a lead frame having die pads 10 and 12, output leads 14, control leads 16, and suspension leads 18 is formed. Then, the power chip 20 is mounted on the die pad 10 and the integrated circuit chip 22 is mounted on the die pad 12. Further, the power chip 20 and the output lead 14, and the integrated circuit chip 22 and the control lead 16 are connected by wires 24. Thereafter, an Al plate 28 is disposed on the back surface of the die pad 10 via an insulating sheet 26.

次に、図６に示すように、ダイパッド１０，１２、電力用チップ２０、集積回路チップ２２、出力リード１４の一部、制御リード１６の一部、ワイヤ２４、吊りリード１８の一部、絶縁シート２６、及びＡｌ板２８をモールド金型４６のキャビティ４８内に入れ、モールド樹脂３０で封止する。この際に、制御リード１６を、モールド樹脂３０の側面から外部に突出させる。また、モールド樹脂３０の側面に、開口側の部分４２が奥側の部分４４よりも狭い切り欠き３６を形成する。そして、吊りリード１８を、切り欠き３６の奥からモールド樹脂３０の外部に突出させる。   Next, as shown in FIG. 6, die pads 10 and 12, power chip 20, integrated circuit chip 22, part of output lead 14, part of control lead 16, wire 24, part of suspension lead 18, insulation The sheet 26 and the Al plate 28 are placed in the cavity 48 of the mold 46 and sealed with the mold resin 30. At this time, the control lead 16 is projected from the side surface of the mold resin 30 to the outside. Further, a notch 36 in which the opening-side portion 42 is narrower than the back-side portion 44 is formed on the side surface of the mold resin 30. Then, the suspension lead 18 is projected from the back of the notch 36 to the outside of the mold resin 30.

また、図７に示すように、吊りリード１８に、切り欠き３６の開口側の部分４２から外側に延びる溝５０を形成しておく。そして、モールド樹脂３０で封止する工程において、溝５０を、キャビティ４８から外部に空気を抜くエアベントとして用いる。   Further, as shown in FIG. 7, a groove 50 extending outward from the opening-side portion 42 of the notch 36 is formed in the suspension lead 18. In the step of sealing with the mold resin 30, the groove 50 is used as an air vent that vents air from the cavity 48 to the outside.

次に、図８に示すように、モールド樹脂３０から突出した出力リード１４、制御リード１６及び吊りリード１８のカットを行う。その後、出力リード１４や制御リード１６の曲げ工程などを経て、本実施の形態に係る樹脂封止型半導体装置が製造される。   Next, as shown in FIG. 8, the output lead 14, the control lead 16, and the suspension lead 18 protruding from the mold resin 30 are cut. Thereafter, the resin-encapsulated semiconductor device according to the present embodiment is manufactured through a bending process of the output lead 14 and the control lead 16.

上記のように切り欠き３６の開口側の部分４２を奥側の部分４４よりも狭くすることにより、切り欠き３６を深くしなくても、隣接する制御リード１６と吊りリード１８の沿面距離を長くすることができる。よって、吊りリード１８の絶縁性を確保しつつ、パッケージを小型化することができる。   By making the opening-side portion 42 of the notch 36 narrower than the back-side portion 44 as described above, the creepage distance between the adjacent control lead 16 and the suspension lead 18 can be increased without deepening the notch 36. can do. Therefore, the package can be reduced in size while ensuring the insulation of the suspension leads 18.

また、切り欠き３６の開口側の部分４２は、樹脂封止の際に最終充填箇所となるため、空気溜まりができて未充填となりやすい。そこで、吊りリード１８に切り欠き３６の開口側の部分４２から外側に延びる溝５０を形成し、樹脂封止の際に溝５０をキャビティ４８から外部に空気を抜くエアベントとして用いることにより、未充填の問題を解消することができる。   Further, since the opening 42 of the notch 36 becomes a final filling portion when the resin is sealed, an air pocket is easily formed and the portion is not easily filled. Accordingly, a groove 50 extending outward from the opening 42 of the notch 36 is formed in the suspension lead 18, and the groove 50 is used as an air vent for extracting air from the cavity 48 to the outside during resin sealing. The problem can be solved.

実施の形態２．
図９は、本発明の実施の形態２に係る樹脂封止型半導体装置を示す平面図であり、図１０はその切り欠きを拡大した平面図である。 Embodiment 2. FIG.
FIG. 9 is a plan view showing a resin-encapsulated semiconductor device according to the second embodiment of the present invention, and FIG. 10 is an enlarged plan view of the notch.

切り欠き３６の形状は、実施の形態１とは異なり、開口側の部分も奥側の部分も同じ幅である。吊りリード１８のモールド樹脂３０の外部に突出した部分は、ポッティング樹脂５２により覆われている。その他の構成は実施の形態１と同様である。   The shape of the notch 36 is different from that of the first embodiment, and the opening-side portion and the back-side portion have the same width. A portion of the suspension lead 18 protruding outside the mold resin 30 is covered with a potting resin 52. Other configurations are the same as those of the first embodiment.

このように吊りリード１８のモールド樹脂３０の外部に突出した部分をポッティング樹脂５２で覆うことで、切り欠き３６を深くしなくても、隣接する制御リード１６に対して吊りリード１８を確実に絶縁することができる。よって、吊りリード１８の絶縁性を確保しつつ、パッケージを小型化することができる。   Thus, by covering the portion of the suspension lead 18 that protrudes outside the mold resin 30 with the potting resin 52, the suspension lead 18 is reliably insulated from the adjacent control lead 16 without deepening the notch 36. can do. Therefore, the package can be reduced in size while ensuring the insulation of the suspension leads 18.

実施の形態３．
図１１は、本発明の実施の形態３に係る樹脂封止型半導体装置を示す平面図であり、図１２はその切り欠きを拡大した平面図である。 Embodiment 3 FIG.
FIG. 11 is a plan view showing a resin-encapsulated semiconductor device according to Embodiment 3 of the present invention, and FIG. 12 is an enlarged plan view of the notch.

切り欠き３６の２つの側面４０及び底面３８には、吊りリード１８の近傍において凸部５４が形成されている。その他の構成は実施の形態２と同様である。このように凸部５４を形成したことで、凸部５４に付着したポッティング樹脂５２の表面張力により、ポッティング樹脂５２の樹脂ダレを防ぎ、ポッティング樹脂５２がモールド樹脂３０の外形からはみ出すのを防ぐことができる。   Convex portions 54 are formed on the two side surfaces 40 and the bottom surface 38 of the notch 36 in the vicinity of the suspension lead 18. Other configurations are the same as those of the second embodiment. By forming the convex portion 54 in this manner, the surface tension of the potting resin 52 attached to the convex portion 54 prevents the potting resin 52 from sagging and prevents the potting resin 52 from protruding from the outer shape of the mold resin 30. Can do.

図１３は、本発明の実施の形態３に係る樹脂封止型半導体装置の切り欠きを拡大した斜視図であり、図１４はその平面図、図１５は図１４のＡ−Ａ´における断面図、図１６は図１４のＢ−Ｂ´における断面図である。ただし、説明の簡略化のために図１３〜図１５においてポッティング樹脂５２は省略している。   13 is an enlarged perspective view of a cutout of the resin-encapsulated semiconductor device according to the third embodiment of the present invention, FIG. 14 is a plan view thereof, and FIG. 15 is a cross-sectional view taken along line AA ′ of FIG. 16 is a cross-sectional view taken along the line BB ′ of FIG. However, for simplification of description, the potting resin 52 is omitted in FIGS.

切り欠き３６の奥から開口に向かう方向において、２つの側面４０に形成された凸部５４の長さｔ１は、吊りリード１８のモールド樹脂３０の外部に突出した部分の長さｔ２よりも長い。これにより、吊りリード１８を確実にポッティング樹脂５２で覆うことができる。   In the direction from the back of the cutout 36 toward the opening, the length t1 of the convex portion 54 formed on the two side surfaces 40 is longer than the length t2 of the portion of the suspension lead 18 that protrudes outside the mold resin 30. Thereby, the suspension lead 18 can be reliably covered with the potting resin 52.

また、吊りリード１８と凸部５４の下辺との幅ｗ１と吊りリード１８と凸部５４の上辺との幅ｗ２は同じである。即ち、吊りリード１８は、モールド樹脂３０の厚み方向において凸部５４の中央に位置する。これにより、吊りリード１８がポッティング樹脂５２の中央にくるため、ポッティング樹脂５２からの吊りリード１８のはみ出しを減らし、吊りリード１８を更に確実に絶縁することができる。   Further, the width w1 between the suspension lead 18 and the lower side of the projection 54 and the width w2 between the suspension lead 18 and the upper side of the projection 54 are the same. That is, the suspension lead 18 is located at the center of the convex portion 54 in the thickness direction of the mold resin 30. Thereby, since the suspension lead 18 comes to the center of the potting resin 52, the protrusion of the suspension lead 18 from the potting resin 52 can be reduced, and the suspension lead 18 can be further reliably insulated.

本発明の実施の形態１に係る樹脂封止型半導体装置を示す平面図である。1 is a plan view showing a resin-encapsulated semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１に係る樹脂封止型半導体装置の内部を示す平面図である。It is a top view which shows the inside of the resin-sealed semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る樹脂封止型半導体装置の断面図である。1 is a cross-sectional view of a resin-encapsulated semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１に係る樹脂封止型半導体装置の切り欠きを拡大した平面図である。It is the top view which expanded the notch of the resin-sealed semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る樹脂封止型半導体装置の製造方法を説明するための平面図である。It is a top view for demonstrating the manufacturing method of the resin sealing type semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る樹脂封止型半導体装置の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the resin sealing type semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る樹脂封止型半導体装置の製造方法を説明するための拡大平面図である。It is an enlarged plan view for demonstrating the manufacturing method of the resin sealing type | mold semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る樹脂封止型半導体装置の製造方法を説明するための平面図である。It is a top view for demonstrating the manufacturing method of the resin sealing type semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る樹脂封止型半導体装置を示す平面図である。It is a top view which shows the resin-encapsulated semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る樹脂封止型半導体装置の切り欠きを拡大した平面図である。It is the top view which expanded the notch of the resin sealing type semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る樹脂封止型半導体装置を示す平面図である。It is a top view which shows the resin-encapsulated semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る樹脂封止型半導体装置の切り欠きを拡大した平面図である。It is the top view which expanded the notch of the resin sealing type semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る樹脂封止型半導体装置の切り欠きを拡大した斜視図である。It is the perspective view which expanded the notch of the resin sealing type semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る樹脂封止型半導体装置の切り欠きを拡大した平面図である。It is the top view which expanded the notch of the resin sealing type semiconductor device which concerns on Embodiment 3 of this invention. 図１４のＡ−Ａ´における断面図である。It is sectional drawing in AA 'of FIG. 図１４のＢ−Ｂ´における断面図である。It is sectional drawing in BB 'of FIG.

符号の説明Explanation of symbols

１０，１２ ダイパッド
１６ 制御リード（リード端子）
１８ 吊りリード
２０ 電力用チップ（半導体チップ）
２２ 集積回路チップ（半導体チップ）
２４ ワイヤ
３０ モールド樹脂
３４ モールド樹脂の側面
３６ 切り欠き
３８ 切り欠きの底面
４０ 切り欠きの側面
４２ 切り欠きの開口側の部分
４４ 切り欠きの奥側の部分
４６ モールド金型
４８ キャビティ
５０ 溝
５２ ポッティング樹脂
５４ 凸部 10, 12 Die pad 16 Control lead (lead terminal)
18 Suspended lead 20 Power chip (semiconductor chip)
22 Integrated circuit chip (semiconductor chip)
24 Wire 30 Mold resin 34 Mold resin side surface 36 Notch 38 Notch bottom surface 40 Notch side surface 42 Notch opening side portion 44 Notch deep side portion 46 Mold die 48 Cavity 50 Groove 52 Potting resin 54 Convex

Claims (6)

ダイパッドと、
ダイパッド上に搭載された半導体チップと、
前記ダイパッドから離れて配置されたリード端子と、
前記半導体チップと前記リード端子を接続するワイヤと、
前記ダイパッドに接続された吊りリードと、
前記ダイパッド、前記半導体チップ、前記リード端子の一部、前記ワイヤ、及び前記吊りリードの一部を封止するモールド樹脂とを備え、
前記リード端子は、前記モールド樹脂の側面から外部に突出し、
前記モールド樹脂の前記側面には、開口側の部分が奥側の部分よりも狭い切り欠きが形成され、
前記吊りリードは、前記切り欠きの奥から前記モールド樹脂の外部に突出していることを特徴とする樹脂封止型半導体装置。 Die pad,
A semiconductor chip mounted on a die pad;
A lead terminal disposed away from the die pad;
A wire connecting the semiconductor chip and the lead terminal;
Suspension leads connected to the die pad;
A mold resin for sealing the die pad, the semiconductor chip, a part of the lead terminal, the wire, and a part of the suspension lead;
The lead terminal protrudes outside from the side surface of the mold resin,
On the side surface of the mold resin, a cutout is formed in which the opening side portion is narrower than the back side portion,
The resin-encapsulated semiconductor device, wherein the suspension lead protrudes from the back of the notch to the outside of the mold resin. ダイパッドと、
ダイパッド上に搭載された半導体チップと、
前記ダイパッドから離れて配置されたリード端子と、
前記半導体チップと前記リード端子を接続するワイヤと、
前記ダイパッドに接続された吊りリードと、
前記ダイパッド、前記半導体チップ、前記リード端子の一部、前記ワイヤ、及び前記吊りリードの一部を封止するモールド樹脂とを備え、
前記リード端子は、前記モールド樹脂の側面から外部に突出し、
前記モールド樹脂の前記側面には切り欠きが形成され、
前記吊りリードは、前記切り欠きの奥から前記モールド樹脂の外部に突出し、
前記吊りリードの前記モールド樹脂の外部に突出した部分は、ポッティング樹脂により覆われていることを特徴とする樹脂封止型半導体装置。 Die pad,
A semiconductor chip mounted on a die pad;
A lead terminal disposed away from the die pad;
A wire connecting the semiconductor chip and the lead terminal;
Suspension leads connected to the die pad;
A mold resin for sealing the die pad, the semiconductor chip, a part of the lead terminal, the wire, and a part of the suspension lead;
The lead terminal protrudes outside from the side surface of the mold resin,
Notches are formed on the side surfaces of the mold resin,
The suspension lead protrudes from the back of the notch to the outside of the mold resin,
A resin-encapsulated semiconductor device, wherein a portion of the suspension lead that protrudes outside the mold resin is covered with a potting resin. 前記切り欠きは、前記切り欠きの奥に存在する底面と、前記切り欠きの前記奥と開口の間に存在し、互いに向かい合う２つの側面とを有し、
前記切り欠きの前記２つの側面及び前記底面には、前記吊りリードの近傍において凸部が形成されていることを特徴とする請求項２に記載の樹脂封止型半導体装置。 The notch has a bottom surface existing in the back of the notch, and two side surfaces existing between the back of the notch and the opening and facing each other,
3. The resin-encapsulated semiconductor device according to claim 2, wherein a convex portion is formed in the vicinity of the suspension lead on the two side surfaces and the bottom surface of the notch. 前記２つの側面に形成された前記凸部は、前記切り欠きの前記奥から前記開口に向かう方向において、前記吊りリードの前記モールド樹脂の外部に突出した部分よりも長いことを特徴とする請求項３に記載の樹脂封止型半導体装置。   The convex portion formed on the two side surfaces is longer than a portion of the suspension lead that protrudes outside the mold resin in a direction from the back of the notch toward the opening. 3. A resin-encapsulated semiconductor device according to 3. 前記吊りリードは、前記モールド樹脂の厚み方向において前記凸部の中央に位置することを特徴とする請求項３に記載の樹脂封止型半導体装置。   The resin-encapsulated semiconductor device according to claim 3, wherein the suspension lead is positioned at a center of the convex portion in a thickness direction of the mold resin. ダイパッドと、前記ダイパッドから離れて配置されたリード端子と、前記ダイパッドに接続された吊りリードとを有するリードフレームを形成する工程と、
前記ダイパッド上に半導体チップを搭載し、前記半導体チップと前記リード端子をワイヤで接続する工程と、
前記ダイパッド、前記半導体チップ、前記リード端子の一部、前記ワイヤ、及び前記吊りリードの一部をモールド金型のキャビティ内に入れ、モールド樹脂で封止する工程とを備え、
前記リード端子を、前記モールド樹脂の側面から外部に突出させ、
前記モールド樹脂の前記側面に、開口側の部分が奥側の部分よりも狭い切り欠きを形成し、
前記吊りリードを、前記切り欠きの奥から前記モールド樹脂の外部に突出させ、
前記吊りリードに、前記切り欠きの開口側の部分から外側に延びる溝を形成し、
前記モールド樹脂で封止する工程において、前記溝を、前記キャビティから外部に空気を抜くエアベントとして用いることを特徴とする樹脂封止型半導体装置の製造方法。 Forming a lead frame having a die pad, a lead terminal disposed away from the die pad, and a suspension lead connected to the die pad;
Mounting a semiconductor chip on the die pad, and connecting the semiconductor chip and the lead terminal with a wire;
A step of placing the die pad, the semiconductor chip, a part of the lead terminal, the wire, and a part of the suspension lead in a cavity of a mold, and sealing with a mold resin,
The lead terminal protrudes outside from the side surface of the mold resin,
On the side surface of the mold resin, the opening side portion is formed with a notch narrower than the back side portion,
The suspension lead protrudes from the back of the notch to the outside of the mold resin,
Forming a groove extending outward from the opening side portion of the notch in the suspension lead;
In the step of sealing with the mold resin, the groove is used as an air vent for extracting air from the cavity to the outside.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150097278A1 (en) * 2013-10-09 2015-04-09 Freescale Semiconductor, Inc. Surface mount semiconductor device with additional bottom face contacts
CN104681546A (en) * 2013-12-02 2015-06-03 三菱电机株式会社 Power module and method for manufacturing the same
US9064851B2 (en) 2013-02-27 2015-06-23 Denso Corporation Semiconductor device
JP2021034657A (en) * 2019-08-28 2021-03-01 富士電機株式会社 Semiconductor device and method of manufacturing semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0312954A (en) * 1989-06-12 1991-01-21 Nec Corp Resin sealed semiconductor device
JP2000012756A (en) * 1998-06-23 2000-01-14 Hitachi Ltd Semiconductor device and its manufacturing method, and mounting structure using the device
JP2001196532A (en) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp Semiconductor device
JP2001332687A (en) * 2000-05-23 2001-11-30 Hitachi Ltd Semiconductor device and manufacturing method thereof
JP2003124437A (en) * 2001-10-19 2003-04-25 Mitsubishi Electric Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0312954A (en) * 1989-06-12 1991-01-21 Nec Corp Resin sealed semiconductor device
JP2000012756A (en) * 1998-06-23 2000-01-14 Hitachi Ltd Semiconductor device and its manufacturing method, and mounting structure using the device
JP2001196532A (en) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp Semiconductor device
JP2001332687A (en) * 2000-05-23 2001-11-30 Hitachi Ltd Semiconductor device and manufacturing method thereof
JP2003124437A (en) * 2001-10-19 2003-04-25 Mitsubishi Electric Corp Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064851B2 (en) 2013-02-27 2015-06-23 Denso Corporation Semiconductor device
US20150097278A1 (en) * 2013-10-09 2015-04-09 Freescale Semiconductor, Inc. Surface mount semiconductor device with additional bottom face contacts
CN104681546A (en) * 2013-12-02 2015-06-03 三菱电机株式会社 Power module and method for manufacturing the same
JP2015106685A (en) * 2013-12-02 2015-06-08 三菱電機株式会社 Power module and method of manufacturing the same
US9716058B2 (en) 2013-12-02 2017-07-25 Mitsubishi Electric Corporation Power module and control integrated circuit
US10332869B2 (en) 2013-12-02 2019-06-25 Mitsubishi Electric Corporation Method for manufacturing power module
JP2021034657A (en) * 2019-08-28 2021-03-01 富士電機株式会社 Semiconductor device and method of manufacturing semiconductor device
JP7459465B2 (en) 2019-08-28 2024-04-02 富士電機株式会社 Semiconductor device and semiconductor device manufacturing method

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