JP2009277926A - Semiconductor light-emitting device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress stress generated between a semiconductor substrate and a compound semiconductor layer stacked thereupon. <P>SOLUTION: A semiconductor light-emitting device comprises: the semiconductor substrate 11; the compound semiconductor layer 12 formed on a first surface S1 of the semiconductor substrate 11; a ridge-shaped first stripe portion 14 formed on the compound semiconductor layer 12; resonance surfaces 21 and 22, formed opposite in a sectional direction perpendicular in the length direction of the first stripe portion 14; a ridge-shaped second stripe portion 16 formed on the side of a second surface S2 of the semiconductor substrate 11 on the opposite side from the first surface S1, at a position opposed to the first stripe portion 14; and second groove portions 15, formed on the side of the second surface S2 of the semiconductor substrate 11 on both sides of the second stripe portion 16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device and a manufacturing method thereof.

Nitride semiconductor laser elements are used as light sources for optical disks such as DVDs, and high output and high reliability are problems. A nitride semiconductor laser device is manufactured, for example, by stacking a plurality of nitride semiconductor layers on a gallium nitride (GaN) substrate selectively grown for a sapphire substrate, removing the sapphire substrate, and forming a resonant surface by cleavage. (For example, see Non-Patent Document 1.)
However, it has been very difficult to produce a good cleavage plane with good reproducibility. There was a problem that the ridge-shaped stripes were chipped by the impact of cleavage and the reliability was affected.
In addition, even when a good cleavage plane can be produced with good reproducibility, a gap occurs between the layers of the gallium nitride substrate and the nitride semiconductor layer stacked thereon, and stress is generated. Deterioration of the characteristics of the laser element due to the occurrence of a layer shift due to stress has been a problem.

  In addition, a nitride semiconductor substrate is used as a conventional semiconductor laser device, and a first main surface of the nitride semiconductor substrate includes a first region in which a crystal growth surface is a (0001) plane and a first region. And a second region having a different crystal plane. A recess groove is formed in the second region of the second main surface of the nitride semiconductor substrate, and a ridge-shaped stripe is formed on the upper portion of the first main surface of the nitride semiconductor substrate. (For example, refer to Patent Document 1).

JP 2005-159278 A Jpn.J.Appl.Phys.Vol.37 (1998) pp.L309-L312, Part2, No.3B, 15 March1998

  The problem to be solved is that stress generated between the semiconductor substrate, for example, a gallium nitride substrate and the compound semiconductor layer laminated thereon, for example, the nitride semiconductor layer cannot be suppressed.

  The present invention makes it possible to suppress stress generated between the semiconductor substrate and the compound semiconductor layer laminated thereon.

  The semiconductor light-emitting device (first semiconductor light-emitting device) of the present invention includes a semiconductor substrate, a compound semiconductor layer formed on the first surface of the semiconductor substrate, and a ridge-shaped first formed on the top of the compound semiconductor layer. A stripe portion, a resonant surface formed in a cross-sectional direction perpendicular to the length direction of the first stripe portion and formed opposite to each other, and a second surface opposite to the first surface of the semiconductor substrate A ridge-shaped second stripe portion formed at a position facing the first stripe portion on the surface side; and a groove portion formed on both sides of the second stripe portion on the second surface side of the semiconductor substrate.

  In the first semiconductor light-emitting device of the present invention, a ridge-shaped second stripe portion formed at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate, and the semiconductor substrate Since the groove portion formed on both sides of the second stripe portion on the second surface side, the stress generated between the semiconductor substrate and the compound semiconductor layer is relieved, and the stress between the first stripe portion and the second stripe portion is reduced. Is alleviated. Thereby, the stress at the resonance surface is relaxed.

  The semiconductor light-emitting device (second semiconductor light-emitting device) of the present invention includes a semiconductor substrate, a compound semiconductor layer formed on the first surface of the semiconductor substrate, and a ridge-shaped first formed on the top of the compound semiconductor layer. A stripe portion, a resonant surface formed in a cross-sectional direction perpendicular to the length direction of the first stripe portion and formed opposite to each other, and a second surface opposite to the first surface of the semiconductor substrate A groove portion formed at a position facing the first stripe portion on the surface side or a ridge-shaped second stripe portion is provided.

  The second semiconductor light emitting device of the present invention has a groove formed at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate, or a ridge-shaped second stripe portion. Therefore, the stress generated between the semiconductor substrate and the compound semiconductor layer is relieved, and the stress between the first stripe portion and the second stripe portion or the groove portion is relieved. Thereby, the stress at the resonance surface is relaxed.

  According to a first method of manufacturing a semiconductor light emitting device of the present invention, a step of forming a compound semiconductor layer having a ridge-shaped first stripe portion on a first surface of a semiconductor substrate, and a side opposite to the first surface of the semiconductor substrate. A ridge-shaped second stripe portion and a step of forming a groove on both sides of the second stripe portion at a position facing the first stripe portion on the second surface side.

  In the first method for manufacturing a semiconductor light emitting device of the present invention, the second stripe portion having the ridge shape and the second stripe portion are disposed at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate. Since the groove portions are formed on both sides of the stripe portion, the stress generated between the semiconductor substrate and the compound semiconductor layer is relieved, and the stress between the first stripe portion and the second stripe portion is relieved. Thereby, the stress at the resonance surface is relaxed.

  According to a second method of manufacturing a semiconductor light emitting device of the present invention, a step of forming a compound semiconductor layer having a ridge-shaped first stripe portion on a first surface of a semiconductor substrate, and a side opposite to the first surface of the semiconductor substrate. Forming a ridge-shaped second stripe portion or groove portion at a position facing the first stripe portion on the second surface side.

  In the second method for manufacturing a semiconductor light emitting device according to the present invention, a ridge-shaped second stripe portion or groove portion is formed at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate. Therefore, the stress generated between the semiconductor substrate and the compound semiconductor layer is relieved, and the stress between the first stripe portion and the second stripe portion or the groove portion is relieved. Thereby, the stress at the resonance surface is relaxed.

  In each semiconductor light emitting device of the present invention, the stress generated between the semiconductor substrate and the compound semiconductor layer is relaxed, and the warpage of the semiconductor substrate is reduced. As a result, the stress on the resonance surface is relieved and the life of the semiconductor light emitting device is extended. Therefore, there is an advantage that the life characteristics can be improved, and the reliability of the semiconductor light emitting device can be improved.

  In each method for manufacturing a semiconductor light emitting device of the present invention, the stress generated between the semiconductor substrate and the compound semiconductor layer is relaxed, and the warpage of the semiconductor substrate is reduced. As a result, the stress on the resonance surface is relieved, so that there is an advantage that a semiconductor light emitting device having a long lifetime can be manufactured, and the reliability of the semiconductor light emitting device can be improved.

  An embodiment (first embodiment) according to a semiconductor light emitting device of the present invention will be described with reference to a schematic perspective view of FIG. 1A and a schematic cross-sectional view of FIG. FIG. 1 shows an example of a first semiconductor light emitting device corresponding to claims 1 and 2.

  As shown in FIG. 1, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11, and an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

  A compound semiconductor layer 12 is formed on the first surface S1 of the semiconductor substrate 11. For example, two first groove portions 13 are formed on the top of the compound semiconductor layer 12, and a ridge-shaped first stripe portion 14 is formed between the first groove portions 13 with the compound semiconductor layer 12. That is, the first groove portion 13 is formed on both sides of the first stripe portion 14.

On the other hand, on the second surface S2 opposite to the first surface S1 of the semiconductor substrate 11, for example, two second parallel surfaces to the first stripe portion 14 at a position facing the first stripe portion 14. Two groove portions 15 are formed. A second stripe portion 16 is formed in the semiconductor substrate 10 between the second groove portions 15. That is, the second groove portion 15 is formed on both sides of the second stripe portion 16.
Further, in the semiconductor light emitting device 1 having the above configuration, the resonance surfaces 21 and 22 are formed in the cross-sectional direction perpendicular to the length direction of the first stripe portion 14 and facing each other. The resonance surface 22 is hidden behind the semiconductor light emitting device 1 in the drawing and is not shown directly.
The resonance surface 21 is formed on the same surface as the end surface 23 of the semiconductor light emitting device 1, and the resonance surface 22 is formed on the same surface as the end surface 24 of the semiconductor light emitting device 1. The first groove portion 13, the first stripe portion 14, the second groove portion 15, and the second stripe portion 16 are formed between the end surfaces 23 and 24.

  A p-side electrode 41 is formed on the first stripe portion 14 on the first surface S1 side. The p-side electrode 41 is formed of, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer from the compound semiconductor layer 12 side, for example. The p-side electrode 41 is also formed on the compound semiconductor layer 12 except for the first stripe portion 14 via an insulating film 51 and a silicon layer (not shown).

  An n-side electrode 42 is formed on the second surface S2 of the semiconductor substrate 11. The n-side electrode 42 is, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the semiconductor substrate 11 side, for example.

  For example, the first stripe portion 14 has a width Ws1 of 1.5 μm and a height of 0.5 μm. Further, the width Wd1 of the first groove portion 13 where the first stripe portion 14 is formed is 4.25 μm. Further, the width Wd2 of the second groove portion 15 is equal to the width Wd1 of the first groove portion 13 and is formed to 4.25 μm, and the second stripe portion 16 is equivalent to the first stripe portion 14, The width Ws2 is 1.5 μm and the height is 0.5 μm. The width Ws2 and height of the second stripe portion 16 and the width Wd2 and depth of the second groove portion 15 are appropriately adjusted according to the amount of stress relaxation.

  Next, an example of the compound semiconductor layer 12 and the first stripe portion 14 will be described in detail with reference to the schematic configuration cross-sectional view of FIG. 2 and the enlarged partial cross-sectional view of FIG.

  2 and 3, the compound semiconductor layer 12 includes, from the semiconductor substrate 11 side, an n-type cladding layer 31, an n-type guide layer 32, an active layer 33, an undoped guide layer 34, an optical waveguide layer 35, A p-type electron barrier layer 36, a p-type guide layer 37, a p-type cladding layer 38, and a p-type contact layer 39 are sequentially stacked.

  The n-type cladding layer 31 is made of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and has a film thickness of, for example, 1.3 μm. The aluminum (Al) composition is 0.07.

  The n-type guide layer 32 is made of, for example, an n-type gallium nitride (GaN) guide layer, and has a film thickness of, for example, 0.1 μm.

The active layer 33 is composed of a quantum well layer, for example, a gallium indium nitride (Ga _1-x In _x N) layer having a thickness of 3 nm (wherein the composition x of indium (In) is 0.08); A well is formed by a gallium indium nitride (Ga _{1 -y} In _y N) layer (the composition y of indium (In) is 0.02) that constitutes the barrier layer and has a thickness of 7 nm. It is.

  The undoped guide layer 34 is composed of, for example, an undoped gallium indium nitride (GaInN) guide layer. The undoped gallium indium nitride (GaInN) guide layer has, for example, a thickness of 40 nm and a composition of indium (In) of 0.02.

  The optical waveguide layer 35 is composed of, for example, an undoped aluminum gallium nitride (AlGaN) optical waveguide layer. This undoped aluminum gallium nitride (AlGaN) optical waveguide layer has a thickness of 60 nm, for example, and the composition of aluminum (Al) is 0.02.

  The p-type electron barrier layer 36 is composed of, for example, a p-type aluminum gallium nitride (AlGaN) electron barrier layer, the thickness thereof is 10 nm, and the composition of aluminum (Al) is 0.20.

The p-type guide layer 37 is made of, for example, a p-type gallium nitride (GaN) guide layer. For example, the p-type gallium nitride (GaN) layer having a thickness of 3 nm and a p-type indium gallium (In _0.02 ) having a thickness of 2 nm are used. (Ga _0.98 ) layer. The p-type gallium nitride (GaN) guide layer is doped with magnesium (Mg), for example, 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The p-type cladding layer 38 is composed of a p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer, and has a thickness of 0.5 μm. The composition of aluminum (Al) in the undoped aluminum gallium nitride (AlGaN) layer of the p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer is 0.10. As described above, the first stripe portion 14 and the first groove portion 13 are formed in the p-type cladding layer 38 including the undoped layer.

  The p-type contact layer 39 is made of a p-type gallium nitride (GaN) contact layer, and has a thickness of 0.1 μm, for example.

  The first groove 13 is formed in the p-type cladding layer 38, and the width of the first groove 13 is, for example, 4.25 μm. The first stripe portion 14 is formed in a ridge shape with a p-type cladding layer 38 between the first groove portions 13. The width of the first stripe portion 14 is, for example, 1.5 μm to 2 μm. Yes.

  Next, stress relaxation in the semiconductor light emitting device 1 will be described with reference to the schematic perspective view of the wafer state in FIG. 4A and the schematic cross-sectional view in FIG. FIG. 4 (3) shows a schematic sectional view of a comparative example.

As shown in FIGS. 4A and 4B, a compressive stress is applied to the compound semiconductor layer 12 on the first surface S1 side of the semiconductor substrate 11 in the direction of arrow A parallel to the longitudinal direction of the first stripe portion 14. . Further, a compressive stress indicated by an arrow B is applied in the direction perpendicular to the first stripe portion 14.
In this state, compressive stress is generated at the compound semiconductor layer 12 side of the semiconductor light emitting device 1, specifically, at the interface between the semiconductor substrate 11 and the compound semiconductor layer 12.
However, in the semiconductor light emitting device 1, the second groove portion 15 and the second stripe portion 16 are formed on the second surface S2 of the semiconductor substrate 11, and therefore the second stripe portion 16 is also formed on the second surface S2 side. Compressive stress is applied in a direction parallel to the longitudinal direction. Further, a tensile stress indicated by an arrow D is applied to the second groove portion 15 in the vertical direction and in the outer direction. As a result, the stress in the region between the first stripe portion 14 and the second stripe portion 16 (region surrounded by the one-dot chain line in the drawing) is relieved.
The stress value in the direction of arrow B is 70% of the stress value in the direction of arrow A regardless of the presence or absence of the first groove portion 13 and the first stripe portion 14, and similarly, the stress value in the direction of arrow D is the direction of arrow C. It is 70% of the stress value. As a result of actual measurement, each stress value varies depending on the shapes of the first stripe portion 14 and the second stripe portion 16.

  On the other hand, as shown in FIG. 4C, when nothing is formed on the second surface S2 of the semiconductor substrate 11, a compressive stress indicated by an arrow B is applied to the first surface S1, and the semiconductor substrate 11 A tensile stress indicated by an arrow E is generated on the second surface S2 side, and the semiconductor substrate 11 warps. For this reason, stress relaxation of the first stripe portion 14 and the region of the semiconductor substrate 11 below the first stripe portion 14 cannot be performed.

  In the semiconductor light emitting device 1, the ridge-shaped second stripe portion 16 formed at a position facing the first stripe portion 14 of the second surface S 2 of the semiconductor substrate 11 and the second surface S 2 of the semiconductor substrate are second. It has the 2nd groove part 15 formed in the both sides of the stripe part 16. As shown in FIG. For this reason, the stress generated between the semiconductor substrate 11 and the compound semiconductor layer 12 is relieved, and the stress in the region between the first stripe portion 14 and the second stripe portion 16 is relieved. As a result, stress at the resonance surfaces 21 and 22 is relieved, so that the life of the semiconductor light emitting device 1 is extended. Therefore, there is an advantage that the life characteristics can be improved, and the reliability of the semiconductor light emitting device 1 is increased. Can do.

  An embodiment (second embodiment) according to the semiconductor light emitting device of the present invention will be described with reference to a schematic perspective view and a schematic sectional view of FIG. FIG. 5 shows an example of a first semiconductor light emitting device corresponding to claims 1 and 3.

  As shown in FIG. 5, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11, and an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

  A compound semiconductor layer 12 (hereinafter referred to as a first compound semiconductor layer) is formed on the first surface S1 of the semiconductor substrate 11. Then, for example, two first groove portions 13 are formed on the first compound semiconductor layer 12, and the first compound semiconductor layer 12 is formed between the first groove portions 13 to form a ridge-shaped first stripe portion 14. ing. That is, the first groove portion 13 is formed on both sides of the first stripe portion 14.

On the other hand, a second compound semiconductor layer 17 is formed on the second surface S2 of the semiconductor substrate 11 opposite to the first surface S1.
As an example, the second compound semiconductor layer 17 is made of n-type aluminum gallium nitride (AlGaN) similar to the n-type cladding layer 31 formed to be the thickest in the first compound semiconductor layer 12. Alternatively, it is made of n-type gallium nitride (GaN) similar to the n-type guide layer 32 formed near the first surface S1 on the semiconductor substrate 11 side.

In the second compound semiconductor layer 17, for example, two second groove portions 15 are formed in parallel with the first stripe portion 14 at a position facing the first stripe portion 14. A second stripe portion 16 is formed in the second compound semiconductor layer 17 between the second groove portions 15. That is, the second groove portion 15 is formed on both sides of the second stripe portion 16.
Further, in the semiconductor light emitting device 1 having the above configuration, the resonance surfaces 21 and 22 are formed in the cross-sectional direction perpendicular to the length direction of the first stripe portion 14 and facing each other. The resonance surface 22 is hidden behind the semiconductor light emitting device 1 in the drawing and is not shown directly.
The resonance surface 21 is formed on the same surface as the end surface 23 of the semiconductor light emitting device 1, and the resonance surface 22 is formed on the same surface as the end surface 24 of the semiconductor light emitting device 1. The first groove portion 13, the first stripe portion 14, the second groove portion 15, and the second stripe portion 16 are formed between the end surfaces 23 and 24.

  The thickness of the second compound semiconductor layer 17 is preferably formed to a film thickness that has a stress value substantially equal to the stress value generated by the first compound semiconductor layer 12, but the film thickness has a different stress value. It may be. When formed with film thicknesses having different stress values, the stress value generated on the first surface S1 side of the semiconductor substrate 11 and the stress generated on the second surface S2 side due to the height of the second stripe portion 16. The values are adjusted so that they are almost equal.

  A p-side electrode 41 is formed on the first stripe portion 14 on the first surface S1 side. The p-side electrode 41 is, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer from the first compound semiconductor layer 12 side, for example. The p-side electrode 41 is also formed on the first compound semiconductor layer 12 excluding the first stripe portion 14 via an insulating film 51.

  An n-side electrode 42 is formed on the second surface S2 of the second compound semiconductor layer 17. The n-side electrode 42 is, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the semiconductor substrate 11 side, for example.

  For example, the first stripe portion 14 has a width Ws1 of 1.5 μm and a height of 0.5 μm. Further, the width Wd1 of the first groove portion 13 where the first stripe portion 14 is formed is 4.25 μm. Further, the width Wd2 of the second groove portion 15 is equal to the width Wd1 of the first groove portion 13 and is formed to 4.25 μm, and the second stripe portion 16 is equivalent to the first stripe portion 14, The width Ws2 is 1.5 μm and the height is 0.5 μm. The width Ws2 and height of the second stripe portion 16 and the width Wd2 and depth of the second groove portion 15 are appropriately adjusted according to the amount of stress relaxation.

  Next, an example of the first compound semiconductor layer 12 and the second compound semiconductor layer 17 will be described with reference to FIGS.

As shown in FIGS. 2 and 6, the first compound semiconductor layer 12 includes an n-type cladding layer 31, an n-type guide layer 32, an active layer 33, and an undoped guide from the first surface S1 side of the semiconductor substrate 11. A layer 34, an optical waveguide layer 35, a p-type electron barrier layer 36, a p-type guide layer 37, a p-type cladding layer 38, and a p-type contact layer 39 are sequentially stacked.
A second compound semiconductor layer 17 is formed on the second surface S2 side of the semiconductor substrate 11.

  The n-type cladding layer 31 is made of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and has a film thickness of, for example, 1.3 μm. The aluminum (Al) composition is 0.07.

  The n-type guide layer 32 is made of, for example, an n-type gallium nitride (GaN) guide layer, and has a film thickness of, for example, 0.1 μm.

The active layer 33 is composed of a quantum well layer, for example, a gallium indium nitride (Ga _1-x In _x N) layer having a thickness of 3 nm (wherein the composition x of indium (In) is 0.08); A well is formed by a gallium indium nitride (Ga _{1 -y} In _y N) layer (the composition y of indium (In) is 0.02) that constitutes the barrier layer and has a thickness of 7 nm. It is.

  The undoped guide layer 34 is composed of, for example, an undoped gallium indium nitride (GaInN) guide layer. The undoped gallium indium nitride (GaInN) guide layer has, for example, a thickness of 40 nm and a composition of indium (In) of 0.02.

  The optical waveguide layer 35 is composed of, for example, an undoped aluminum gallium nitride (AlGaN) optical waveguide layer. This undoped aluminum gallium nitride (AlGaN) optical waveguide layer has a thickness of 60 nm, for example, and the composition of aluminum (Al) is 0.02.

  The p-type electron barrier layer 36 is composed of, for example, a p-type aluminum gallium nitride (AlGaN) electron barrier layer, the thickness thereof is 10 nm, and the composition of aluminum (Al) is 0.20.

The p-type guide layer 37 is made of, for example, a p-type gallium nitride (GaN) guide layer. For example, the p-type gallium nitride (GaN) layer having a thickness of 3 nm and a p-type indium gallium (In _0.02 ) having a thickness of 2 nm are used. (Ga _0.98 ) layer. The p-type gallium nitride (GaN) guide layer is doped with magnesium (Mg), for example, 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The p-type cladding layer 38 is composed of a p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer, and has a thickness of 0.5 μm. The composition of aluminum (Al) in the undoped aluminum gallium nitride (AlGaN) layer of the p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer is 0.10. As described above, the first stripe portion 14 and the first groove portion 13 are formed in the p-type cladding layer 38 including the undoped layer.

  The p-type contact layer 39 is made of a p-type gallium nitride (GaN) contact layer, and has a thickness of 0.1 μm, for example.

  The first groove 13 is formed in the p-type cladding layer 38, and the width of the first groove 13 is, for example, 4.25 μm. The first stripe portion 14 is formed in a ridge shape with a p-type cladding layer 38 between the first groove portions 13. The width of the first stripe portion 14 is, for example, 1.5 μm to 2 μm. Yes.

  The second compound semiconductor layer 17 is made of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and has a film thickness of 1.3 μm, for example. The aluminum (Al) composition is 0.07. Alternatively, it consists of an n-type gallium nitride (GaN) guide layer.

  Next, stress relaxation in the semiconductor light emitting device 2 will be described with reference to the schematic perspective view of FIG.

As shown in FIG. 7, a compressive stress is applied to the compound semiconductor layer 12 on the first surface S <b> 1 side of the semiconductor substrate 11 in the arrow A direction parallel to the longitudinal direction of the first stripe portion 14. Further, a compressive stress indicated by an arrow B is applied in the direction perpendicular to the first stripe portion 14.
In this state, since the compressive stress is generated biased toward the compound semiconductor layer 12 side of the semiconductor light emitting device 2, specifically, the interface between the semiconductor substrate 11 and the first compound semiconductor layer 12, the semiconductor light emitting device 2 has the first compound The semiconductor layer 12 side warps so as to shrink.
However, in the semiconductor light emitting device 2, the second compound semiconductor layer 17 is formed on the second surface S 2 side of the semiconductor substrate 11, and the second groove portion 15 and the second stripe portion 16 are formed in the second compound semiconductor layer 17. ing. As a result, compressive stress is also applied to the second surface S2 side in the direction of arrow C parallel to the longitudinal direction of the second stripe portion 16. In addition, a compressive stress indicated by an arrow D is applied in the direction perpendicular to the second stripe portion 16.
Accordingly, since the compressive stress in the same direction is applied to both the first surface S1 side and the second surface S2 side of the semiconductor substrate 11 of the semiconductor light emitting device 2, the tensile stress generated in the semiconductor substrate 11 is offset, and the semiconductor substrate 11 Warpage can be suppressed.
Here, the height of the second stripe portion 16 is adjusted so that stress in the same direction is applied to both the first surface S1 side and the second surface S2 side of the semiconductor substrate 11. For example, the stress value in the arrow C direction can be increased by increasing the height of the second stripe portion 16. Conversely, by reducing the height of the second stripe portion 16, the stress value in the arrow C direction can be weakened.
The compressive stress in the direction of arrow B is 70% of the compressive stress in the direction of arrow A regardless of the presence or absence of the first groove portion 13 and the first stripe portion 14, and similarly, the compressive stress in the direction of arrow D is the direction of arrow C. It is 70% of the compressive stress. As a result of actual measurement, each stress value varies depending on the shape of the first stripe portion 14 and the second stripe portion 16.

  In the semiconductor light emitting device 2, the ridge-shaped second stripe portion 16 and the second stripe portion 16 are formed at positions facing the first stripe portion 14 of the second compound semiconductor layer 17 formed on the second surface S 2 side of the semiconductor substrate 11. The second groove portion 15 is provided on both sides of the two stripe portions 16. Thereby, the stress generated between the semiconductor substrate 11 and the first compound semiconductor layer 12 is relaxed, and the warpage of the semiconductor substrate 11 is reduced. For this reason, since the stress at the resonance surfaces 21 and 22 is relieved, the life of the semiconductor light emitting device 2 is extended. Therefore, there is an advantage that the life characteristics can be improved, and the reliability of the semiconductor light emitting device 2 is improved. Can do.

  In the first and second embodiments, a plurality of second stripe portions 16 and second groove portions 15 formed on both sides of each second stripe portion 16 may be used. Note that the formation of the second stripe portion 16 and the second groove portion 15 at the position facing the first stripe portion 14 is most effective for stress relaxation, and therefore a large number (for example, five or more) of the second groove portions 15 are provided. Even if a large number (for example, four or more) of the second stripe portions 16 are formed, a significant effect is not obtained.

Here, the p-side electrode 41 and the n-side electrode 42 will be described in detail with reference to FIG. Here, the semiconductor light emitting device 2 is shown as an example, but the same applies to the semiconductor light emitting device 1.
An insulating film 61 is formed on the first compound semiconductor layer 12 excluding the inside of the first groove portion 13 formed in the compound semiconductor layer 12 and the upper surface of the first stripe portion 14. This insulating film 61 is used as an etching mask when forming the first groove 13 and may be removed.
Furthermore, an insulating film 51 is formed on the surface of the first compound semiconductor layer 12 (insulating film 61) excluding the inside of the first groove portion 13 formed in the first compound semiconductor layer 12 and the upper surface of the first stripe portion 14. Yes. The insulating film 51 is made of, for example, a silicon oxide film.
Further, a non-doped silicon film 65 is formed on the surface of the insulating film 51. The p-side electrode 41 is formed on the non-doped silicon film 65 and on the upper surface of the first stripe portion 14.
The n-side electrode 42 is formed on the inner surface of the second groove portion 15 formed on the second compound semiconductor layer 17 and the surface of the second compound semiconductor layer 17 (including the surface of the second stripe portion 16).

  An embodiment (third embodiment) according to the semiconductor light emitting device of the present invention will be described with reference to a schematic perspective view and a schematic sectional view of FIG. FIG. 9 shows an example of a second semiconductor light emitting device corresponding to claims 4 and 5.

  As shown in FIG. 9, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11, and an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

  A compound semiconductor layer 12 is formed on the first surface S1 of the semiconductor substrate 11. A ridge-shaped stripe portion 18 is formed on the top of the compound semiconductor layer 12.

On the other hand, on the second surface S2 opposite to the first surface S1 of the semiconductor substrate 11, a groove portion 19 is formed in parallel to the stripe portion 18 at a position facing the stripe portion 18.
Further, in the semiconductor light emitting device 3 having the above-described configuration, the resonance surfaces 21 and 22 are formed in the cross-sectional direction perpendicular to the length direction of the stripe portion 18 and facing each other. The resonance surface 22 is hidden behind the semiconductor light emitting device 3 in the drawing and is not shown directly.
The resonance surface 21 is formed on the same surface as the end surface 23 of the semiconductor light emitting device 3, and the resonance surface 22 is formed on the same surface as the end surface 24 of the semiconductor light emitting device 1. The stripe portions 18 and the groove portions 19 are formed between the end faces 23 and 24.

  A p-side electrode 41 is formed on the stripe portion 18 on the first surface S1 side. The p-side electrode 41 is, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer, for example, from the compound semiconductor layer 12 side. The p-side electrode 41 is also formed on the compound semiconductor layer 12 excluding the stripe portion 18 via an insulating film 51.

  An n-side electrode 42 is formed on the second surface S2 of the semiconductor substrate 11. The n-side electrode 42 is, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the semiconductor substrate 11 side, for example.

  For example, the stripe portion 18 has a width Ws1 of 1.5 μm and a height of 0.5 μm. The groove 19 has a width Wd2 of 1.5 μm and a depth of 0.5 μm, for example. The width Wd2, the height, and the like of the groove 18 are appropriately adjusted according to the amount of stress relaxation.

  Next, an example of the detailed layer structure of the compound semiconductor layer 12 and the stripe portion 18 is the same as that described with reference to FIGS.

  That is, as shown in FIGS. 3 and 4, the compound semiconductor layer 12 includes the n-type cladding layer 31, the n-type guide layer 32, the active layer 33, the undoped guide layer 34, and the optical waveguide from the semiconductor substrate 11 side. A layer 35, a p-type electron barrier layer 36, a p-type guide layer 37, a p-type cladding layer 38, and a p-type contact layer 39 are stacked in this order.

  The n-type cladding layer 31 is made of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and has a film thickness of, for example, 1.3 μm. The aluminum (Al) composition is 0.07.

  The n-type guide layer 32 is made of, for example, an n-type gallium nitride (GaN) guide layer, and has a film thickness of, for example, 0.1 μm.

The active layer 33 is composed of a quantum well layer, for example, a gallium indium nitride (Ga _1-x In _x N) layer having a thickness of 3 nm (wherein the composition x of indium (In) is 0.08); A well is formed by a gallium indium nitride (Ga _{1 -y} In _y N) layer (the composition y of indium (In) is 0.02) that constitutes the barrier layer and has a thickness of 7 nm. It is.

  The undoped guide layer 34 is composed of, for example, an undoped gallium indium nitride (GaInN) guide layer. The undoped gallium indium nitride (GaInN) guide layer has, for example, a thickness of 40 nm and a composition of indium (In) of 0.02.

  The optical waveguide layer 35 is composed of, for example, an undoped aluminum gallium nitride (AlGaN) optical waveguide layer. This undoped aluminum gallium nitride (AlGaN) optical waveguide layer has a thickness of 60 nm, for example, and the composition of aluminum (Al) is 0.02.

  The p-type electron barrier layer 36 is composed of, for example, a p-type aluminum gallium nitride (AlGaN) electron barrier layer, the thickness thereof is 10 nm, and the composition of aluminum (Al) is 0.20.

The p-type guide layer 37 is made of, for example, a p-type gallium nitride (GaN) guide layer. For example, the p-type gallium nitride (GaN) layer having a thickness of 3 nm and a p-type indium gallium (In _0.02 ) having a thickness of 2 nm are used. (Ga _0.98 ) layer. The p-type gallium nitride (GaN) guide layer is doped with magnesium (Mg), for example, 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The p-type cladding layer 38 is composed of a p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer, and has a thickness of 0.5 μm. The composition of aluminum (Al) in the undoped aluminum gallium nitride (AlGaN) layer of the p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer is 0.10. Thus, the stripe portion 18 is formed in the p-type cladding layer 38 including the undoped layer. The width of the stripe portion 18 is formed in a range of 1.5 μm to 2 μm, for example.

  The p-type contact layer 39 is made of a p-type gallium nitride (GaN) contact layer, and has a thickness of 0.1 μm, for example.

  Next, stress relaxation in the semiconductor light emitting device 3 will be described with reference to a schematic perspective view of a wafer state in FIG. 10A and a schematic cross-sectional view in FIG. FIG. 10 (3) shows a schematic sectional view of a comparative example.

As shown in FIGS. 10A and 10B, a compressive stress is applied to the compound semiconductor layer 12 on the first surface S <b> 1 side of the semiconductor substrate 11 in the direction of arrow A parallel to the longitudinal direction of the stripe portion 18. Further, a compressive stress indicated by an arrow B is applied in a direction perpendicular to the stripe portion 18.
In this state, compressive stress is generated at the compound semiconductor layer 12 side of the semiconductor light emitting device 3, specifically, at the interface between the semiconductor substrate 11 and the compound semiconductor layer 12.
However, in the semiconductor light emitting device 3, since the groove portion 19 is formed on the second surface S <b> 2 of the semiconductor substrate 11, the second surface S <b> 2 side is also perpendicular to the second groove portion 15 and outward. Applies a tensile stress indicated by an arrow D. As a result, the stress in the stripe portion 18 and the region of the semiconductor substrate 11 therebelow (the region surrounded by the one-dot chain line in the drawing) is relieved.
Note that there is no effect on stress relaxation in a direction parallel to the longitudinal direction of the groove 19.
Regardless of the presence or absence of the stripe portion 18, the compressive stress in the arrow B direction is 70% of the compressive stress in the arrow A direction, and similarly, the compressive stress in the arrow D direction is 70% of the compressive stress in the arrow C direction. is there. As a result of actual measurement, each compressive stress value varies depending on the shapes of the first stripe portion 14 and the second stripe portion 16.

  On the other hand, as shown in FIG. 10 (3), when nothing is formed on the second surface of the semiconductor substrate 11, the compressive stress indicated by the arrow B is applied to the first surface S1 side, and A tensile stress is generated on the second surface S2 side, and the semiconductor substrate 11 warps. For this reason, stress relaxation of the first stripe portion 18 and the region of the semiconductor substrate 11 below the first stripe portion 18 cannot be performed.

  In the semiconductor light emitting device 3, the groove portion 19 is provided at a position facing the stripe portion 14 on the second surface S <b> 2 opposite to the first surface S <b> 1 of the semiconductor substrate 11. For this reason, the stress which generate | occur | produces between the semiconductor substrate 11 and the 1st compound semiconductor layer 12 is relieve | moderated, and the curvature of the semiconductor substrate 11 is reduced. As a result, the stress at the resonance surfaces 21 and 22 is relieved, so that the life of the semiconductor light emitting device 3 is extended. Therefore, there is an advantage that the life characteristics can be improved, and the reliability of the semiconductor light emitting device 3 is improved. Can do.

  An embodiment (fourth embodiment) according to the semiconductor light emitting device of the present invention will be described with reference to a schematic perspective view and a schematic sectional view of FIG. FIG. 11 shows an example of a second semiconductor light emitting device corresponding to claims 4 and 6.

  As shown in FIG. 11, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11, and an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

  A compound semiconductor layer 12 (hereinafter referred to as a first compound semiconductor layer) is formed on the first surface S1 of the semiconductor substrate 11. A ridge-shaped stripe portion 18 is formed on the first compound semiconductor layer 12.

On the other hand, a second compound semiconductor layer 17 is formed on the second surface S2 of the semiconductor substrate 11 opposite to the first surface S1.
For example, the second compound semiconductor layer 17 is formed of n-type aluminum gallium nitride (AlGaN) similar to the n-type cladding layer formed to be the thickest in the first compound semiconductor layer 12. Alternatively, it is made of n-type gallium nitride (GaN) similar to the n-type guide layer formed near the first surface S1 on the semiconductor substrate 11 side.

In the second compound semiconductor layer 17, a groove portion 19 is formed in parallel with the stripe portion 18 at a position facing the stripe portion 18.
Further, in the semiconductor light emitting device 4 having the above configuration, the resonance surfaces 21 and 22 are formed in the cross-sectional direction perpendicular to the length direction of the stripe portion 18 and facing each other. The resonance surface 22 is hidden behind the semiconductor light emitting device 3 in the drawing and is not shown directly.
The resonance surface 21 is formed on the same surface as the end surface 23 of the semiconductor light emitting device 3, and the resonance surface 22 is formed on the same surface as the end surface 24 of the semiconductor light emitting device 1. The stripe portions 18 and the groove portions 19 are formed between the end faces 23 and 24.

  The thickness of the second compound semiconductor layer 17 is preferably formed to a film thickness that has a stress value substantially equal to the stress value generated by the first compound semiconductor layer 12, but the film thickness has a different stress value. It may be. When formed with different film thicknesses, the stress value generated on the first surface S1 side of the semiconductor substrate 11 and the stress value generated on the second surface S2 side of the semiconductor substrate 11 are almost equal depending on the depth of the groove 19. It is adjusted to be equivalent.

  A p-side electrode 41 is formed on the stripe portion 18 on the first surface S1 side. The p-side electrode 41 is, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer from the first compound semiconductor layer 12 side, for example. The p-side electrode 41 is also formed on the first compound semiconductor layer 12 excluding the stripe portion 18 with an insulating film 51 interposed therebetween.

  An n-side electrode 42 is formed on the second compound semiconductor layer 17 on the second surface S2 side of the semiconductor substrate 11. The n-side electrode 42 is, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the semiconductor substrate 11 side, for example.

  For example, the stripe portion 18 has a width Ws1 of 1.5 μm and a height of 0.5 μm. The groove 19 has a width Wd2 of 1.5 μm and a depth of 5 μm, for example. The width Wd2, height, and the like of the groove portion 19 are appropriately adjusted according to the amount of stress relaxation.

  Next, an example of the detailed layer structure of the first compound semiconductor layer 12 and the stripe portion 18 is the same as that described with reference to FIGS.

  That is, as shown in FIGS. 3 and 4, the first compound semiconductor layer 12 includes an n-type cladding layer 31, an n-type guide layer 32, an active layer 33, an undoped guide layer 34, from the semiconductor substrate 11 side. An optical waveguide layer 35, a p-type electron barrier layer 36, a p-type guide layer 37, a p-type cladding layer 38, and a p-type contact layer 39 are sequentially stacked.

  The n-type cladding layer 31 is made of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and has a film thickness of, for example, 1.3 μm. The aluminum (Al) composition is 0.07.

  The n-type guide layer 32 is made of, for example, an n-type gallium nitride (GaN) guide layer, and has a film thickness of, for example, 0.1 μm.

The active layer 33 is composed of a quantum well layer, for example, a gallium indium nitride (Ga _1-x In _x N) layer having a thickness of 3 nm (wherein the composition x of indium (In) is 0.08); A well is formed by a gallium indium nitride (Ga _{1 -y} In _y N) layer (the composition y of indium (In) is 0.02) that constitutes the barrier layer and has a thickness of 7 nm. It is.

  The undoped guide layer 34 is composed of, for example, an undoped gallium indium nitride (GaInN) guide layer. The undoped gallium indium nitride (GaInN) guide layer has, for example, a thickness of 40 nm and a composition of indium (In) of 0.02.

  The optical waveguide layer 35 is composed of, for example, an undoped aluminum gallium nitride (AlGaN) optical waveguide layer. This undoped aluminum gallium nitride (AlGaN) optical waveguide layer has a thickness of 60 nm, for example, and the composition of aluminum (Al) is 0.02.

  The p-type electron barrier layer 36 is composed of, for example, a p-type aluminum gallium nitride (AlGaN) electron barrier layer, the thickness thereof is 10 nm, and the composition of aluminum (Al) is 0.20.

The p-type guide layer 37 is made of, for example, a p-type gallium nitride (GaN) guide layer. For example, the p-type gallium nitride (GaN) layer having a thickness of 3 nm and a p-type indium gallium (In _0.02 ) having a thickness of 2 nm are used. (Ga _0.98 ) layer. The p-type gallium nitride (GaN) guide layer is doped with magnesium (Mg), for example, 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The p-type cladding layer 38 is composed of a p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer, and has a thickness of 0.5 μm. The composition of aluminum (Al) in the undoped aluminum gallium nitride (AlGaN) layer of the p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer is 0.10. Thus, the stripe portion 18 is formed in the p-type cladding layer 38 including the undoped layer. The width of the stripe portion 18 is formed in a range of 1.5 μm to 2 μm, for example.

  The p-type contact layer 39 is made of a p-type gallium nitride (GaN) contact layer, and has a thickness of 0.1 μm, for example.

  Next, stress relaxation in the semiconductor light emitting device 4 will be described with reference to a schematic perspective view of a wafer state in FIG. 12A and a schematic cross-sectional view in FIG. FIG. 12 (3) shows a schematic cross-sectional view of a comparative example.

As shown in FIGS. 12A and 12B, compressive stress is applied to the first compound semiconductor layer 12 on the first surface S1 side of the semiconductor substrate 11 in the direction of arrow A parallel to the longitudinal direction of the stripe portion 18. Take it. Further, a compressive stress indicated by an arrow B is applied in a direction perpendicular to the stripe portion 18.
In this state, compressive stress is generated at the first compound semiconductor layer 12 side of the semiconductor light emitting device 4, specifically, at the interface between the semiconductor substrate 11 and the first compound semiconductor layer 12.
However, in the semiconductor light emitting device 4, since the groove portion 19 is formed in the second compound semiconductor layer 17 formed on the second surface S2 of the semiconductor substrate 11, the second groove portion is also formed on the second surface S2 side. A tensile stress indicated by an arrow D is applied in a direction perpendicular to the direction 15 and outward. As a result, the stress in the stripe portion 18 and the region of the semiconductor substrate 11 therebelow (the region surrounded by the one-dot chain line in the drawing) is relieved.
Note that there is no effect on stress relaxation in a direction parallel to the longitudinal direction of the groove 19.
Regardless of the presence or absence of the stripe portion 18, the compressive stress in the arrow B direction is 70% of the compressive stress in the arrow A direction, and similarly, the compressive stress in the arrow D direction is 70% of the compressive stress in the arrow C direction. is there. As a result of actual measurement, each compressive stress value varies depending on the shapes of the stripe portion 18 and the groove portion 19.

  On the other hand, as shown in FIG. 12 (3), when nothing is formed on the second surface S2 of the semiconductor substrate 11, the compressive stress indicated by the arrow B is applied to the first surface S1, and the semiconductor substrate 11 A tensile stress is generated on the second surface S2 side, and the semiconductor substrate 11 warps. For this reason, stress relaxation of the stripe portion 18 and the region of the semiconductor substrate 11 below the stripe portion 18 cannot be performed.

  In the semiconductor light emitting device 4, the groove portion 19 is provided at a position facing the stripe portion 14 of the second compound semiconductor layer 17 formed on the second surface S2 side opposite to the first surface S1 of the semiconductor substrate 11. For this reason, the stress which generate | occur | produces between the semiconductor substrate 11 and the 1st compound semiconductor layer 12 is relieve | moderated, and the curvature of the semiconductor substrate 11 is reduced. As a result, stress on the resonance surfaces 21 and 22 is relieved, so that the life of the semiconductor light emitting device 4 is extended. Therefore, there is an advantage that the life characteristics can be improved, and the reliability of the semiconductor light emitting device 4 is improved. Can do.

  An embodiment (fifth embodiment) according to a semiconductor light-emitting device of the present invention will be described with reference to a schematic perspective view and a schematic cross-sectional view of FIG. FIG. 13 shows an example of a second semiconductor light emitting device corresponding to claims 4 and 5.

  As shown in FIG. 13, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11, and an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

  A compound semiconductor layer 12 is formed on the first surface S1 of the semiconductor substrate 11. A ridge-shaped first stripe portion 18 is formed on the top of the compound semiconductor layer 12.

On the other hand, on the second surface S2 opposite to the first surface S1 of the semiconductor substrate 11, a second ridge-shaped second is formed in parallel with the first stripe portion 18 at a position facing the first stripe portion 18. A stripe portion 20 is formed.
In the semiconductor light emitting device 5 having the above-described configuration, resonance surfaces 21 and 22 are formed in a cross-sectional direction perpendicular to the length direction of the first stripe portion 18 and facing each other. The resonance surface 22 is hidden behind the semiconductor light emitting device 5 in the drawing and is not shown directly.
The resonance surface 21 is formed on the same surface as the end surface 23 of the semiconductor light emitting device 5, and the resonance surface 22 is formed on the same surface as the end surface 24 of the semiconductor light emitting device 1. The first stripe portion 18 and the second stripe portion 20 are formed between the end faces 23 and 24.

  A p-side electrode 41 is formed on the first stripe portion 18 on the first surface S1 side. The p-side electrode 41 is, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer, for example, from the compound semiconductor layer 12 side. The p-side electrode 41 is also formed on the compound semiconductor layer 12 except for the first stripe portion 18 via an insulating film 51.

  An n-side electrode 42 is formed on the second surface S2 of the semiconductor substrate 11. The n-side electrode 42 is, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the semiconductor substrate 11 side, for example.

  For example, the first stripe portion 18 has a width Ws1 of 1.5 μm and a height of 0.5 μm. The second stripe portion 20 has a width Ws2 of 1.5 μm and a height of 0.5 μm, for example. The width Ws2, the height, and the like of the second stripe portion 20 are appropriately adjusted depending on the amount of stress relaxation.

  Next, an example of the detailed layer structure of the first compound semiconductor layer 12 and the first stripe portion 18 is the same as that described with reference to FIGS.

  That is, as shown in FIGS. 3 and 4, the compound semiconductor layer 12 includes the n-type cladding layer 31, the n-type guide layer 32, the active layer 33, the undoped guide layer 34, and the optical waveguide from the semiconductor substrate 11 side. A layer 35, a p-type electron barrier layer 36, a p-type guide layer 37, a p-type cladding layer 38, and a p-type contact layer 39 are stacked in this order.

  The n-type cladding layer 31 is made of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and has a film thickness of, for example, 1.3 μm. The aluminum (Al) composition is 0.07.

  The n-type guide layer 32 is made of, for example, an n-type gallium nitride (GaN) guide layer, and has a film thickness of, for example, 0.1 μm.

The active layer 33 is composed of a quantum well layer, for example, a gallium indium nitride (Ga _1-x In _x N) layer having a thickness of 3 nm (wherein the composition x of indium (In) is 0.08); A well is formed by a gallium indium nitride (Ga _{1 -y} In _y N) layer (the composition y of indium (In) is 0.02) that constitutes the barrier layer and has a thickness of 7 nm. It is.

  The undoped guide layer 34 is composed of, for example, an undoped gallium indium nitride (GaInN) guide layer. The undoped gallium indium nitride (GaInN) guide layer has, for example, a thickness of 40 nm and a composition of indium (In) of 0.02.

  The optical waveguide layer 35 is composed of, for example, an undoped aluminum gallium nitride (AlGaN) optical waveguide layer. This undoped aluminum gallium nitride (AlGaN) optical waveguide layer has a thickness of 60 nm, for example, and the composition of aluminum (Al) is 0.02.

  The p-type electron barrier layer 36 is composed of, for example, a p-type aluminum gallium nitride (AlGaN) electron barrier layer, the thickness thereof is 10 nm, and the composition of aluminum (Al) is 0.20.

The p-type guide layer 37 is made of, for example, a p-type gallium nitride (GaN) guide layer. For example, the p-type gallium nitride (GaN) layer having a thickness of 3 nm and a p-type indium gallium (In _0.02 ) having a thickness of 2 nm are used. (Ga _0.98 ) layer. The p-type gallium nitride (GaN) guide layer is doped with magnesium (Mg), for example, 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The p-type cladding layer 38 is composed of a p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer, and has a thickness of 0.5 μm. The composition of aluminum (Al) in the undoped aluminum gallium nitride (AlGaN) layer of the p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer is 0.10. Thus, the stripe portion 18 is formed in the p-type cladding layer 38 including the undoped layer. The width of the stripe portion 18 is formed in a range of 1.5 μm to 2 μm, for example.

  The p-type contact layer 39 is made of a p-type gallium nitride (GaN) contact layer, and has a thickness of 0.1 μm, for example.

  Next, stress relaxation in the semiconductor light emitting device 5 will be described with reference to a schematic perspective view of a wafer state in FIG. 14A and a schematic cross-sectional view in FIG.

As shown in FIGS. 14A and 14B, a compressive stress is applied to the compound semiconductor layer 12 on the first surface S1 side of the semiconductor substrate 11 in the direction of arrow A parallel to the longitudinal direction of the stripe portion 18. Further, a compressive stress indicated by an arrow B is applied in a direction perpendicular to the stripe portion 18.
In this state, compressive stress is generated at the compound semiconductor layer 12 side of the semiconductor light emitting device 5, specifically, at the interface between the semiconductor substrate 11 and the compound semiconductor layer 12.
However, in the semiconductor light emitting device 5, since the groove portion 19 is formed on the second surface S <b> 2 of the semiconductor substrate 11, the second surface S <b> 2 side is also perpendicular to the second groove portion 15 and outward. Applies a tensile stress indicated by an arrow D. As a result, the stress in the stripe portion 18 and the region of the semiconductor substrate 11 therebelow (the region surrounded by the one-dot chain line in the drawing) is relieved.
Note that there is no effect on stress relaxation in a direction parallel to the longitudinal direction of the groove 19.
Regardless of the presence or absence of the stripe portion 18, the compressive stress in the arrow B direction is 70% of the compressive stress in the arrow A direction, and similarly, the compressive stress in the arrow D direction is 70% of the compressive stress in the arrow C direction. is there. As a result of actual measurement, each compressive stress value varies depending on the shapes of the first stripe portion 14 and the second stripe portion 16.

  On the other hand, as shown in FIG. 10 (3), when nothing is formed on the second surface of the semiconductor substrate 11, the compressive stress indicated by the arrow B is applied to the first surface S1 side, and A tensile stress is generated on the second surface S2 side, and the semiconductor substrate 11 warps. For this reason, stress relaxation of the first stripe portion 14 and the region of the semiconductor substrate 11 below the first stripe portion 14 cannot be performed.

  In the semiconductor light emitting device 3, the groove portion 19 is provided at a position facing the stripe portion 14 on the second surface S <b> 2 opposite to the first surface S <b> 1 of the semiconductor substrate 11. For this reason, the stress which generate | occur | produces between the semiconductor substrate 11 and the 1st compound semiconductor layer 12 is relieve | moderated, and the curvature of the semiconductor substrate 11 is reduced. As a result, stress on the resonance surfaces 21 and 22 is relieved, so that the life of the semiconductor light emitting device 3 is extended. Therefore, there is an advantage that the life characteristics can be improved, and the reliability of the semiconductor light emitting device 5 is improved. Can do.

  An embodiment (sixth embodiment) according to the semiconductor light-emitting device of the present invention will be described with reference to a schematic perspective view and a schematic sectional view of FIG. FIG. 15 shows an example of a second semiconductor light emitting device corresponding to claims 4 and 6.

  As shown in FIG. 15, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11, and an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

  A compound semiconductor layer (hereinafter referred to as a first compound semiconductor layer) 12 is formed on the first surface S1 of the semiconductor substrate 11. A ridge-shaped stripe portion (hereinafter referred to as a first stripe portion) 18 is formed on the first compound semiconductor layer 12.

On the other hand, a second compound semiconductor layer 17 is formed on the second surface S2 of the semiconductor substrate 11 opposite to the first surface S1.
For example, the second compound semiconductor layer 17 is formed of n-type aluminum gallium nitride (AlGaN) similar to the n-type cladding layer formed to be the thickest in the first compound semiconductor layer 12. Alternatively, it is made of n-type gallium nitride (GaN) similar to the n-type guide layer formed near the first surface S1 on the semiconductor substrate 11 side.
In the second compound semiconductor layer 17, a second stripe portion 20 is formed in parallel to the first stripe portion 18 at a position facing the first stripe portion 18.
In the semiconductor light emitting device 6 having the above configuration, the resonance surfaces 21 and 22 are formed so as to face each other in the cross-sectional direction perpendicular to the length direction of the first stripe portion 18. The resonance surface 22 is hidden behind the semiconductor light emitting device 6 in the drawing and is not shown directly.
The resonance surface 21 is formed on the same surface as the end surface 23 of the semiconductor light emitting device 6, and the resonance surface 22 is formed on the same surface as the end surface 24 of the semiconductor light emitting device 1. The first stripe portion 18 and the second stripe portion 20 are formed between the end faces 23 and 24.

  The thickness of the second compound semiconductor layer 17 is preferably formed to a film thickness that has a stress value substantially equal to the stress value generated by the first compound semiconductor layer 12, but the film thickness has a different stress value. It may be. When formed with film thicknesses having different stress values, the stress value generated on the first surface S1 side of the semiconductor substrate 11 and the stress generated on the second surface S2 side depending on the height of the second stripe portion 20. The values are adjusted so that they are almost equal.

  A p-side electrode 41 is formed on the first stripe portion 18 on the first surface S1 side. The p-side electrode 41 is, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer from the first compound semiconductor layer 12 side, for example. The p-side electrode 41 is also formed on the first compound semiconductor layer 12 except for the first stripe portion 18 via an insulating film 51.

  An n-side electrode 42 is formed on the second compound semiconductor layer 17 on the second surface S2 side of the semiconductor substrate 11. The n-side electrode 42 is, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the semiconductor substrate 11 side, for example.

  For example, the first stripe portion 18 has a width Ws1 of 1.5 μm and a height of 0.5 μm. The second stripe portion 20 has a width Ws2 of 1.5 μm and a height of 0.5 μm, for example. The width Ws2, the height, and the like of the second stripe portion 20 are appropriately adjusted depending on the amount of stress relaxation.

  Next, an example of the detailed layer structure of the first compound semiconductor layer 12 and the first stripe portion 18 is the same as that described with reference to FIGS.

  That is, as shown in FIGS. 3 and 4, the first compound semiconductor layer 12 includes an n-type cladding layer 31, an n-type guide layer 32, an active layer 33, an undoped guide layer 34, from the semiconductor substrate 11 side. An optical waveguide layer 35, a p-type electron barrier layer 36, a p-type guide layer 37, a p-type cladding layer 38, and a p-type contact layer 39 are sequentially stacked.

  The n-type cladding layer 31 is made of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and has a film thickness of, for example, 1.3 μm. The aluminum (Al) composition is 0.07.

  The n-type guide layer 32 is made of, for example, an n-type gallium nitride (GaN) guide layer, and has a film thickness of, for example, 0.1 μm.

The active layer 33 is composed of a quantum well layer, for example, a gallium indium nitride (Ga _1-x In _x N) layer having a thickness of 3 nm (wherein the composition x of indium (In) is 0.08); A well is formed by a gallium indium nitride (Ga _{1 -y} In _y N) layer (the composition y of indium (In) is 0.02) that constitutes the barrier layer and has a thickness of 7 nm. It is.

  The undoped guide layer 34 is composed of, for example, an undoped gallium indium nitride (GaInN) guide layer. The undoped gallium indium nitride (GaInN) guide layer has, for example, a thickness of 40 nm and a composition of indium (In) of 0.02.

  The optical waveguide layer 35 is composed of, for example, an undoped aluminum gallium nitride (AlGaN) optical waveguide layer. This undoped aluminum gallium nitride (AlGaN) optical waveguide layer has a thickness of 60 nm, for example, and the composition of aluminum (Al) is 0.02.

  The p-type electron barrier layer 36 is composed of, for example, a p-type aluminum gallium nitride (AlGaN) electron barrier layer, the thickness thereof is 10 nm, and the composition of aluminum (Al) is 0.20.

The p-type guide layer 37 is made of, for example, a p-type gallium nitride (GaN) guide layer. For example, the p-type gallium nitride (GaN) layer having a thickness of 3 nm and a p-type indium gallium (In _0.02 ) having a thickness of 2 nm are used. (Ga _0.98 ) layer. The p-type gallium nitride (GaN) guide layer is doped with magnesium (Mg), for example, 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The p-type cladding layer 38 is composed of a p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer, and has a thickness of 0.5 μm. The composition of aluminum (Al) in the undoped aluminum gallium nitride (AlGaN) layer of the p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer is 0.10. Thus, the first stripe portion 18 is formed in the p-type cladding layer 38 including the undoped layer. The width of the first stripe portion 18 is, for example, in the range of 1.5 μm to 2 μm.

  The p-type contact layer 39 is made of a p-type gallium nitride (GaN) contact layer, and has a thickness of 0.1 μm, for example.

  Next, stress relaxation in the semiconductor light emitting device 6 will be described with reference to the schematic perspective view of FIG.

As shown in FIG. 16, a compressive stress is applied to the first compound semiconductor layer 12 on the first surface S <b> 1 side of the semiconductor substrate 11 in the arrow A direction parallel to the longitudinal direction of the first stripe portion 18. Further, a compressive stress indicated by an arrow B is applied in a direction perpendicular to the first stripe portion 18.
In this state, a compressive stress is generated on the first compound semiconductor layer 12 side of the semiconductor light emitting device 6, specifically on the interface between the semiconductor substrate 11 and the first compound semiconductor layer 12. The one compound semiconductor layer 12 side warps so as to shrink.
However, in the semiconductor light emitting device 6, the second compound semiconductor layer 17 is formed on the second surface S 2 side of the semiconductor substrate 11, and the second stripe portion 20 is formed in the second compound semiconductor layer 17. As a result, compressive stress is also applied to the second surface S2 side in the direction of arrow C parallel to the longitudinal direction of the second stripe portion 20. Further, a compressive stress indicated by an arrow D is applied in a direction perpendicular to the second stripe portion 20.
Therefore, since the compressive stress in the same direction is applied to both the first surface S1 side and the second surface S2 side of the semiconductor substrate 11 of the semiconductor light emitting device 6, the tensile stress generated in the semiconductor substrate 11 is offset, and the semiconductor substrate 11 Warpage can be suppressed.
Here, the height of the second stripe portion 20 is adjusted so that stress in the same direction is applied to both the first surface S1 side and the second surface S2 side of the semiconductor substrate 11. For example, the stress value in the arrow C direction can be increased by increasing the height of the second stripe portion 20. Conversely, by reducing the height of the second stripe portion 20, the stress value in the arrow C direction can be weakened.
The compressive stress in the direction of arrow B is 70% of the compressive stress in the direction of arrow A regardless of the presence or absence of the first stripe portion 18, and similarly, the compressive stress in the direction of arrow D is 70% of the compressive stress in the direction of arrow C. %. As a result of actual measurement, each stress value varies depending on the shapes of the first stripe portion 18 and the second stripe portion 20.

  In the semiconductor light emitting device 6, the second stripe portion 20 having a ridge shape is provided at a position facing the first stripe portion 18 of the second compound semiconductor layer 17 formed on the second surface S <b> 2 side of the semiconductor substrate 11. Thereby, the stress generated between the semiconductor substrate 11 and the first compound semiconductor layer 12 is relaxed, and the warpage of the semiconductor substrate 11 is reduced. For this reason, since the stress at the resonance surfaces 21 and 22 is relieved, the life of the semiconductor light emitting device 6 is extended. Therefore, there is an advantage that the life characteristics can be improved, and the reliability of the semiconductor light emitting device 6 is improved. Can do.

The depth of the second groove portion 15 and the groove portion 19 in each of the above embodiments has an effect of suppressing stress between the semiconductor substrate 11 and the compound semiconductor layer 12 stacked thereon, and may be a depth of 0.1 μm or more. .
In addition, the groove portions 19 and the second stripe portions 20 in the third to sixth embodiments are most effective for stress relaxation if they are formed at positions facing the stripe portions (first stripe portions) 18. Even if the groove portions 19 (for example, five or more) and the multiple (for example, four or more) second stripe portions 20 are formed, a particularly great effect is not obtained.
Moreover, as shown in FIG. 17, even if the second stripe portion 20 is formed to have a width that is, for example, three times or more the width Ws1 of the first stripe portion 14, an effect of stress relaxation cannot be obtained. This configuration is the same as the configuration disclosed in Patent Document 1 described in the related art.
The second stripe portion 20 is preferably formed at a position facing the first stripe portion 14 (stripe portion 18) and having a width equivalent to that of the first stripe portion 14. Although not shown in the drawing, the same applies to the second groove portion 15 and the groove portion 19, and the widths of the second groove portion 15 and the groove portion 19 are the positions facing the first stripe portion 14 (stripe portion 18) and It is preferable to form the same width as the first stripe portion 14.

Further, the second stripe portion 16 and the second stripe portion 20 may be formed wider from both ends toward the central portion. As described above, since the second stripe portions 16 and 20 are formed wider toward the center, the cross sections at both ends of the second stripe portions 16 and 20 are narrower than the cross sections of the other regions. It becomes easy to cleave at the part.
Moreover, the said 2nd groove part 15 and the groove part 19 may be narrowly formed as it goes to a center part from both ends. Thus, since the second groove portion 15 and the groove portion 19 are formed narrower toward the central portion, the cross sections at both ends of the second groove portion 15 and the groove portion 19 are narrower than the cross sections of other regions. It becomes easy to cleave at that part.

  Next, an embodiment (first embodiment) according to a method for manufacturing a semiconductor light emitting device of the present invention will be described with reference to schematic cross-sectional views of FIGS. 18 to 20 show an example of a second semiconductor light emitting device corresponding to claims 7 and 8.

  As shown in FIG. 18A, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11. For example, an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

The compound semiconductor layer 12 is formed on the first surface S1 of the semiconductor substrate 11.
The compound semiconductor layer 12 is formed by, for example, epitaxial growth from the side of the semiconductor substrate 11 from the n-type cladding layer 31, the n-type guide layer 32, the active layer 33, and the undoped, as described with reference to FIGS. The guide layer 34, the optical waveguide layer 35, the p-type electron barrier layer 36, the p-type guide layer 37, the p-type cladding layer 38, and the p-type contact layer 39 are sequentially stacked.

  The n-type cladding layer 31 is formed of, for example, an n-type aluminum gallium nitride (AlGaN) cladding layer, and the thickness thereof is set to 1.3 μm, for example. Moreover, the aluminum (Al) composition was set to 0.07, for example.

  The n-type guide layer 32 is formed of, for example, an n-type gallium nitride (GaN) guide layer, and has a thickness of 0.1 μm, for example.

The active layer 33 is composed of a quantum well layer. For example, for example, a gallium indium nitride (Ga _{1 -x} In _x N) layer (wherein the composition x of indium (In) is 0.08) and a barrier layer such as gallium indium nitride (Ga _{1 -y} In _y) N) layers (where the composition y of indium (In) is, for example, 0.02) form a well. The thickness of the gallium indium nitride (Ga _1-x In _x N) layer is, for example, 3 nm. The thickness of the gallium indium nitride (Ga _{1 -y} In _y N) layer is, for example, 7 nm. The number of wells is set to 3, for example.

  The undoped guide layer 34 is formed of, for example, an undoped gallium indium nitride (GaInN) guide layer. The undoped gallium indium nitride (GaInN) guide layer has a thickness of, for example, 40 nm, and the composition of indium (In) is, for example, 0.02.

  The optical waveguide layer 35 is formed of, for example, an undoped aluminum gallium nitride (AlGaN) optical waveguide layer. The undoped aluminum gallium nitride (AlGaN) optical waveguide layer has a thickness of 60 nm, for example, and a composition of aluminum (Al), for example, 0.02.

  The p-type electron barrier layer 36 is formed of, for example, a p-type aluminum gallium nitride (AlGaN) electron barrier layer, and has a thickness of 10 nm, for example, and a composition of aluminum (Al), for example, 0.20.

The p-type guide layer 37 is formed of, for example, a p-type gallium nitride (GaN) guide layer, for example, a p-type gallium nitride (GaN) layer having a thickness of 3 nm and a p-type indium gallium (In) having a thickness of 2 nm. _0.02 Ga _0.98 ) layer. The p-type gallium nitride (GaN) guide layer is doped with magnesium (Mg), for example, 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The p-type cladding layer 38 is formed of a p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer and has a thickness of 0.5 μm, for example. In addition, the composition of aluminum (Al) in the undoped aluminum gallium nitride (AlGaN) layer of the p-type gallium nitride (GaN) / undoped aluminum gallium nitride (AlGaN) superlattice cladding layer is set to 0.10, for example.

  The p-type contact layer 39 is formed of a p-type gallium nitride (GaN) contact layer, and has a thickness of 0.1 μm, for example.

In the epitaxial growth, an n-type cladding layer 31 made of n-type aluminum gallium nitride (AlGaN), which is a layer not containing indium (In), an n-type gallium nitride (GaN) n-type guide layer 32, and an undoped aluminum gallium nitride (AlGaN). An undoped guide layer 34 made of p-type, an electron barrier layer 36 made of p-type aluminum gallium nitride (AlGaN), a cladding layer 38 made of p-type GaN / undoped aluminum gallium nitride (AlGaN), and p-type gallium nitride (GaN). The growth temperature of the p-type contact layer 39 is, for example, about 1000 ° C. An active layer 34 having an indium (In) -containing layer of gallium indium nitride (Ga _1-x In _x N) / gallium indium nitride (Ga _1-y In _y N) multiple quantum well structure and undoped gallium indium nitride (InGaN) The growth temperature of the optical waveguide layer 35 made of, for example, was 700 ° C. to 800 ° C., for example, 730 ° C. The above-mentioned epitaxial growth temperature is an example, and is appropriately selected depending on the epitaxial growth apparatus, the source gas, etc., the pressure of the growth atmosphere, the source gas concentration, and the like.

Next, as shown in FIG. 18B, after the insulating film 61 is formed on the compound semiconductor layer 12, the insulating film 61 is patterned by a normal lithography technique and an etching technique to form a first groove portion. An opening 62 is formed in the insulating film 61 on the region to be formed. For the insulating film 61, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 61 is etched by dry etching such as reactive ion etching (RIE).
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.

  Next, as shown in FIG. 18 (3), the p-type contact layer 39 (see FIG. 3) and the p-type cladding layer 38 (see FIG. 3) are etched using the insulating film 61 as an etching mask. As a result, for example, two first groove portions 13 are formed in parallel above the compound semiconductor layer 12 (above the p-type contact layer 39 and the p-type cladding layer 38). As a result, a ridge-shaped first stripe portion 14 is formed between the first groove portions 13. That is, the first groove portion 13 is formed on both sides of the first stripe portion 14.

  The width of the first groove 13 is, for example, 4.25 μm. The width of the first stripe portion 14 is, for example, 1.5 μm to 2 μm.

  Thereafter, the insulating film 61 is removed by wet etching, for example. Note that FIG. 18C shows a state immediately before the insulating film 61 is removed.

  Next, as shown in FIG. 19 (4), an insulating film 51 is formed on the inner surface of the first groove 13 and the surface of the compound semiconductor layer 12. Hereinafter, the insulating film 61 will be described including the insulating film 51. The insulating film 51 is formed of, for example, a silicon oxide film. Further, although not shown, an undoped silicon film is formed on the insulating film 51.

  Next, as shown in FIG. 19 (5), the insulating film on the first stripe portion 14 is formed by forming a resist mask (not shown) by a normal lithography technique and etching using the resist mask. 51 and the silicon film are removed. Then, the upper surface of the first stripe portion 14 is exposed. The upper surface of the first stripe portion 14 is the surface of the p-type contact portion 39 (see FIG. 3). For example, the etching is performed by wet etching using hydrofluoric acid. The resist used as a mask was stripped using a general resist stripping solution such as acetone.

  Next, as shown in FIG. 19 (6), a p-side electrode 41 is formed on the upper surface of the first stripe portion 14 and the surface of an undoped silicon film (not shown) formed on the insulating film 51. The p-side electrode 41 is formed of, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer from the compound semiconductor layer 12 side, for example.

  Next, the semiconductor substrate 11 is formed to a predetermined thickness by polishing the semiconductor substrate 11 from the back surface (second surface S2) side as necessary.

Next, as shown in FIG. 20 (7), after the insulating film 63 is formed on the back surface (second surface S2) of the semiconductor substrate 11, the insulating film 63 is patterned by a normal lithography technique and an etching technique. Then, an opening 64 is formed in the insulating film 63 on the region where the second groove is to be formed. For the insulating film 63, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 63 is etched by dry etching such as reactive ion etching (RIE).
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.

Next, as shown in FIG. 20 (8), the second surface S 2 side of the semiconductor substrate 11 is etched by using the insulating film 63 as an etching mask to etch the second surface S 2 side of the semiconductor substrate 11. For example, two two groove portions 15 are formed in parallel. In this etching, for example, dry etching is used. As this dry etching, for example, reactive ion etching is used.
As a result, a ridge-shaped second stripe portion 16 is formed between the second groove portions 15. That is, the first groove portion 15 is formed on both sides of the second stripe portion 16. The second stripe portion 16 is formed at a position facing the first stripe portion 14. The second groove 15 is also formed at a position facing the first groove 13.

The width of the second groove 15 is, for example, 4.25 μm, and the depth is, for example, 0.5 μm. The depth of the second groove 15 may be at least 0.1 μm, for example. The width of the second stripe portion 16 is, for example, 1.5 μm to 2 μm.
The first groove portion 13, the first stripe portion 14, the second groove portion 15, and the second stripe portion 16 are all formed such that the longitudinal direction extends between the end faces of the semiconductor light emitting device. The number of the second stripe portions 16 may be plural, but it is always necessary that the second stripe portions 16 be formed at a position facing the first stripe portion 14 across the semiconductor substrate 11. .
In order to effectively relieve stress, it is preferable to form the first groove portion 13 and the second groove portion 15 in the same shape, and similarly, the first stripe portion 14 and the second stripe portion 16 have the same shape. It is preferable to form.
The width Ws2 and height of the second stripe portion 16 and the width Wd2 and depth of the second groove portion 15 are appropriately adjusted according to the amount of stress relaxation.

  Thereafter, the insulating film 63 is performed by wet etching using, for example, hydrofluoric acid. The resist used as a mask was stripped using a general resist stripping solution such as acetone. Note that FIG. 18 (3) shows a state immediately before the insulating film 63 is removed.

Next, as shown in FIG. 20 (9), an n-side electrode 42 is formed on the second surface S 2 of the semiconductor substrate 11 including the inner surface of the second groove 15. The n-side electrode 42 is formed of, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the second surface S2 side of the semiconductor substrate 11, for example. The n-side electrode 42 is formed by, for example, a chemical vapor deposition (CVD) method, a sputtering method, a vapor deposition method, or the like.
Thus, the semiconductor light emitting device 1 which is the gallium nitride (GaN) semiconductor laser device described with reference to FIG. 1 and the like is manufactured.

  In the manufacturing method of the semiconductor light emitting device according to the first embodiment, the ridge-shaped second stripe is formed at a position facing the first stripe portion 14 on the second surface S2 side opposite to the first surface S1 of the semiconductor substrate 11. Since the second groove portion 15 is formed on both sides of the portion 16 and the second stripe portion 16, the stress generated between the semiconductor substrate 11 and the compound semiconductor layer 12 is relieved, and the first stripe portion 14 and the second stripe portion The stress between the parts 16 is relieved. As a result, stress on the resonance surface is relieved, so that there is an advantage that the semiconductor light emitting device 1 having a long lifetime and high reliability can be manufactured.

  Next, an embodiment (second embodiment) according to a method for manufacturing a semiconductor light emitting device of the present invention will be described with reference to schematic sectional views of FIGS. 21 to 23 show an example of a second semiconductor light emitting device corresponding to claims 7 and 9.

  As shown in FIG. 21A, a semiconductor substrate 11 is used. For example, a compound semiconductor substrate is used as the semiconductor substrate 11. For example, an n-type gallium nitride (GaN) substrate is used as the compound semiconductor substrate.

A compound semiconductor layer (hereinafter referred to as a first compound semiconductor layer) 12 is formed on the first surface S1 of the semiconductor substrate 11.
The first compound semiconductor layer 12 is formed from the semiconductor substrate 11 side by, for example, an epitaxial growth method, for example, by an epitaxial growth method, from the semiconductor substrate 11 side, an n-type cladding layer 31, an n-type guide layer 32, an active layer 33, an undoped guide. The layer 34, the optical waveguide layer 35, the p-type electron barrier layer 36, the p-type guide layer 37, the p-type cladding layer 38, and the p-type contact layer 39 are sequentially stacked.

  N-type cladding layer 31, n-type guide layer 32, active layer 33, undoped guide layer 34, optical waveguide layer 35, p-type electron barrier layer 36, p-type guide layer 37, p-type cladding Details of each material and manufacturing method of the layer 38 and the p-type contact layer 39 are the same as those described in the first embodiment of the manufacturing method of the semiconductor light emitting device.

  A second compound semiconductor layer 17 is formed on the second surface S2 of the semiconductor substrate 11 opposite to the first surface S1. The second compound semiconductor layer 17 is formed of, for example, an n-type aluminum gallium nitride (AlGaN) similar to the n-type clad layer 31 formed thickest in the first compound semiconductor layer 12 by, for example, an epitaxial growth method. Has been. Alternatively, it is made of n-type gallium nitride (GaN) similar to the n-type guide layer 32 formed near the first surface S1 on the semiconductor substrate 11 side.

Next, as shown in FIG. 21B, after forming an insulating film 61 on the compound semiconductor layer 12, the insulating film 61 is patterned by a normal lithography technique and etching technique to form a first groove portion. An opening 62 is formed in the insulating film 61 on the region to be formed. For the insulating film 61, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 61 is etched by dry etching such as reactive ion etching (RIE).
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.

  Next, as shown in FIG. 21 (3), the p-type contact layer 39 and the p-type cladding layer 38 are etched using the insulating film 61 as an etching mask, so that the upper part (p For example, two first groove portions 13 are formed in parallel in the upper part of the type contact layer 39 and the p-type cladding layer 38. As a result, a ridge-shaped first stripe portion 14 is formed between the first groove portions 13. That is, the first groove portion 13 is formed on both sides of the first stripe portion 14.

  The width of the first groove 13 is, for example, 4.25 μm. The width of the first stripe portion 14 is, for example, 1.5 μm to 2 μm.

  Thereafter, the insulating film 61 is removed by wet etching, for example. Note that FIG. 21 (3) shows a state immediately before the insulating film 61 is removed.

  Next, as shown in FIG. 22 (4), an insulating film 51 is formed on the inner surface of the first groove 13 and the surface of the compound semiconductor layer 12. Hereinafter, the insulating film 61 will be described including the insulating film 51. The insulating film 51 is formed of, for example, a silicon oxide film. Further, although not shown, an undoped silicon film is formed on the insulating film 51.

  Next, as shown in FIG. 22 (5), the insulating film on the first stripe portion 14 is formed by forming a resist mask (not shown) by a normal lithography technique and etching using the resist mask. 51 and the silicon film are removed. Then, the upper surface of the first stripe portion 14 is exposed. The upper surface of the first stripe portion 14 is the surface of the p-type contact portion 39 (see FIG. 3). For example, the etching is performed by wet etching using hydrofluoric acid. The resist used as a mask was stripped using a general resist stripping solution such as acetone.

  Next, as shown in FIG. 22 (6), the p-side electrode 41 is formed on the upper surface of the first stripe portion 14 and the surface of the undoped silicon film (not shown) formed on the insulating film 51. The p-side electrode 41 is formed of, for example, a laminated film of a nickel (Ni) layer and a gold (Au) layer from the compound semiconductor layer 12 side, for example.

Next, as shown in FIG. 23 (7), after the insulating film 63 is formed on the second compound semiconductor layer 17, the insulating film 63 is patterned by a normal lithography technique and an etching technique to form a second groove portion. An opening 64 is formed in the insulating film 63 on the region where the film is to be formed. For the insulating film 63, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 63 is etched by dry etching such as reactive ion etching (RIE).
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.

Next, as shown in FIG. 23 (8), the second compound semiconductor layer 17 is etched in parallel with the second compound semiconductor layer 17 by etching the second compound semiconductor layer 17 using the insulating film 61 as an etching mask. For example, two are formed. At this time, etching is performed, for example, by adjusting the etching time so that the second groove portion 15 does not reach the semiconductor substrate 11. In addition, the second compound semiconductor layer 17 is formed to a thickness greater than the depth of the second groove portion 15. In this etching, for example, wet etching is used. As this dry etching, for example, reactive ion etching is used.
As a result, a ridge-shaped second stripe portion 16 is formed between the second groove portions 15. That is, the first groove portion 15 is formed on both sides of the second stripe portion 16. The second stripe portion 16 is formed at a position facing the first stripe portion 14. The second groove 15 is also formed at a position facing the first groove 13.

The width of the second groove 15 is, for example, 4.25 μm, and the depth is, for example, 0.5 μm. The depth of the second groove 15 may be at least 0.1 μm, for example. The width of the second stripe portion 16 is, for example, 1.5 μm to 2 μm.
The first groove portion 13, the first stripe portion 14, the second groove portion 15, and the second stripe portion 16 are all formed so that the longitudinal direction extends between the end faces of the semiconductor light emitting device 1. In addition, the number of the second stripe portions 16 may be plural, but one of the second stripe portions 16 is always located at a position facing the first stripe portion 14 across the semiconductor substrate 11. The book needs to be formed.
In order to effectively relieve stress, it is preferable to form the first groove portion 13 and the second groove portion 15 in the same shape, and similarly, the first stripe portion 14 and the second stripe portion 16 have the same shape. It is preferable to form.
The width Ws2 and height of the second stripe portion 16 and the width Wd2 and depth of the second groove portion 15 are appropriately adjusted according to the amount of stress relaxation.

  Thereafter, the insulating film 63 is performed by wet etching using, for example, hydrofluoric acid. Note that FIG. 213) shows a state immediately before the insulating film 63 is removed.

Next, as shown in FIG. 23 (9), the n-side electrode 42 is formed on the second compound semiconductor layer 17 including the inner surface of the second groove 15. The n-side electrode 42 is formed of, for example, a stacked film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the second compound semiconductor layer 17 side, for example. The n-side electrode 42 is formed by, for example, a chemical vapor deposition (CVD) method, a sputtering method, a vapor deposition method, or the like.
Thus, the semiconductor light emitting device 2 which is the gallium nitride (GaN) semiconductor laser device described with reference to FIG. 5 and the like is manufactured.

  In the manufacturing method according to the second embodiment of the semiconductor light emitting device, the second compound semiconductor layer 17 formed on the second surface S2 side of the semiconductor substrate 11 has a ridge-shaped second stripe at a position facing the first stripe portion. The second groove portion 15 is formed on both sides of the portion 16 and the second stripe portion 16. Thereby, the stress generated between the semiconductor substrate 11 and the compound semiconductor layer 12 is relaxed, and the stress between the first stripe portion 14 and the second stripe portion 16 is relaxed. Therefore, since the stress on the resonance surface is relieved, there is an advantage that the semiconductor light emitting device 2 having a long lifetime and high reliability can be manufactured.

  Next, an embodiment (third embodiment) according to a method for manufacturing a semiconductor light emitting device of the present invention will be described with reference to a schematic cross-sectional view of FIG. FIG. 24 shows an example of a second semiconductor light emitting device corresponding to claims 10 and 11.

As shown in FIG. 24 (1), the compound semiconductor layer 12 is formed on the first surface S 1 side of the semiconductor substrate 11, and the stripe portion 18 is formed above the compound semiconductor layer 12. Further, a p-side electrode 41 connected on the upper surface of the stripe portion 18 is formed between the compound semiconductor layer 12 and an insulating film 51.
After the insulating film 67 is formed on the back surface (second surface S2) of the semiconductor substrate 11 as described above, the insulating film 67 is patterned by a normal lithography technique and an etching technique to form a second groove portion. An opening 68 is formed in the insulating film 67. For the insulating film 67, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 67 is etched by, for example, dry etching such as reactive ion etching (RIE).

Next, as shown in FIG. 24B, by using the insulating film 67 as an etching mask, the second surface S2 side of the semiconductor substrate 11 is etched to form a groove portion in the second surface S2 of the semiconductor substrate 11. 19 is formed. In this etching, for example, dry etching is used. As this dry etching, for example, reactive ion etching is used.
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.
The groove portion 19 is formed at a position facing the stripe portion 18.

The width of the groove 19 is, for example, 1.5 μm, and the depth is, for example, 0.5 μm. The depth of the groove 19 may be at least 0.1 μm, for example. The width of the stripe portion 18 is, for example, 1.5 μm to 2 μm.
Both the stripe portion 18 and the groove portion 19 are formed such that the longitudinal direction extends between the end faces of the semiconductor light emitting device. Further, the number of the groove portions 19 may be plural, but it is always necessary to be formed at a position facing the stripe portion 18 across the semiconductor substrate 11.
In order to effectively relieve the stress, it is preferable to form the stripe portions 18 and the groove portions 19 with the same width.
The width, depth, and the like of the groove 19 are appropriately adjusted according to the amount of stress relaxation.

  Thereafter, the insulating film 67 is removed by wet etching using, for example, hydrofluoric acid. Note that FIG. 24B shows a state immediately before the insulating film 67 is removed.

Next, as shown in FIG. 24 (3), an n-side electrode 42 is formed on the second surface S 2 of the semiconductor substrate 11 including the inner surface of the groove 19. The n-side electrode 42 is formed of, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the second surface S2 side of the semiconductor substrate 11, for example. The n-side electrode 42 is formed by, for example, a chemical vapor deposition (CVD) method, a sputtering method, a vapor deposition method, or the like.
Thus, the semiconductor light emitting device 3 which is the gallium nitride (GaN) semiconductor laser device described with reference to FIG. 9 and the like is manufactured.

  In the manufacturing method of the third embodiment, since the groove portion 19 is formed at a position facing the stripe portion 18 on the second surface S2 side of the semiconductor substrate 11, it is generated between the semiconductor substrate 11 and the compound semiconductor layer 12. The stress between the stripe portion 18 and the groove portion 19 is relaxed. As a result, stress on the resonance surface is relieved, so that there is an advantage that the semiconductor light emitting device 3 having a long lifetime and high reliability can be manufactured.

  Next, an embodiment (fourth embodiment) according to a method for manufacturing a semiconductor light emitting device of the present invention will be described with reference to a schematic cross-sectional view of FIG. FIG. 25 shows an example of a second semiconductor light emitting device corresponding to claims 10 and 11.

As shown in FIG. 25 (1), a compound semiconductor layer (hereinafter referred to as a first compound semiconductor layer) 12 is formed on the first surface S 1 side of the semiconductor substrate 11, and stripes are formed above the first compound semiconductor layer 12. A portion 18 is formed. Further, a p-side electrode 41 connected on the upper surface of the stripe portion 18 is formed between the first compound semiconductor layer 12 and an insulating film 51.
A second compound semiconductor layer 17 is formed on the second surface S2 side of the semiconductor substrate 11.
After the insulating film 67 is formed on the second compound semiconductor layer 17, the insulating film 67 is patterned by a normal lithography technique and an etching technique, and an opening is formed in the insulating film 67 on the region where the second groove is to be formed. 68 is formed. For the insulating film 67, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 67 is etched by, for example, dry etching such as reactive ion etching (RIE).

Next, as shown in FIG. 25 (2), the second compound semiconductor layer 17 is etched using the insulating film 67 as an etching mask, thereby forming a groove portion 19 in the second compound semiconductor layer 17. In this etching, for example, dry etching is used. As this dry etching, for example, reactive ion etching is used.
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.
The groove portion 19 is formed at a position facing the stripe portion 18.

The width of the groove 19 is, for example, 1.5 μm, and the depth is, for example, 0.5 μm. The depth of the groove 19 may be at least 0.1 μm, for example. The width of the stripe portion 18 is, for example, 1.5 μm to 2 μm.
Both the stripe portion 18 and the groove portion 19 are formed so that the longitudinal direction extends between the end faces of the semiconductor light emitting device 3. Further, the number of the groove portions 19 may be plural, but it is always necessary to be formed at a position facing the stripe portion 18 across the semiconductor substrate 11.
In order to effectively relieve the stress, it is preferable to form the stripe portion 18 and the groove portion 19 in the same width.
The width Wd2, depth, and the like of the groove portion 19 are appropriately adjusted depending on the amount of stress relaxation.

  Thereafter, the insulating film 67 is removed by wet etching using, for example, hydrofluoric acid. Note that FIG. 25 (2) shows a state immediately before the insulating film 67 is removed.

Next, as shown in FIG. 25 (3), the n-side electrode 42 is formed on the second surface S 2 of the semiconductor substrate 11 including the inner surface of the groove 19. The n-side electrode 42 is formed of, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the second surface S2 side of the semiconductor substrate 11, for example. The n-side electrode 42 is formed by, for example, a chemical vapor deposition (CVD) method, a sputtering method, a vapor deposition method, or the like.
Thus, the semiconductor light emitting device 4 which is the gallium nitride (GaN) semiconductor laser device described with reference to FIG. 11 and the like is manufactured.

  In the manufacturing method of the fourth embodiment, the groove portion 19 is formed at a position facing the stripe portion 18 on the second surface S2 side of the semiconductor substrate 11, and therefore, it is generated between the semiconductor substrate 11 and the compound semiconductor layer 12. The stress between the stripe portion 18 and the groove portion 19 is relaxed. As a result, stress on the resonance surface is relieved, so that there is an advantage that the semiconductor light emitting device 3 having a long lifetime and high reliability can be manufactured.

  Next, an embodiment (fifth embodiment) according to a method for manufacturing a semiconductor light-emitting device of the present invention will be described with reference to a schematic cross-sectional view of FIG. FIG. 24 shows an example of a second semiconductor light emitting device corresponding to claims 10 and 12.

As shown in FIG. 26 (1), the compound semiconductor layer 12 is formed on the first surface S 1 side of the semiconductor substrate 11, and a stripe portion (hereinafter referred to as a first scribe portion) 18 is formed above the compound semiconductor layer 12. Is formed. Further, a p-side electrode 41 connected on the upper surface of the first scribe portion 18 is formed between the compound semiconductor layer 12 and an insulating film 51.
After the insulating film 69 is formed on the back surface (second surface S2) of the semiconductor substrate 11 as described above, the insulating film 69 is patterned by a normal lithography technique and an etching technique to form a second stripe portion. The insulating film 69 is left. For the insulating film 69, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 69 is etched by, for example, dry etching such as reactive ion etching (RIE).

Next, as shown in FIG. 26 (2), the second surface S 2 side of the semiconductor substrate 11 is etched by using the insulating film 69 as an etching mask, so that the second surface S 2 of the semiconductor substrate 11 is etched. Two stripe portions 20 are formed. In this etching, for example, dry etching is used. As this dry etching, for example, reactive ion etching is used.
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.
The second stripe portion 20 is formed at a position facing the first stripe portion 18.

The width of the second stripe part 20 is, for example, 1.5 μm, and the height is, for example, 0.5 μm. The height of the second stripe portion 20 may be at least 0.1 μm, for example. The width of the first stripe portion 18 is, for example, 1.5 μm to 2 μm.
The first stripe portion 18 and the second stripe portion 20 are both formed so that the longitudinal direction extends between the end faces of the semiconductor light emitting device. In addition, the number of the second stripe portions 20 may be plural, but the second stripe portions 20 must always be formed at a position facing the first stripe portion 18 across the semiconductor substrate 11. .
In order to relieve stress effectively, it is preferable to form the first stripe portion 18 and the second stripe portion 20 with the same width.
The width, height, and the like of the second stripe portion 20 are appropriately adjusted according to the amount of stress relaxation.

  Thereafter, the insulating film 69 is removed by wet etching using, for example, hydrofluoric acid. Note that FIG. 26B shows a state immediately before the insulating film 69 is removed.

Next, as shown in FIG. 26 (3), an n-side electrode 42 is formed on the second surface S 2 of the semiconductor substrate 11 including the surface of the second stripe portion 20. The n-side electrode 42 is formed of, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the second surface S2 side of the semiconductor substrate 11, for example. The n-side electrode 42 is formed by, for example, a chemical vapor deposition (CVD) method, a sputtering method, a vapor deposition method, or the like.
As described above, the semiconductor light emitting device 5 which is the gallium nitride (GaN) semiconductor laser device described with reference to FIG. 9 and the like is manufactured.

  In the manufacturing method of the fifth embodiment, since the second stripe portion 20 is formed at a position facing the first stripe portion 18 on the second surface S2 side of the semiconductor substrate 11, the semiconductor substrate 11 and the compound semiconductor layer 12 are formed. The stress generated between the first stripe portion 18 and the second stripe portion 20 is relaxed. As a result, stress on the resonance surface is relieved, so that there is an advantage that the semiconductor light emitting device 5 having a long lifetime and high reliability can be manufactured.

  Next, an embodiment (sixth embodiment) according to a method for manufacturing a semiconductor light emitting device of the present invention will be described with reference to a schematic cross-sectional view of FIG. FIG. 27 shows an example of a second semiconductor light emitting device corresponding to claims 10 and 12.

As shown in FIG. 27 (1), a compound semiconductor layer (hereinafter referred to as a first compound semiconductor layer) 12 is formed on the first surface S 1 side of the semiconductor substrate 11, and stripes are formed above the first compound semiconductor layer 12. A portion (hereinafter referred to as a first stripe portion) 18 is formed. Further, a p-side electrode 41 connected on the upper surface of the stripe portion 18 is formed between the first compound semiconductor layer 12 and an insulating film 51.
A second compound semiconductor layer 17 is formed on the second surface S2 side of the semiconductor substrate 11.
After the insulating film 69 is formed on the second compound semiconductor layer 17, the insulating film 69 is patterned by a normal lithography technique and an etching technique to leave the insulating film 69 on the region where the second stripe portion is to be formed. . For the insulating film 69, for example, zirconium oxide, silicon oxide or the like is used. The insulating film 69 is etched by, for example, dry etching such as reactive ion etching (RIE).

Next, as shown in FIG. 27B, the second compound semiconductor layer 17 is etched by using the insulating film 69 as an etching mask, so that the second stripe portion 20 is formed in the second compound semiconductor layer 17. Form. In this etching, for example, dry etching is used. As this dry etching, for example, reactive ion etching is used.
As the reactive ion etching conditions, chlorine was used as the etching gas, the flow rate was set to 30 cm ³ / min, the pressure in the etching atmosphere was set to 0.5 Pa, and the power of the etching apparatus was set to 300 W. In addition, it can also form by ion milling and laser processing instead of the said dry etching.
The second stripe portion 20 is formed at a position facing the first stripe portion 18.

The width of the second stripe part 20 is, for example, 1.5 μm, and the height is, for example, 0.5 μm. The height of the second stripe portion 20 may be at least 0.1 μm, for example. The width of the first stripe portion 18 is, for example, 1.5 μm to 2 μm.
The first stripe portion 18 and the second stripe portion 20 are both formed such that the longitudinal direction extends between the end faces of the semiconductor light emitting device 6. In addition, the number of the second stripe portions 20 may be plural, but the second stripe portions 20 must always be formed at a position facing the first stripe portion 18 across the semiconductor substrate 11. .
In order to relieve stress effectively, it is preferable to form the first stripe portion 18 and the second stripe portion 20 with the same width.
The width, height, and the like of the second stripe portion 20 are appropriately adjusted according to the amount of stress relaxation.

  Thereafter, the insulating film 69 is removed by wet etching using, for example, hydrofluoric acid. Note that FIG. 27B shows a state immediately before the insulating film 69 is removed.

Next, as shown in FIG. 27 (3), an n-side electrode 42 is formed on the second surface S 2 of the semiconductor substrate 11 including the surface of the second stripe portion 20. The n-side electrode 42 is formed of, for example, a laminated film of a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer from the second surface S2 side of the semiconductor substrate 11, for example. The n-side electrode 42 is formed by, for example, a chemical vapor deposition (CVD) method, a sputtering method, a vapor deposition method, or the like.
Thus, the semiconductor light emitting device 6 which is the gallium nitride (GaN) semiconductor laser device described with reference to FIG. 15 and the like is manufactured.

  In the manufacturing method of the sixth embodiment, since the second stripe portion 20 is formed at a position facing the first stripe portion 18 on the second surface S2 side of the semiconductor substrate 11, the semiconductor substrate 11 and the compound semiconductor layer 12 are formed. The stress generated between the first stripe portion 18 and the second stripe portion 20 is relaxed. As a result, the stress on the resonance surface is relieved, and thus there is an advantage that a highly reliable semiconductor light emitting device 6 having a long lifetime can be manufactured.

In addition, in the manufacturing method of each of the above embodiments, a cleavage plane serving as a resonance surface of each semiconductor light emitting device is formed with good reproducibility when a plurality of semiconductor light emitting devices are formed on a wafer and cut into each semiconductor light emitting device. Will be able to.
In addition, the general resist stripping solution is used for the removal of the resist mask (not shown) used with the lithography technique in each said manufacturing method.

BRIEF DESCRIPTION OF THE DRAWINGS It is drawing which showed one Embodiment (1st Embodiment) which concerns on the semiconductor light-emitting device of this invention, (1) A figure is a typical perspective view, (2) A figure is typical sectional drawing. It is a schematic structure sectional view showing a compound semiconductor layer and a first stripe part. It is the expanded partial sectional view which showed the compound semiconductor layer and the 1st stripe part. It is drawing which showed description of the stress relaxation in the semiconductor light-emitting device 1, (1) A figure is a typical perspective view of a wafer state, (2) A figure is typical sectional drawing, (3) A figure is a comparative example FIG. It is drawing which showed one Embodiment (2nd Embodiment) which concerns on the semiconductor light-emitting device of this invention, (1) A figure is a typical perspective view, (2) A figure is typical sectional drawing. It is typical sectional drawing which showed the compound semiconductor layer and the 1st stripe part. 3 is a schematic perspective view illustrating an explanation of stress relaxation in the semiconductor light emitting device 2. FIG. It is the typical sectional view showing the details of the p side electrode and the n side electrode. It is drawing which showed one Embodiment (3rd Embodiment) which concerns on the semiconductor light-emitting device of this invention, (1) A figure is a typical perspective view, (2) A figure is typical sectional drawing. It is drawing which showed description of the stress relaxation in the semiconductor light-emitting device 3, (1) A figure is a typical perspective view of a wafer state, (2) A figure is typical sectional drawing, (3) A figure is a comparative example FIG. It is drawing which showed one Embodiment (4th Embodiment) which concerns on the semiconductor light-emitting device of this invention, (1) A figure is a typical perspective view, (2) A figure is typical sectional drawing. It is drawing explaining the stress relaxation in a semiconductor light-emitting device, (1) A figure is a typical perspective view of a wafer state, (2) A figure is typical sectional drawing, (3) A figure is a schematic of a comparative example It is sectional drawing. It is drawing which showed one Embodiment (5th Embodiment) which concerns on the semiconductor light-emitting device of this invention, (1) A figure is a typical perspective view, (2) A figure is typical sectional drawing. It is drawing explaining the stress relaxation in a semiconductor light-emitting device, (1) A figure is a typical perspective view of a wafer state, (2) A figure is typical sectional drawing. It is drawing which showed one Embodiment (6th Embodiment) which concerns on the semiconductor light-emitting device of this invention, (1) A figure is a typical perspective view, (2) A figure is typical sectional drawing. 3 is a schematic perspective view for explaining stress relaxation in the semiconductor light emitting device 6. FIG. It is typical sectional drawing of a comparative example. It is typical sectional drawing which showed one Embodiment (1st Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (1st Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (1st Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (2nd Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (2nd Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (2nd Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (3rd Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (4th Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (5th Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention. It is typical sectional drawing which showed one Embodiment (6th Embodiment) which concerns on the manufacturing method of the semiconductor light-emitting device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 11 ... Semiconductor substrate, 12 ... Compound semiconductor layer, 14 ... 1st stripe part, 15 ... 2nd groove part, 16 ... 2nd stripe part, 21 ... Resonance surface, 22 ... Resonance surface, S1 ... 1st 1 side, S2 ... 2nd side

Claims (12)

A semiconductor substrate;
A compound semiconductor layer formed on the first surface of the semiconductor substrate;
A ridge-shaped first stripe portion formed on an upper portion of the compound semiconductor layer;
A resonance surface formed opposite to and formed in a cross-sectional direction perpendicular to the length direction of the first stripe portion;
A ridge-shaped second stripe portion formed at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate;
A semiconductor light emitting device having a groove formed on both sides of the second stripe portion on the second surface side of the semiconductor substrate. The semiconductor light emitting device according to claim 1, wherein the groove portion and the second stripe portion are formed in the semiconductor substrate itself on a second surface side of the semiconductor substrate. The semiconductor light emitting device according to claim 1, wherein the groove portion and the second stripe portion are formed in a compound semiconductor layer formed on a second surface side of the semiconductor substrate. A semiconductor substrate;
A compound semiconductor layer formed on the first surface of the semiconductor substrate;
A ridge-shaped first stripe portion formed on an upper portion of the compound semiconductor layer;
A resonance surface formed opposite to and formed in a cross-sectional direction perpendicular to the length direction of the first stripe portion;
A semiconductor light emitting device comprising: a groove formed at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate; or a ridge-shaped second stripe portion. The semiconductor light emitting device according to claim 4, wherein the groove portion or the second stripe portion is formed in the semiconductor substrate itself on a second surface side of the semiconductor substrate. The semiconductor light emitting device according to claim 4, wherein the groove portion or the second stripe portion is formed in a compound semiconductor layer formed on a second surface side of the semiconductor substrate. Forming a compound semiconductor layer having a ridge-shaped first stripe portion on a first surface of a semiconductor substrate;
Forming a ridge-shaped second stripe portion and grooves on both sides of the second stripe portion at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate; A method for manufacturing a semiconductor light emitting device. The method of manufacturing a semiconductor light emitting device according to claim 7, wherein the second stripe portion and the groove portion are formed in the semiconductor substrate itself on a second surface side of the semiconductor substrate. The method of manufacturing a semiconductor light emitting device according to claim 7, wherein the second stripe portion and the groove portion are formed in the compound semiconductor layer after forming the compound semiconductor layer on the second surface side of the semiconductor substrate. Forming a compound semiconductor layer having a ridge-shaped first stripe portion on a first surface of a semiconductor substrate;
Forming a ridge-shaped second stripe portion or groove portion at a position facing the first stripe portion on the second surface side opposite to the first surface of the semiconductor substrate. Method. The method of manufacturing a semiconductor light emitting device according to claim 10, wherein the second stripe portion or the groove portion is formed in the semiconductor substrate itself on a second surface side of the semiconductor substrate. The method of manufacturing a semiconductor light emitting device according to claim 10, wherein the second stripe portion or the groove portion is formed in the compound semiconductor layer after forming the compound semiconductor layer on the second surface side of the semiconductor substrate.

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