JP2009272879A - Amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit capable of making fine both performances of an amplification factor and noise characteristics. <P>SOLUTION: The amplifier circuit has: an input signal node (IN) for entering an input signal; a first field-effect transistor (TR1) in which the input signal node is connected to a gate; a second field-effect transistor (TR2) which is connected in series to the first field-effect transistor, and in which a first bias voltage node is connected to the gate; and current paths (103, 104, TR3) for making a current flow between a mutual connection point of the first field-effect transistor and the second field-effect transistor, and a first potential node. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an amplifier circuit.

  A low-noise amplifier circuit is an amplifier circuit that amplifies a weak signal received by an antenna and transmits it to the subsequent stage. It suppresses noise generated by the circuit itself as low as possible and amplifies the signal to the maximum. With the goal.

  FIG. 5 is a circuit diagram showing a configuration example of a low noise amplifier circuit. A high-frequency input signal is input to the input signal node IN via the antenna. Independent bias voltages are applied to the bias voltage nodes VG1 and VG2, respectively. A power supply potential (power supply voltage) is applied to the power supply potential node VDD. The quarter wavelength transmission line 101 is connected between the input signal node IN and the bias voltage node VG1. The first field effect transistor TR1 is an n-channel field effect transistor, and has a gate connected to the input signal node IN and a source connected to the reference potential node. The second field effect transistor TR2 is an n-channel field effect transistor, and has a gate connected to the bias voltage node VG2 and a source connected to the drain of the first field effect transistor TR1. The quarter-wave transmission line 102 is connected between the drain of the second field effect transistor TR2 and the power supply potential node VDD. The output signal node OUT is a node for outputting an output signal. The capacitor 111 is connected between the drain of the second field effect transistor TR2 and the output signal node OUT. A bias current i1 flows through the first field effect transistor TR1 and the second field effect transistor TR2.

  In order to improve the amplification performance, the two-stage field effect transistors TR1 and TR2 are vertically stacked, the input signal node IN is connected to the gate of the common source amplifier circuit of the first field effect transistor TR1, and the second An amplified signal is output from the drain of the common-gate amplifier circuit of the field effect transistor TR2. This circuit configuration is called a cascode circuit.

  Patent Document 1 below includes an input terminal to which a high-frequency signal is input, a low noise amplifier to which a signal input to the input terminal is supplied, and an output terminal to which an output of the low noise amplifier is supplied. A power supply circuit for supplying a driving voltage to a power supply terminal of the low noise amplifier, a detection circuit for supplying a power supply circuit output to detect a failure of the low noise amplifier, and a control to which the output of the detection circuit is connected And a bypass circuit provided between the input terminal and the output terminal, and the control unit for selectively inserting the bypass circuit between the input side and the output side of the low noise amplifier A switching circuit connected to the output of the low noise amplifier, and the switching circuit is inserted between the input side of the low noise amplifier and the ground and between the output side of the low noise amplifier and the ground. Together with the high-circumference A line having a length of approximately ¼ with respect to the wavelength of the signal, and a change-over switch connected to each of these lines and connected to the ground on one terminal side thereof, and the bypass The circuit is connected between the other terminal sides of these changeover switches, and when the control unit obtains a signal from the detection circuit that the low noise amplifier has failed, the changeover switch is connected to the other changeover switch. A low-noise amplifier that switches to the terminal side is described.

  In Patent Document 2 below, an input stage transistor that receives an input signal from a signal input terminal, at least two cascode transistors that are cascode-connected to the input stage transistor, and the cascode transistor can be selectively connected. At least two different load circuits, and a control circuit for making the current flowing in the input stage transistor constant while changing the distribution ratio of the current to the load circuit by controlling the cascode transistor, The amplifier is characterized in that the imaginary impedance component of the load circuit is so small that it can be ignored in the input signal band.

  Patent Document 3 below discloses a balanced type in which a single-ended first unit amplifier and a single-ended second unit amplifier are arranged in parallel and driven with a phase difference of approximately 180 degrees and substantially the same amplitude. An amplifier circuit, wherein the output terminal of the last stage semiconductor element in the first unit amplifier is a first node, and the output terminal of the last stage semiconductor element in the second unit amplifier is a second node, A single output terminal of the entire amplifier circuit as a third node, a phase circuit of approximately −90 degrees connected between the first node and the third node, the second node, the third node, A phase circuit of approximately +90 degrees connected between the first node and the second node, and a first inductance component and a second inductance component of approximately the same size connected between the first node and the second node; 1 inductance generation And a bias for supplying a DC bias to the last stage semiconductor element in the first unit amplifier and the last stage semiconductor element in the second unit amplifier. A balanced amplifier circuit comprising a supply terminal is described.

  Further, in Patent Document 4 below, a first transistor whose AC amplitude is input to a gate electrode and a source electrode of a second transistor are connected to a drain electrode of the first transistor, A ground potential for the AC amplitude is connected to the source electrode, a ground potential for the AC amplitude is connected to the gate electrode of the second transistor, a load is connected to the drain electrode of the second transistor, and the AC In a cascode-connected amplifier from which an output related to amplitude is extracted, the amplifier further includes a first impedance element, a second impedance element, and an impedance control circuit, and a first terminal of the first impedance element is the first transistor. And a second terminal of the first impedance element Connected to a first terminal of a second impedance element, a second terminal of the second impedance element is connected to a ground potential with respect to the AC amplitude, and at least one terminal of the second impedance element A third terminal configured is connected to the impedance control circuit, and the impedance control circuit has an external input terminal, and a control signal created based on information input from the external input terminal is transmitted to the third control terminal. There is described a variable gain amplifier circuit characterized in that the variable gain amplifier circuit is supplied to the terminal.

JP 2007-166256 A JP 2007-189568 A JP 2005-143089 A JP 2007-235525 A

  The noise component generated in the amplifier circuit itself includes thermal noise generated by power represented by the product of the bias current and the bias voltage that flows when a bias voltage is applied to the transistor. In order to suppress the generation of the thermal noise, it is effective to reduce the current or voltage. However, if the current or voltage is suppressed too much, the amplification performance of the transistor is also lowered, so that it does not serve as an amplification circuit.

  FIG. 6 is a graph showing an example of measurement results of the amplification factor 601 and noise characteristic 602 of one field effect transistor. The noise characteristic 602 is minimum when the bias current is 8 mA, but the amplification factor 601 is maximum when the bias current is 22 mA. The same problem exists in a low-noise amplifier circuit with a cascode configuration. There is a trade-off relationship between noise suppression and amplification performance (gain) reduction by increasing or decreasing the current applied to the circuit, and it is difficult to improve the performance of both. It is.

  An object of the present invention is to provide an amplifier circuit that can improve the performance of both amplification factor and noise characteristics.

  According to one aspect of the present invention, an input signal node to which an input signal is input, a first field effect transistor having a gate connected to the input signal node, and the first field effect transistor connected in series. A second field effect transistor having a gate connected to a first bias voltage node, and between the first potential node and an interconnection point of the first field effect transistor and the second field effect transistor. There is provided an amplifier circuit having a current path for flowing a current.

  Since the bias current flowing through the first field effect transistor can be made smaller than the bias current flowing through the second field effect transistor, the noise characteristics can be improved without significantly reducing the amplification factor.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration example of a low noise amplifier circuit according to the first embodiment of the present invention. The low noise amplifier circuit is used in, for example, a wireless communication device. A high-frequency input signal (RF signal) is input to the input signal node IN via the antenna. Independent bias voltages are applied to the bias voltage nodes VG1, VG2, and VG3, respectively. A power supply potential (power supply voltage) is applied to the power supply potential node VDD. The quarter wavelength transmission line 101 is connected between the input signal node IN and the bias voltage node VG1. The first field effect transistor TR1 is an n-channel field effect transistor, and has a gate connected to the input signal node IN and a source connected to a reference potential node (ground potential node). The second field effect transistor TR2 is an n-channel field effect transistor, and has a gate connected to the bias voltage node VG2 and a source connected to the drain of the first field effect transistor TR1. The quarter-wave transmission line 102 is connected between the drain of the second field effect transistor TR2 and the power supply potential node VDD. The output signal node OUT is a node for outputting an output signal. The capacitor 111 is connected between the drain of the second field effect transistor TR2 and the output signal node OUT. The third field effect transistor TR3 has a gate connected to the bias voltage node VG3 and a source connected to the reference potential node. The quarter-wave transmission line 103 is connected between the interconnection point of the drain of the first field effect transistor TR1 and the source of the second field effect transistor TR2 and the drain of the third field effect transistor TR3. The The capacitor 112 is connected between the drain of the third field effect transistor TR3 and the reference potential node. A cascode circuit is configured by cascading the first field effect transistor TR1 and the second field effect transistor TR2.

  A bias current i1 flows from the power supply potential node VDD to the second field effect transistor TR2. A bias current i2 flows from the second field effect transistor TR2 to the first field effect transistor TR1. A current i3 flows from the second field effect transistor TR2 to the transmission line 103. Since the current i1 is divided into the currents i2 and i3, i1 = i2 + i3 is established. The current i3 flows to the reference potential node via the third field effect transistor TR3. The transmission line 103 and the third field effect transistor TR3 constitute a current path of the current i3.

  Since the drain of the third field effect transistor TR3 is connected to the reference potential via the capacitor 112, it is grounded in terms of alternating current. By setting the line length of the transmission lines 101 to 103 to a quarter wavelength with respect to the wavelength of the input signal of the input signal node IN, the transmission lines 101 to 103 and later are opened for a high frequency input signal. It becomes invisible. As a result, the third field effect transistor TR3 for flowing the current i3 is the same as that which does not exist for the input signal. The same effect can be obtained even if the quarter-wavelength transmission lines 101 to 103 are replaced with inductors (spiral inductors).

  Since the input signal node IN is connected to the gate of the first field effect transistor TR1, the first field effect transistor TR1 is more influenced by noise characteristics than the second field effect transistor TR2. Therefore, in order to improve the noise characteristic 602 (FIG. 6), the bias current i2 of the first field effect transistor TR1 is reduced. Further, the second field effect transistor TR2 increases the bias current i1 in order to increase the amplification factor 601 (FIG. 6). The current i3 that is the difference between the bias currents i1 and i2 is shunted to the current path of the transmission line 103 and the third field effect transistor TR3.

  The magnitudes of the currents i1 and i2 can be set by adjusting the bias voltages of the bias voltage nodes VG1 and VG2, or by adjusting the sizes of the field effect transistors TR1 and TR2.

  For example, the noise characteristic 602 can be improved by setting the bias current i2 flowing through the first field effect transistor TR1 to 8 mA. In addition, the amplification factor 601 can be increased by setting the bias current i1 flowing through the second field effect transistor TR2 to 22 mA. In this case, the current i3 flowing through the transmission line 103 is i1-i2 = 14 mA. As a result, it is possible to provide a low-noise amplifier circuit with improved performance in both noise characteristics and amplification factor.

(Second Embodiment)
FIG. 2 is a circuit diagram showing a configuration example of a low noise amplifier circuit according to the second embodiment of the present invention. In the first embodiment, the example in which the three field effect transistors TR1 to TR3 are n-channel field effect transistors has been described, but in the present embodiment, the three field effect transistors TR1 to TR3 are p-channel field effect transistors. An example will be described. Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  The quarter wavelength transmission line 101 is connected between the input signal node IN and the bias voltage node VG1. The first field effect transistor TR1 is a p-channel field effect transistor, and has a gate connected to the input signal node IN and a source connected to the power supply potential node VDD. The second field effect transistor TR2 is a p-channel field effect transistor, and has a gate connected to the bias voltage node VG2 and a source connected to the drain of the first field effect transistor TR1. The quarter-wave transmission line 102 is connected between the drain of the second field effect transistor TR2 and the reference potential node. The capacitor 111 is connected between the drain of the second field effect transistor TR2 and the output signal node OUT. The third field effect transistor TR3 has a gate connected to the bias voltage node VG3 and a source connected to the power supply potential node VDD. The quarter-wave transmission line 103 is connected between the interconnection point of the drain of the first field effect transistor TR1 and the source of the second field effect transistor TR2 and the drain of the third field effect transistor TR3. The The capacitor 112 is connected between the drain of the third field effect transistor TR3 and the reference potential node. A cascode circuit is configured by cascading the first field effect transistor TR1 and the second field effect transistor TR2.

  A bias current i2 flows from the power supply potential node VDD to the first field effect transistor TR1. In the transmission line 103, a current i3 flows from the power supply potential node VDD via the third field effect transistor TR3. A bias current i1 flows from the first field effect transistor TR1 and the transmission line 103 to the second field effect transistor TR2. Since the current i1 is a combined current of the currents i2 and i3, i1 = i2 + i3 is established. The transmission line 103 and the third field effect transistor TR3 constitute a current path of the current i3.

  By setting the line length of the transmission lines 101 to 103 to a quarter wavelength with respect to the wavelength of the input signal of the input signal node IN, the transmission lines 101 to 103 and later are opened for a high frequency input signal. It becomes invisible. As a result, the third field effect transistor TR3 for flowing the current i3 is the same as that which does not exist for the input signal. Even if the quarter-wavelength transmission lines 101 to 103 are replaced with inductors (spiral inductors), the same effect can be obtained.

  Since the input signal node IN is connected to the gate of the first field effect transistor TR1, the first field effect transistor TR1 is more influenced by noise characteristics than the second field effect transistor TR2. Therefore, in order to improve the noise characteristic 602 (FIG. 6), the bias current i2 of the first field effect transistor TR1 is reduced. Further, the second field effect transistor TR2 increases the bias current i1 in order to increase the amplification factor 601 (FIG. 6). The difference current i3 between the bias currents i1 and i2 is merged from the current path of the transmission line 103 and the third field effect transistor TR3.

  For example, the noise characteristic 602 can be improved by setting the bias current i2 flowing through the first field effect transistor TR1 to 8 mA. In addition, the amplification factor 601 can be increased by setting the bias current i1 flowing through the second field effect transistor TR2 to 22 mA. In this case, the current i3 flowing through the transmission line 103 is i1-i2 = 14 mA. As a result, it is possible to provide a low-noise amplifier circuit with improved performance in both noise characteristics and amplification factor.

(Third embodiment)
FIG. 3 is a circuit diagram showing a configuration example of a low noise amplifier circuit according to the third embodiment of the present invention. In this embodiment (FIG. 3), transmission lines 104 and 105 and a capacitor 113 are added to the first embodiment (FIG. 1). Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  The quarter-wave transmission line 104 is connected between the interconnection point of the transmission line 103 and the capacitor 112 and the drain of the third field effect transistor TR3. That is, the transmission lines 103 and 104 are connected in series between the interconnection point of the drain of the first field effect transistor TR1 and the source of the second field effect transistor TR2 and the drain of the third field effect transistor TR3. The The capacitor 113 is connected between the drain of the third field effect transistor TR3 and the output signal node OUT. The capacitor 111 is connected between the drain of the second field effect transistor TR2 and the gate of the third field effect transistor TR3. The quarter wavelength transmission line 105 is connected between the gate of the third field effect transistor TR3 and the bias voltage node VG3.

  As in the first embodiment, the present embodiment is a cascode-type low noise amplifier circuit in which field effect transistors TR1 and TR2 are vertically connected in two stages in order to improve the noise characteristic 602 (FIG. 6). The bias current i2 of the field effect transistor TR1 is reduced. The second field effect transistor TR2 increases the bias current i1 in order to increase the amplification factor 601 (FIG. 6). A current i3 that is the difference between the bias currents i1 and i2 is shunted to the transmission line 103. In order to make this shunt current i3 invisible to the input signal (RF signal), it is connected to the drain of the third field effect transistor TR3 by using the quarter-wavelength transmission lines 103 and 104, and the source is grounded. It is reused as the bias current of the type transistor TR3. Since the third field effect transistor TR3 performs an amplification operation, the total amplification factor of the low-noise amplifier circuit increases. In this low-noise amplifier circuit, in order to make the circuit shunted from the field effect transistors TR1 and TR2 invisible to the input signal (RF signal), the current is shunted by the transmission lines 103 and 104 of the quarter wavelength. The transmission lines 101 to 105 may be replaced with inductors.

  This embodiment can obtain the same effects as those of the first embodiment. Further, in the present embodiment, a common source amplifier circuit which is a third field effect transistor TR3 is added to the first embodiment. The third field effect transistor TR3 performs amplification using the current i3 as a bias current. Thereby, this embodiment can make an amplification factor large compared with 1st Embodiment.

(Fourth embodiment)
FIG. 4 is a circuit diagram showing a configuration example of a low noise amplifier circuit according to the fourth embodiment of the present invention. In the third embodiment, the three field effect transistors TR1 to TR3 are n-channel field effect transistors. However, in the present embodiment, the three field effect transistors TR1 to TR3 are p-channel field effect transistors. An example will be described. In the present embodiment (FIG. 4), transmission lines 104 and 105 and a capacitor 113 are added to the second embodiment (FIG. 2). Hereinafter, the points of the present embodiment different from the second embodiment will be described.

  The quarter-wave transmission line 104 is connected between the interconnection point of the transmission line 103 and the capacitor 112 and the drain of the third field effect transistor TR3. That is, the transmission lines 103 and 104 are connected in series between the interconnection point of the drain of the first field effect transistor TR1 and the source of the second field effect transistor TR2 and the drain of the third field effect transistor TR3. The The capacitor 113 is connected between the drain of the third field effect transistor TR3 and the output signal node OUT. The capacitor 111 is connected between the drain of the second field effect transistor TR2 and the gate of the third field effect transistor TR3. The quarter wavelength transmission line 105 is connected between the gate of the third field effect transistor TR3 and the bias voltage node VG3. The transmission lines 101 to 105 may be replaced with inductors. The operation and effect of this embodiment are the same as those of the third embodiment.

  As described above, in the first to fourth embodiments, in the cascode type low noise amplifier circuit, the bias current i2 of the first field effect transistor TR1 is reduced in order to improve the noise characteristic 602 (FIG. 6). In order to increase the amplification factor 601 (FIG. 6), the bias current i1 of the second field effect transistor TR2 is increased. The current i3 that is the difference between the currents i1 and i2 is shunted to another circuit. However, as in the first and second embodiments, the power efficiency is lowered simply by flowing the difference current i3 to the reference potential node.

  Therefore, in the third and fourth embodiments, the difference current i3 is reused as the bias current of the common source transistor TR3. Since the common source transistor TR3 performs an amplifying operation, the total amplification factor of the low noise amplifier circuit is increased. In the low noise amplifier circuit, in order to make the circuit shunted from the field effect transistors TR1 and TR2 invisible to the input signal (RF signal), the shunt is performed by the quarter-wavelength transmission line 103 (or inductor). Further, in order to flow a bias current to the third field effect transistor TR3, the transmission line 104 (or inductor) is connected to the drain of the third field effect transistor TR3 so that it is not visible to the input signal (RF signal). .

  In the first to fourth embodiments, the bias current i2 of the first field effect transistor TR1 that is most affected by thermal noise is reduced. Although not easily affected by thermal noise, the bias current i1 of the second field effect transistor TR2 is increased in order to increase the amplification factor. The current i3 that is the difference between the currents i1 and i2 is adjusted by flowing it through the shunt circuit. In the third and fourth embodiments, the current i3 flowing in the shunt circuit is used as a bias current for the transistor TR3 of the common-source amplifier circuit arranged in the subsequent stage, so that the power can be effectively used.

  According to the first to fourth embodiments, it is possible to improve the noise characteristics of the circuit without significantly reducing the amplification factor of the cascode circuit. Furthermore, in the third and fourth embodiments, the power utilization efficiency can be improved by reusing the bias current in the subsequent source grounded transistor TR3.

  The low-noise amplifier circuits of the first to fourth embodiments include an input signal node IN to which an input signal is input, a first field effect transistor TR1 to which the input signal node IN is connected to a gate, and a first electric field. A second field effect transistor TR2 connected in series to the effect transistor TR1 and having the gate connected to the first bias voltage node VG2, and an interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 And a current path for flowing a current between the first potential node and the first potential node. The third field effect transistor TR3 may be replaced with a resistor.

  In the third embodiment, the first and second field effect transistors TR1 and TR2 are n-channel field effect transistors. The first potential node is a reference potential node. Furthermore, in the third embodiment, an n-channel field effect in which a drain and a source are connected between an interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 and the first potential node. The third field effect transistor TR3, which is a transistor, the first capacitor 111 connected between the drain of the second field effect transistor TR2 and the gate of the third field effect transistor TR3, and an output signal for outputting an output signal A node OUT, and a second capacitor 113 connected between the drain of the third field effect transistor TR3 and the output signal node OUT.

  In the fourth embodiment, the first and second field effect transistors TR1 and TR2 are p-channel field effect transistors. The first potential node is a power supply potential node. Furthermore, the fourth embodiment is a p-channel field effect in which a drain and a source are connected between an interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 and the first potential node. The third field effect transistor TR3, which is a transistor, the first capacitor 111 connected between the drain of the second field effect transistor TR2 and the gate of the third field effect transistor TR3, and an output signal for outputting an output signal A node OUT, and a second capacitor 113 connected between the drain of the third field effect transistor TR3 and the output signal node OUT.

  In the first embodiment, the first and second field effect transistors TR1 and TR2 are n-channel field effect transistors. The first potential node is a reference potential node. Furthermore, in the first embodiment, the drain and the source are connected between the interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 and the first potential node, and the gate is the second. A third field effect transistor TR3 that is an n-channel field effect transistor connected to the bias voltage node VG3, an output signal node OUT that outputs an output signal, a drain of the second field effect transistor TR2, and an output signal node OUT. A first capacitor 111 is connected in between.

  In the second embodiment, the first and second field effect transistors TR1 and TR2 are p-channel field effect transistors. The first potential node is a power supply potential node. Further, in the second embodiment, the drain and the source are connected between the interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 and the first potential node, and the gate is the second. A third field effect transistor TR3 that is a p-channel field effect transistor connected to the bias voltage node VG3, an output signal node OUT that outputs an output signal, a drain of the second field effect transistor TR2, and an output signal node OUT. And a first capacitor 111 connected therebetween.

  In the first to fourth embodiments, the third field effect transistor TR3 has a drain between the interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 and the first potential node. And the source is connected.

  In the third and fourth embodiments, the first capacitor 111 is connected between the drain of the second field effect transistor TR2 and the gate of the third field effect transistor TR3. The second capacitor 113 is connected between the drain of the third field effect transistor TR3 and the output signal node OUT. The first transmission line 103 and the second transmission line 104 are connected in series between the interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 and the drain of the third field effect transistor TR3. A quarter-wave transmission line to be connected. The third capacitor 112 is connected between the connection point of the first transmission line 103 and the second transmission line 104 and the reference potential node.

  In the first and second embodiments, the gate of the third field effect transistor TR3 is connected to the second bias voltage node VG3. The first capacitor 111 is connected between the drain of the second field effect transistor TR2 and the output signal node OUT. The first transmission line 103 has a quarter wavelength connected between the interconnection point of the first field effect transistor TR1 and the second field effect transistor TR2 and the drain of the third field effect transistor TR3. It is a transmission line. The second capacitor 112 is connected between the drain of the third field effect transistor TR3 and the reference potential node.

  As described above, according to the first to fourth embodiments, the bias current i2 flowing through the first field effect transistor TR1 can be made smaller than the bias current i1 flowing through the second field effect transistor TR2. Noise characteristics can be improved without significantly reducing the amplification factor.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 is a circuit diagram showing a configuration example of a low noise amplifier circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structural example of the low noise amplifier circuit by the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the low noise amplifier circuit by the 3rd Embodiment of this invention. It is a circuit diagram which shows the structural example of the low noise amplifier circuit by the 4th Embodiment of this invention. It is a circuit diagram which shows the structural example of a low noise amplifier circuit. It is a graph which shows the example of an actual measurement result of the amplification factor and noise characteristic of one field effect transistor.

Explanation of symbols

101 to 105 Transmission lines 111 to 113 Capacitance 601 Gain 602 Noise characteristics TR1 to TR3 Field effect transistor IN Input signal node OUT Output signal nodes VG1 to VG3 Bias voltage node

Claims (5)

An input signal node to which the input signal is input; and
A first field effect transistor having a gate connected to the input signal node;
A second field effect transistor connected in series to the first field effect transistor and having a gate connected to a first bias voltage node;
An amplifier circuit comprising: a current path for allowing a current to flow between an interconnection point of the first field effect transistor and the second field effect transistor and a first potential node. The first and second field effect transistors are n-channel field effect transistors;
The first potential node is a reference potential node;
Further, a third electric field which is an n-channel field effect transistor having a drain and a source connected between an interconnection point of the first field effect transistor and the second field effect transistor and the first potential node. An effect transistor;
A first capacitor connected between a drain of the second field effect transistor and a gate of the third field effect transistor;
An output signal node for outputting an output signal; and
2. The amplifier circuit according to claim 1, further comprising a second capacitor connected between the drain of the third field effect transistor and the output signal node. The first and second field effect transistors are p-channel field effect transistors;
The first potential node is a power supply potential node;
Further, a third electric field which is a p-channel field effect transistor having a drain and a source connected between an interconnection point of the first field effect transistor and the second field effect transistor and the first potential node. An effect transistor;
A first capacitor connected between a drain of the second field effect transistor and a gate of the third field effect transistor;
An output signal node for outputting an output signal; and
2. The amplifier circuit according to claim 1, further comprising a second capacitor connected between the drain of the third field effect transistor and the output signal node. The first and second field effect transistors are n-channel field effect transistors;
The first potential node is a reference potential node;
Further, a drain and a source are connected between an interconnection point of the first field effect transistor and the second field effect transistor and the first potential node, and a gate is connected to a second bias voltage node. A third field effect transistor that is an n-channel field effect transistor;
An output signal node for outputting an output signal; and
2. The amplifier circuit according to claim 1, further comprising: a first capacitor connected between a drain of the second field effect transistor and the output signal node. The first and second field effect transistors are p-channel field effect transistors;
The first potential node is a power supply potential node;
Further, a drain and a source are connected between an interconnection point of the first field effect transistor and the second field effect transistor and the first potential node, and a gate is connected to a second bias voltage node. A third field effect transistor that is a p-channel field effect transistor;
An output signal node for outputting an output signal; and
2. The amplifier circuit according to claim 1, further comprising: a first capacitor connected between a drain of the second field effect transistor and the output signal node.

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