JP4896903B2 - amplifier - Google Patents

Description

  The present invention relates to an amplifier having a bypass function, and more particularly, to an amplifier that is reduced in size while improving noise characteristics and loss characteristics.

Adding a bypass function to the amplifier to bypass the input signal of the amplifier to the output side as necessary has been conventionally performed, and various configurations have been proposed (for example, Patent Document 1, Patent Document 2, etc.). reference).
9 and 10 show such conventional circuit configuration examples, and the conventional circuit will be described below with reference to these drawings.
First, the circuit configuration example shown in FIG. 9 will be described. In this conventional circuit, an input matching circuit 25 is provided between the input terminal 21 and the input stage of the amplifier 23, and the output terminal 22 and the amplifier 23 are connected. An output matching circuit 26 is provided between the output stage and the switch element 24 is connected between the input and output stages of the amplifier 23.

In such a configuration, when the amplifier 23 is in the operating state, the amplifier 23 is turned on, while the switch element 24 is turned off. Therefore, in the operational state of the amplifier 23, if the isolation of the switch element 24 in the off state is not sufficiently ensured, capacitive coupling occurs between the input and output of the amplifier 23.
On the other hand, when the bypass function is used, the switch element 24 is turned on and the amplifier 23 is turned off. Therefore, the smaller the passage loss of the switch element 24 in the on state, the better the bypass path characteristics. However, on the other hand, if the input / output impedance of the amplifier 23 in the off state is not sufficiently high, the characteristics of the bypass path will be affected.

Next, the circuit configuration example shown in FIG. 10 will be described. In this conventional circuit, a switch element 36 and an input matching circuit 38 are connected in series between the input terminal 31 and the input stage of the amplifier 33. On the other hand, an output matching circuit 39 and a switch element 37 are connected in series between the output stage of the amplifier 33 and the output terminal 32.
Further, a switch element 34 and a switch element 35 are connected in series between the input terminal 31 and the output terminal 32.

  In such a configuration, when the amplifier 33 is in the operating state, the switch elements 36 and 37 are turned on together with the amplifier 33, while the switch element 34 and the switch element 35 are turned off. Therefore, in the operational state of the amplifier 33, the smaller the passage loss of the switch elements 36 and 37 in the on state, the better the characteristics of the amplification path, but the isolation of the switch elements 34 and 35 in the off state is sufficient. If not secured, capacitive coupling between the input and output of the amplification path will occur.

When the bypass function is used, the smaller the passage loss of the switch elements 34 and 35, the better the characteristics of the bypass path. However, if the isolation of the switch elements 36 and 37 in the off state is not sufficiently ensured, matching is achieved. The impedance of the circuits 38 and 39 affects the characteristics of the bypass path.
JP 2004-194105 A (page 4-8, FIGS. 1 and 2) JP-A-10-84300 (pages 16-28, FIGS. 1 to 65)

  In the conventional circuit as described above, in particular, in the case of the former conventional circuit, since the matching circuits 25 and 26 are included in the bypass path, it is caused by a deviation in impedance on the input / output side. There is a problem that the loss in the bypass path becomes large due to mismatching and the loss of the matching circuits 25 and 26 themselves.

On the other hand, unlike the former conventional circuit, the latter conventional circuit has the advantage that the impedance deviation on the input / output side in the bypass path is small, and that it is difficult to be affected by the impedance of the amplification path, so that the loss is low. Further, the amplification path has an advantage that it is not easily affected by the bypass path. On the other hand, compared with an amplifier that does not provide a bypass path, the amplifier path passes through the switch elements 36 and 37 on the input side and the output side, respectively. Has the disadvantage of becoming larger.
Although the passage loss of the switch element in the on state is small, the influence on the noise characteristics is large even if the loss is particularly small on the input side of the amplifier.
Further, when the latter conventional circuit is constituted by MMIC, there is a problem that the chip area is increased because four or three switch elements are used and a matching circuit is incorporated.

  The present invention has been made in view of the above-described circumstances, and provides an amplifier that can suppress the amplification path to low noise, have a low bypass path loss, and can be easily downsized.

In order to achieve the above object of the present invention, an amplifier according to the present invention comprises:
An amplifier having a bypass circuit that bypasses between the input and output,
The amplifier uses a first amplifying field effect transistor, and the first amplifying field effect transistor allows an input signal to be applied to the source from the outside, and between the source and the ground. A choke inductor is connected in between, and a drain of the first amplification field effect transistor is connected to a source of an amplification path switch field effect transistor as a switching element via a matching circuit, and the amplification path switch field effect is connected. While the transistor drain is enabled for signal output,
The source of the first amplification field effect transistor and the drain of the amplification path switch field effect transistor are connected via a bypass circuit in which a capacitor and a bypass path switch field effect transistor as a switch element are connected in series. And
The first amplifying field effect transistor has a gate that can be externally applied with a bias voltage and is grounded in an alternating manner, while a drain is applied with a power supply voltage via the matching circuit. is there.
In such a configuration, a second amplifying field effect transistor is provided between the drain of the first amplifying field effect transistor and the matching circuit, and the source of the second amplifying field effect transistor is The drain of the first amplifying field effect transistor is connected, the drain of the second amplifying field effect transistor is connected to the matching circuit, and the gate of the second amplifying field effect transistor is A device connected to the gate of the first amplifying field effect transistor is also suitable.

According to the present invention, since the configuration using the grounded-gate amplifier, unlike the conventional case, the gate width and current consumption of the field-effect transistor constituting the grounded-gate amplifier can be appropriately set without using the switch element or matching circuit on the input side. With this setting, the input impedance can be adjusted, and an amplifier having low noise characteristics can be provided.
Also, unlike the conventional case, the bypass path is configured by a switch element that is turned off without passing through the input matching circuit of the amplification path, and is separated from the amplification path, so that the loss is low and compared with the conventional one. Therefore, since the number of switch elements is small, the size can be easily reduced.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 8.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first configuration example according to the embodiment of the present invention will be described with reference to FIG.
The amplifier in the first configuration example includes a first amplification field effect transistor 5, an amplification path switch field effect transistor 6, a bypass path switch field effect transistor 7, a matching circuit 8, a choke inductor 9, The bypass capacitor 10 and the DC cut capacitor 11 are configured as main components.

First, the source of the first amplifying field effect transistor 5 is connected to the input terminal 1 and to one end of the choke inductor 9, and the other end of the choke inductor 9 is connected to the ground. It has become. Note that an input signal (high frequency signal) from the outside is applied to the input terminal 1.
The drain of the first amplification field effect transistor 5 is connected to the source of the amplification path switch field effect transistor 6 via the matching circuit 8, and the drain of the amplification path switch field effect transistor 6 is connected to the output terminal. 2 is connected.

Further, the gate of the first amplifying field effect transistor 5 is connected to the ground via the bypass capacitor 10 and a bias voltage is applied from the outside via the bias application terminal 4.
The source of the bypass path switching field effect transistor 7 is connected to the input terminal 1 via the DC cut capacitor 11, while the drain is connected to the output terminal 2 together with the drain of the amplification path switching field effect transistor 6. It has become.

The power supply voltage necessary for the operation of the first amplification field effect transistor 5, the amplification path switch field effect transistor 6, and the bypass path switch field effect transistor 7 is externally supplied via the power supply voltage terminal 3 and the matching circuit 8. It is to be supplied from.
Further, a necessary bias voltage can be applied to the gates of the amplification path switch field effect transistor 6 and the bypass path switch field effect transistor 7 separately from the outside.
In this configuration, the amplification path through which the high-frequency signal passes through the first amplification field effect transistor 5, the matching circuit 8, and the amplification path switch field effect transistor 6, the DC cut capacitor 11, and the bypass path switch field effect transistor. As will be described below, the bypass path passing through 7 is alternatively formed according to the operating state.

Next, the operation in such a configuration will be described. First, in the case of an amplification operation, it is necessary to put each of the gates of the first amplification field effect transistor 5 and the amplification path switch field effect transistor 6 into an operation state. On the other hand, a predetermined bias voltage necessary to turn off the bypass path switch field effect transistor 7 is applied to the gate of the bypass path switch field effect transistor 7.
In the first amplifying field effect transistor 5, the power supply voltage is applied to the drain via the matching circuit 8, while the source is DC-grounded via the choke inductor 9. Will operate as.

On the other hand, the amplification path switch field effect transistor 6 and the bypass path switch field effect transistor 7 are turned on and off by a bias voltage (switching voltage) applied to their gates by eliminating the potential difference between the source and drain. It operates as a switching element whose state is switched.
Since the first amplifying field effect transistor 5 operates as a grounded-gate amplifier, the first amplifying field effect transistor 5 has a characteristic that the input impedance viewed from the source is low and the output impedance viewed from the drain is high.

  The input impedance of the grounded-gate amplifier can be adjusted by appropriately selecting the gate width and current consumption of the field effect transistor used therefor. Therefore, by adjusting the gate width and current consumption of the first amplification field effect transistor 5 Thus, the characteristic impedance of the input terminal 1 can be brought close to, so that the first circuit configuration example is configured without providing an input matching circuit unlike the prior art.

On the other hand, the output stage is adjusted to the characteristic impedance required at the output terminal 2 by the matching circuit 8, but when the amplification path is in the operating state, the field effect transistor 6 for the amplification path switch is in the ON state. Since it functions as a switching element, the passage loss of the amplification path switching field effect transistor 6 is small and has little influence on matching.
Further, since the bypass path switching field effect transistor 7 is in the OFF state, the capacitive coupling between the input terminal 1 and the output terminal 2 becomes smaller as the isolation is larger, and the characteristic degradation of the amplification path can be further suppressed. It has become.

Next, a case where the bypass path is set in an operating state will be described.
In this case, the bypass path switching field effect transistor 7 is turned on, while the first amplification field switching transistor 5 and the amplification path switching field effect transistor 6 are turned off.
The passage loss as a switching element by the field effect transistor 7 for the bypass path switch in the on state is substantially the passage loss of the entire bypass path. On the other hand, the greater the isolation as the switching element by the first amplification field effect transistor 5 and the amplification path switching field effect transistor 6 in the off state, the smaller the influence of the matching circuit 8 on the impedance of the bypass path becomes. It is possible to reduce degradation of the path characteristics.

  For example, assuming that an input matching circuit is provided in the amplification path, a switch element is provided on the input side of the amplification path in order to isolate the input matching circuit when the bypass path operates. The input matching circuit and the bypass path need to be disconnected. This has the same configuration as that of the conventional circuit shown in FIG. 10, and the noise characteristic when the amplification path operates is deteriorated and the number of elements is increased.

  On the other hand, in the amplifier according to the embodiment of the present invention, the use of a grounded-gate amplifier at the input stage eliminates the need for the input matching circuit and the input side switching element as described above, and improves the noise characteristics. As a result, it has become smaller.

FIG. 2 shows a second configuration example. Hereinafter, an amplifier in the second configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
This second configuration example uses a grounded-gate amplifier composed of a two-stage field effect transistor cascade connection.

That is, the source of the first amplifying field effect transistor 5 is connected to the drain of the second amplifying field effect transistor 5 b, and the source of the second amplifying field effect transistor 5 b is connected via the matching circuit 8. It is connected to the source of the field effect transistor 6 for amplification path switch.
The gate of the first amplifying field effect transistor 5 and the gate of the second amplifying field effect transistor 5b are connected to each other.

In such a configuration, the first amplifying field effect transistor 5 functions as a switch element, and the amplifying operation is mainly performed by the second amplifying field effect transistor 5b.
Since the first amplification field effect transistor 5 operates as a switching element, the input impedance of the amplifier can be adjusted by adjusting the resistance value and the capacitance value thereof. The effect transistor 5 serves as a matching circuit. Therefore, the first amplifying field effect transistor 5 can be regarded as an impedance adjusting element.
For this reason, the amplifier in the second configuration example can easily bring the input impedance of the amplification path closer to the characteristic impedance at the input terminal 1 as compared with the amplifier in the first configuration example shown in FIG. It has become.
The amplification operation and the bypass operation are basically the same as those in the first configuration example, and thus detailed description thereof is omitted here.

Next, FIGS. 3 to 8 show that the grounded-gate amplifier used in the amplifier according to the embodiment of the present invention is more effective than the grounded-source amplifier and adjusts the input impedance of the grounded-gate amplifier. Various simulation results showing that the gate width is effective are shown, and these figures will be described below.
First, referring to FIG. 3, this figure shows the S11 parameter of a grounded-gate amplifier configured using one field effect transistor and the S11 parameter of a source-grounded amplifier configured using one field effect transistor. The frequency change simulation results are shown on the Smith diagram. In the same figure, the letters “gate grounding” or “source grounding” representing the corresponding amplifier type are shown in the immediate vicinity of each simulation result (the same applies to FIGS. 4 to 6).

  According to this figure, it can be confirmed that the frequency characteristics of the grounded-gate amplifier are smaller than those of the grounded-source amplifier. The simulation is for a field effect transistor having a gate width of 960 μm and a drain current of 3.4 mA.

Next, FIG. 4 is a characteristic diagram showing the result of simulating the change of the S11 parameter with respect to the frequency change of the common-gate amplifier and the common-source amplifier.
In the figure, the horizontal axis represents frequency change, and the vertical axis represents S11 parameter change. The simulation conditions are the same as in the case of FIG.
According to the figure, it can be confirmed that the grounded source amplifier has a very high input impedance compared to the grounded gate amplifier. For this reason, in the common source amplifier, when matching is performed by a matching circuit using a coil or a capacitor, there is a drawback that it is difficult to widen the band due to the originally high frequency characteristics.
On the other hand, in the case of a grounded-gate amplifier, a low NF (noise figure) can be realized in a wide band with matching without using a matching circuit as described above.

FIG. 5 is a Smith diagram showing the simulation result of the frequency change of the S11 parameter when the grounded-gate amplifier has one stage and two stages of field effect transistors. The simulation conditions are the same as in the case of FIG. In FIG. 5, the notation of “grounded gate 1” is a circuit having a single field effect transistor, and the notation of “grounded gate 2” is a circuit having a field effect transistor configured in a two-stage stack. , Each meaning.
According to the figure, it can be confirmed that in any case, the frequency characteristic is smaller than that of the common source amplifier as described in FIG.

FIG. 6 is a characteristic diagram showing the results of simulating changes in the S11 parameter with respect to frequency changes when the grounded-gate amplifier is configured with one stage of field effect transistor and with two stages.
In the figure, the horizontal axis represents frequency change, and the vertical axis represents S11 parameter change. The simulation conditions are the same as in the case of FIG.
According to the figure, it is easier to reduce the input impedance to a desired input impedance (for example, Zs = 50Ω) when the field effect transistor has a two-stage stack than when it has a single stage. I can confirm.

FIG. 7 is a Smith diagram showing the simulation result of the change of the S11 parameter when the gate width Wgt is changed in the grounded-gate amplifier. In the simulation, the drain current of the field effect transistor is 3.4 mA.
FIG. 8 shows characteristic lines representing simulation results for changes in the S11 parameter with respect to frequency changes in various gate widths Wgt in the grounded-gate amplifier. In the figure, the horizontal axis represents frequency change, and the vertical axis represents S11 parameter change.

  According to these figures, it is possible to confirm that the S11 parameter can be lowered as the gate width Wgt is reduced, and thereby the input impedance can be adjusted. However, since the adjustment of the gate width Wgt is a trade-off with NF, it is actually necessary to make a comprehensive decision in consideration of other conditions and select an appropriate value.

It is a block diagram which shows the 1st structural example of the amplifier in embodiment of this invention. It is a block diagram which shows the 2nd structural example of the amplifier in embodiment of this invention. It is a Smith figure showing the simulation result of the change of S11 parameter in a gate ground amplifier and a source ground amplifier. It is a characteristic diagram which shows the simulation result about the change of S11 parameter with respect to the frequency change in a gate ground amplifier and a source ground amplifier. It is a Smith figure showing the simulation result of the frequency change of S11 parameter in the case where the common-gate amplifier has one stage and two stages. It is a characteristic diagram which shows the simulation result about the change of S11 parameter with respect to the frequency change in the case where the grounded-gate amplifier has one field effect transistor and two stages. It is a Smith figure showing the simulation result about the change of S11 parameter at the time of changing the gate width of a field effect transistor in a gate common amplifier. It is a characteristic diagram showing the simulation result about the change of the S11 parameter with respect to the frequency change when the gate width of the field effect transistor is changed in the common-gate amplifier. It is a block diagram which shows the structural example of a conventional circuit. It is a block diagram which shows the other structural example of a conventional circuit.

Explanation of symbols

5 ... first amplification field effect transistor 5b ... second amplification field effect transistor 6 ... amplification path switch field effect transistor 7 ... bypass path switch field effect transistor 8 ... matching circuit

Claims (2)

An amplifier having a bypass circuit that bypasses between the input and output,
The amplifier uses a first amplifying field effect transistor, and the first amplifying field effect transistor allows an input signal to be applied to the source from the outside, and between the source and the ground. A choke inductor is connected in between, and a drain of the first amplification field effect transistor is connected to a source of an amplification path switch field effect transistor as a switching element via a matching circuit, and the amplification path switch field effect is connected. While the transistor drain is enabled for signal output,
The source of the first amplification field effect transistor and the drain of the amplification path switch field effect transistor are connected via a bypass circuit in which a capacitor and a bypass path switch field effect transistor as a switch element are connected in series. And
The first amplifying field effect transistor has a gate that can be externally applied with a bias voltage and is grounded in an alternating manner, while a drain is applied with a power supply voltage via the matching circuit. A characteristic amplifier. A second amplifying field effect transistor is provided between the drain of the first amplifying field effect transistor and the matching circuit, and the source of the second amplifying field effect transistor includes the first amplifying field effect transistor. The drain of the second amplification field effect transistor is connected, and the drain of the second amplification field effect transistor is connected to the matching circuit,
2. The amplifier according to claim 1, wherein a gate of the second amplification field effect transistor is connected to a gate of the first amplification field effect transistor.

Images