JP2009272319A - Ferroelectric memory device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device which has oxygen barrier properties and hydrogen barrier properties and simplifies the structure of a ferroelectric capacitor and is manufactured in an easy method, and a method of manufacturing the same. <P>SOLUTION: The ferroelectric memory device has a conductive barrier film 1 connected to a plug electrode 24, a lower electrode 2 disposed on the conductive barrier film 1 and connected to a plug electrode 24 through the conductive barrier film 1, a ferroelectric film 3 disposed on the lower electrode 2, an upper electrode 4 disposed on the ferroelectric film 3, a conductive hydrogen barrier film 5 disposed on the upper electrode 4, a VIA electrode 26 disposed on the conductive hydrogen barrier film 5 and connected to the upper electrode 4 through the conductive hydrogen barrier film 5, and an insulating hydrogen barrier film 6 disposed on the conductive hydrogen barrier film 5 and also on sidewalls of the conductive barrier film 1, lower electrode 2, ferroelectric film 3, upper electrode 4, and conductive hydrogen barrier film 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory device and a manufacturing method thereof, and more particularly to a ferroelectric memory device having a ferroelectric capacitor having oxygen barrier performance and hydrogen barrier performance and a manufacturing method thereof.

  A capacitor having a ferroelectric film disposed between electrodes (hereinafter referred to as “ferroelectric capacitor”) is used as a capacitor constituting a pixel of a display device or a memory cell such as a nonvolatile memory. Yes. As the ferroelectric used in the ferroelectric capacitor, a material having a large remanent polarization and a small coercive electric field and having a good squareness ratio is used. Specifically, a ferroelectric capacitor having a structure in which a ferroelectric film such as a lanthanum-doped lead zirconate titanate (PLZT) film is disposed between an upper electrode and a lower electrode is employed.

  The ferroelectric memory uses the hysteresis characteristic of the ferroelectric capacitor, so that it is excellent in non-volatile storage data (for example, retention performance of about 10 years) and high-speed data writing performance of, for example, about several tens of ns. Realize the characteristics.

  As shown in FIG. 13, the conventional ferroelectric capacitor multilayer structure includes a lower electrode 102, a ferroelectric film 103 disposed on the lower electrode 102, and an upper electrode 104 disposed on the ferroelectric film 103. With. A conductive barrier film 101 is formed between the lower electrode 102 and the plug electrode 124, and a VIA electrode 126 is formed on the upper electrode 104. An insulating hydrogen barrier film 106 is formed on the side wall portion of the laminated structure of the conductive barrier film 101 / the lower electrode 102 / the ferroelectric film 103 / the upper electrode 104 and on the upper electrode 104.

  In the conventional ferroelectric memory cell, at the interface between the VIA electrode 126 and the upper electrode 104 around the ferroelectric capacitor multilayer structure composed of the conductive barrier film 101 / the lower electrode 102 / the ferroelectric film 103 / the upper electrode 104. Has a structure without a hydrogen barrier film. This is because in the conventional ferroelectric memory cell, since the ratio of the area of the VIA electrode 126 is smaller than the area of the ferroelectric capacitor, the hydrogen barrier performance is not a problem.

  However, when the processing rule becomes finer and the ratio of the area of the VIA electrode 126 increases as compared to the area of the ferroelectric capacitor, it is necessary to apply tungsten (W) or copper (Cu) as the material of the VIA electrode 126. .

In particular, when W is used as a VIA electrode 126 or a plug electrode, chemical vapor deposition (CVD) is used in an electrode forming process by a fine process in which a high aspect ratio contact hole or a VIA hole is embedded with a W electrode. According to the method, tungsten hexafluoride (WF ₆ ) as a raw material gas is reduced with hydrogen or silane.

  At this time, the conventional structure in which no hydrogen barrier film is present has a problem that the ferroelectric film 103 is also reduced.

  When using W as the plug electrode 124, it is necessary to use a material having an oxygen barrier property as the conductive barrier film 101. For example, iridium (Ir) or titanium nitride (TiN) based materials are used as the oxygen barrier film. When using Ir or a TiN-based material, the oxygen barrier property is low, and thus contrivances such as increasing the film thickness or forming a buried structure are made, but there is a disadvantage that the number of steps increases. Further, a structure in which an IrTa film is applied as the conductive barrier film 101 for protecting the lower electrode has already been proposed (see, for example, Patent Document 1).

In addition, a structure in which an alumina (Al ₂ O ₃ ) film, which is an insulator, is formed on the sidewall as the insulating hydrogen barrier film 106 has already been proposed (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 2002-141383 (FIG. 1, Table 1, pages 6-7) JP 2006-73560 A (FIG. 1, pages 7-8)

Conventionally, the oxygen barrier performance of IrTa films has been known, but the hydrogen barrier performance has not been found. The present inventors experimentally confirmed the hydrogen barrier performance of an Ir _x Ta _1-x (0 <x <1) film as an amorphous metal, and formed an Ir _x Ta _1-x (0 <x <1) film. It has been found that the present invention can be applied not only as a conductive oxygen barrier film but also as a conductive hydrogen barrier film.

  An object of the present invention is to provide a ferroelectric memory device having an oxygen barrier property and a hydrogen barrier property, a simplified multilayer structure of a ferroelectric capacitor, and an easy manufacturing method, and a manufacturing method thereof. .

  According to one aspect of the present invention for achieving the above object, a first electrode, a conductive barrier film connected to the first electrode, and the conductive barrier film disposed on the conductive barrier film. A lower electrode connected to the first electrode via the first electrode; a ferroelectric film disposed on the lower electrode; an upper electrode disposed on the ferroelectric film; and an upper electrode disposed on the upper electrode. A conductive hydrogen barrier film, a second electrode disposed on the conductive hydrogen barrier film and connected to the upper electrode via the conductive hydrogen barrier film, on the conductive hydrogen barrier film, and A ferroelectric memory device is provided that includes a conductive barrier film, the ferroelectric film, the upper electrode, and an insulating hydrogen barrier film disposed on a sidewall of the conductive hydrogen barrier film.

  According to another aspect of the present invention, a step of forming a first electrode, a step of forming a conductive barrier film on the first electrode, a step of forming a lower electrode on the conductive barrier film, Forming a ferroelectric film on the lower electrode; forming an upper electrode on the ferroelectric film; forming a conductive hydrogen barrier film on the upper electrode; and the conductive hydrogen Forming an insulating hydrogen barrier film on the barrier film and on the conductive barrier film, the ferroelectric film, the upper electrode, and a sidewall of the conductive hydrogen barrier film; and on the conductive hydrogen barrier film And a method of forming a second electrode. A method for manufacturing a ferroelectric memory device is provided.

  According to the present invention, there are provided a ferroelectric memory device having an oxygen barrier property and a hydrogen barrier property, a simplified multilayer structure of a ferroelectric capacitor, and an easy manufacturing method, and a manufacturing method thereof.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
(Ferroelectric memory device)
A schematic cross-sectional structure of the ferroelectric memory device according to the first embodiment of the present invention is expressed as shown in FIG. 1, and an enlarged schematic cross-sectional structure of the ferroelectric capacitor multilayer structure 8 is shown in FIG. As shown in FIG.

  As shown in FIGS. 1 and 2, the ferroelectric memory device according to the first embodiment is formed on a semiconductor substrate 10 and has a plug electrode 24 and a conductive barrier film 1 connected to the plug electrode 24. A lower electrode 2 disposed on the conductive barrier film 1 and connected to the plug electrode 24 via the conductive barrier film 1, a ferroelectric film 3 disposed on the lower electrode 2, and a ferroelectric The upper electrode 4 disposed on the film 3, the conductive hydrogen barrier film 5 disposed on the upper electrode 4, and the upper electrode disposed on the conductive hydrogen barrier film 5 via the conductive hydrogen barrier film 5 4, on the conductive hydrogen barrier film 5, and on the conductive hydrogen barrier film 5, the upper electrode 4, the ferroelectric film 3, the lower electrode 2, and the side wall of the conductive barrier film 1. And an insulating hydrogen barrier film 6 disposed.

  A memory cell transistor made of a metal-oxide-semiconductor field effect transistor (MOSFET) is formed on the semiconductor substrate 10.

The semiconductor substrate 10 is formed of a p-type semiconductor, and an active region electrically isolated by the element isolation region 14 is formed. In the active region, as shown in FIG. 1, a source region or a drain region (S / D region) 12 and an S / D region 13 formed of an n ⁺ diffusion region are arranged. S / n ⁺ (12,13) D region 13 opposes n to p (10) joint surfaces ^- high resistance region 16 is ^{arranged, n + (12,13) n- (} 16) p (10) junction Thus, the leakage current in the vicinity of the S / D region 12 and the S / D region 13 is reduced and the breakdown voltage is maintained.

  A gate insulating film 18 is disposed on the semiconductor substrate 10 between the S / D region 12 and the S / D region 13, a gate electrode 20 is disposed on the gate insulating film 18, and a cap insulating film is disposed on the gate electrode 20. 22 is further disposed on the side wall portions of the gate insulating film 18, the gate electrode 20, and the cap insulating film 22.

  A plug electrode 25 is disposed on the S / D region 13, and the plug electrode 25 is connected to an M2 electrode 30 connected to the bit line BL via an M1 electrode 28 and a VIA electrode 29.

  A ferroelectric capacitor multilayer structure 8 is formed on the S / D region 12 via a plug electrode 24.

  An M1 electrode 27 connected to the plate line PL of the ferroelectric memory is arranged on the ferroelectric capacitor multilayer structure 8 via the VIA electrode 26.

  Regions 41, 42, and 43 represent interlayer insulating films and separate the electrodes.

  In FIG. 1, an interlayer insulating film 44 is disposed on the M2 electrode 30 connected to the bit line BL, and an interlayer insulating film 45 in which the M3 electrode 32 is embedded is disposed on the interlayer insulating film 44. An interlayer insulating film 46 in which the M4 electrode 34 is embedded is disposed on the 45. In addition, in this embodiment, although the structure of the 4-layer metal of M1 electrode-M4 electrode is shown, it is not restricted to this, For example, a 3 layer, 5 layer metal may be sufficient. An appropriate number of metal layers may be selected depending on the wiring scale, for example.

  The M1 electrode 27 to M4 electrode 34 are connected to each other at a predetermined contact portion via, for example, a metal damascene structure via a VIA electrode.

  In FIG. 1, two memory cell transistors composed of MOSFETs having the S / D region 13 as a common region are arranged. The S / D region 13 is connected to the M2 electrode 30 connected to the bit line BL, and the S / D region 12 is connected to the plate line 27 via the ferroelectric capacitor formed by the ferroelectric capacitor multilayer structure 8. Has been. As a result, two 1T-1C type ferroelectric memory cells having the M2 electrode 30 connected to the bit line BL as a common wiring are formed.

  In the configuration shown in FIG. 1, the formation of the M1 electrodes 27 and 28 to M4 electrodes 34 via the MOSFET regions and the respective interlayer insulating films 41 to 46 is the same as that of the miniaturized silicon process, and thus the description of the manufacturing method is omitted. Since the portion of the ferroelectric capacitor multilayer structure 8 is a characteristic structure of the ferroelectric memory device according to the present embodiment, a detailed manufacturing method of the portion will be described later.

The conductive barrier film 1 can be formed of Ir _x Ta _1-x (0 <x <1). In particular, it is made of an amorphous metal. The composition ratio x of iridium in Ir _x Ta _1-x (0 <x <1) is, for example, about 0.3 or more and about 0.5 or less.

  As the lower electrode 2, platinum (Pt), Ir, strontium ruthenate (SRO), or the like can be used. The conductive barrier film 1 is a layer necessary for ensuring the conduction between the plug electrode 24 and the lower electrode 2 while preventing the plug electrode 24 from being oxidized, and is a ferroelectric layer having a stack structure applied to the present embodiment. It is an essential layer for the capacitor multilayer structure 8.

The ferroelectric film 3 is a material in which the polarization state generated when an electric field is applied after the electric field is no longer applied is maintained, and the direction of polarization changes depending on the direction of the electric field from the outside. In addition, a material having a hysteresis with an excellent squareness ratio with a small coercive electric field can be used. Specifically, for example, lead zirconate titanate (PZT) film, lanthanum doped lead zirconate titanate (PLZT) film, strontium barium titanate (BST) film, strontium bismuth tantalate (SBT) film, strontium niobate film Barium (SBN) film, lithium niobate (LiNbO ₃ ) film, barium titanate (TiBaO ₃ ) film, lanthanum strontium copper oxide (LSCO) film, potassium dihydrogen phosphate (KDP) film, potassium tantalum niobate (KTN) A film, a lead magnesium niobate titanate (PMN-PT) ceramic film, a lead zinc niobate titanate (PZN-PT) ceramic film, or the like can be used.

As the upper electrode 4, a transparent electrode such as Pt, Ir, iridium oxide (IrO _y ), SRO film, ITO film, or zinc oxide (ZnO) film can be employed.

The conductive hydrogen barrier film 5 is made of Ir _x Ta _1-x (0 <x <1). In particular, it is made of an amorphous metal. The composition ratio x of iridium in Ir _x Ta _1-x (0 <x <1) is, for example, about 0.3 or more and about 0.5 or less.

  The conductive hydrogen barrier film 5 is used not only for the wiring process and the VIA electrode 26 but also for protecting the ferroelectric film 3 from hydrogen generated during the subsequent VIA electrode forming process and between the upper electrode 4 and the VIA electrode 26. This layer is necessary for ensuring conduction.

As the insulating hydrogen barrier film 6, an alumina (Al ₂ O ₃ ) film, a nitride film (Si ₃ N ₄ ), or a multilayer film thereof can be employed. The insulating hydrogen barrier film 6 maintains the insulation between the upper electrode 4 and the lower electrode 2, while the ferroelectric film 3 is not limited to the wiring process, not only the VIA electrode 26 but also hydrogen generated during the subsequent VIA electrode forming process, It is a necessary layer for protection.

  For example, silicon (Si), gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), silicon carbide (SiC), or the like can be used for the semiconductor substrate 10. Instead of the semiconductor substrate 10, a sapphire substrate, a quartz substrate, a silicon on insulator (SOI) substrate, or the like can also be applied.

(Memory matrix circuit configuration example)
The circuit configuration of the memory matrix configuration of the ferroelectric memory device according to the first embodiment of the present invention is expressed as shown in FIG. Two ferroelectric memory cells 200 arranged along one bit line BL in FIG. 3 correspond to the element cross-sectional structure in FIG.

  3 has a plurality of bit lines BL1, BL2,... Arranged in the column direction and a plurality of bit lines BL1, BL2,... Arranged in the row direction orthogonal to the bit lines BL1, BL2,. Of word lines WL1, WL2,. The ferroelectric memory cells 200 controlled by any one of the bit lines BL1, BL2,... And any one of the word lines WL1, WL2,... Are arranged in a matrix in the column direction and the row direction.

As shown in FIG. 3, the ferroelectric memory cell 200 includes a memory cell transistor (Q _M ) 201 and a ferroelectric capacitor (C _F ) 202 connected in series. Writing and reading of the ferroelectric memory cell 200 are controlled by the memory cell transistor 201. The gate electrode and the drain electrode of the memory cell transistor 201 are connected to the word lines WL1, WL2,... And the bit lines BL1, BL2, ..., respectively, and the source electrode is connected to one electrode of the ferroelectric capacitor 202. The other electrode of the ferroelectric capacitor 202 is connected to the plate line. For example, the electrode connected to the plate line of the ferroelectric capacitor 202 can be the upper electrode 4 of each ferroelectric memory cell 200.

  In the ferroelectric memory cell 200, data is stored and retained using the polarization phenomenon of the ferroelectric film 3. That is, since the polarization state of the ferroelectric film 3 is maintained even when the external electric field is removed, the data stored in each ferroelectric memory cell 200 does not disappear even when the supply of power is stopped. Therefore, the ferroelectric memory cell 200 operates as a nonvolatile memory.

In the above description, the 1T-1C system configuration example in which the ferroelectric memory cell 200 includes one memory cell transistor 201 and one ferroelectric capacitor 202 is shown. Also good. For example, a 2T-2C system configuration example in which the ferroelectric memory cell includes two memory cell transistors Q _M and two ferroelectric capacitors C _F may be used. It is also possible to employ a configuration example of a 1T type having a ferroelectric capacitor C _F as the gate capacitor of the memory cell transistor Q _M.

(Manufacturing method of ferroelectric memory device)
As shown in FIGS. 4 to 8, the method for manufacturing a ferroelectric memory device according to the present embodiment includes a step of forming a plug electrode 24 and a step of forming a conductive barrier film 1 on the plug electrode 24. A step of forming a lower electrode 2 on the conductive barrier film 1, a step of forming a ferroelectric film 3 on the lower electrode 2, a step of forming an upper electrode 4 on the ferroelectric film 3, and an upper portion A step of forming a conductive hydrogen barrier film 5 on the electrode 4; a conductive hydrogen barrier film 5; and a conductive barrier film 1, a lower electrode 2, a ferroelectric film 3, an upper electrode 4, and a conductive hydrogen barrier. A step of forming an insulating hydrogen barrier film on the sidewall of the film; and a step of forming a VIA electrode on the conductive hydrogen barrier film.

  A manufacturing method of the ferroelectric memory device according to the present embodiment will be described below in detail with reference to FIGS.

(A) First, as shown in FIG. 4, after a MOSFET serving as a memory cell transistor is formed on the semiconductor substrate 10, an interlayer insulating film 41 is deposited by, for example, a CVD insulating film, a TEOS film, etc. Form. As the material of the plug electrode 24, for example, W is applied together with the miniaturization of the memory cell transistor.

Here, a process of forming the plug electrode 24 with a W plug (W-plug) will be described. After forming a high aspect ratio contact hole in the interlayer insulating film 41, when filling the contact hole with a W electrode, the source gas WF ₆ is reduced with H ₂ , SiH ₄ or the like.

The reaction in the case of H ₂ reduction is represented by WF ₆ + 3H ₂ → W + 6HF. The reaction in the case of SiH ₄ reduction is represented by 2WF ₆ + 3SiH ₄ → 2W + 3SiF ₄ + 6H ₂ . Therefore, if there is no hydrogen barrier performance in the ferroelectric capacitor multilayer structure 8, the ferroelectric film 3 is also reduced.

  Note that a normal silicon miniaturization process can be applied to the MOSFET formation process. For example, the element isolation region 14 is formed by a shallow trench isolation (STI) technique. The gate insulating film 18 is formed by a thermal oxidation process. The S / D region 12, the S / D region 13, and the high resistance region 16 are formed by an arsenic or phosphorus ion implantation technique or a diffusion process. The gate electrode 20 is formed by, for example, a polysilicon forming technique. In the electrode forming process for the S / D region 12, the S / D region 13, and the gate electrode 20, a silicide technique such as W, molybdenum (Mo), cobalt (Co) or the like for forming a miniaturized contact is applied. Is also possible. Deposition techniques such as a CVD oxide film and a CVD nitride film are applied to the sidewall insulating film 19 and the cap insulating film 22. The description of the MOSFET manufacturing process is omitted here.

(B) Next, as shown in FIG. 5, the conductive barrier film 1 is formed on the entire surface of the interlayer insulating film 41 and the plug electrode 24. The conductive barrier film 1 is made of Ir _x Ta _1-x . In particular, it is made of an amorphous metal. The composition ratio x of iridium in Ir _x Ta _1-x is, for example, about 0.3 or more and about 0.5 or less. Since the Ir _x Ta _1-x film formed of amorphous metal has hydrogen barrier performance, it becomes a hydrogen barrier film when a plug electrode or a VIA electrode is formed as a W electrode thereafter. As a result, it can be a protective film for the ferroelectric film 3. Moreover, since the Ir _x Ta _1-x (0 <x <1) film formed of amorphous metal also has oxygen barrier performance, the W electrode can be prevented from being oxidized.

(C) Next, as shown in FIG. 5, the lower electrode 2 is formed on the entire surface of the conductive barrier film 1. The lower electrode 2 is formed, for example, by sputtering or the like with a film thickness of about several tens of nm to about 100 nm of Pt, Ir, SRO, or the like.

  Specifically, the lower electrode 2 may be formed with a two-layer structure. For example, an IrTa film is formed in contact with the conductive barrier film 1 by a sputtering method, and then an Ir film is similarly formed on the IrTa film by a sputtering method. The thickness of each layer is about several tens of nm to 100 nm.

(D) Next, as shown in FIG. 5, a ferroelectric film 3 is formed on the entire surface of the lower electrode 2. For example, PZT, PLZT film, BST film, SBT film, SBN film, LiNbO ₃ film, TiBaO ₃ film, LSCO film, KDP film, KTN film, PMN-PT based ceramic film, PZN-PT based ceramic film, etc. It is formed by the method, MOCVD method, sol-gel method or the like. Specifically, the PLZT film is formed with a film thickness of about several tens to about 100 nm using, for example, MOCVD.

(E) Next, as shown in FIG. 5, the upper electrode 4 is formed on the entire surface of the ferroelectric film 3. As the upper electrode 4, a transparent electrode such as Pt, Ir, iridium oxide (IrO _y ), SRO film, ITO film or ZnO film is formed with a film thickness of about 200 nm by sputtering or the like.

Specifically, the upper electrode 4 may be formed with a two-layer structure. For example, an IrO ₂ film is formed in contact with the ferroelectric film 3 by a sputtering method, and then an Ir film is similarly formed on the IrO ₂ film by a sputtering method. The thickness of each layer is about several tens of nm to 100 nm.

(F) Next, as shown in FIG. 5, a conductive hydrogen barrier film 5 is formed on the entire surface of the upper electrode 4. The conductive hydrogen barrier film 5 is made of Ir _x Ta _1-x (0 <x <1). In particular, it is made of an amorphous metal. The composition ratio x of iridium in Ir _x Ta _1-x (0 <x <1) is, for example, about 0.3 or more and about 0.5 or less. Since the Ir _x Ta _1-x (0 <x <1) film formed of amorphous metal has hydrogen barrier performance, a hydrogen barrier film when a plug electrode or a VIA electrode is formed as a W electrode by H ₂ reduction Become. As a result, it can be a protective film for the ferroelectric film 3. In addition, since the Ir _x Ta _1-x film formed of amorphous metal also has oxygen barrier performance, the W electrode can be prevented from being oxidized.

(G) Next, as shown in FIG. 6, after applying a photoresist film on the conductive hydrogen barrier film 5, the formation region of the ferroelectric capacitor is demarcated by the photolithography technique, and the conductive hydrogen barrier film 5 is formed. The upper electrode 4, the ferroelectric film 3, the lower electrode 2, and the conductive barrier film 1 are selectively etched by dry etching. In dry etching of each layer, it is effective to switch the etching gas system. As the etching gas system, for example, a halogen-based gas such as a chlorine-based or bromine-based gas or an argon (Ar) -based gas can be used. Specifically, for example, C ₄ F ₈ gas, CF ₄ gas, and Ar gas can be applied to PLZT. For ITO, for example, Ar gas, Cl ₂ gas, and Pt, C ₄ F ₈ gas, CF ₄ gas, Ar gas, or Cl ₂ gas can be applied.

(H) Next, as shown in FIG. 7, after the insulating hydrogen barrier film 6 is formed on the entire surface of the device, the conductive barrier film 1, and the conductive barrier film 1, An insulating hydrogen barrier film 6 is formed on the side walls of the lower electrode 2, the ferroelectric film 3, the upper electrode 4, and the conductive hydrogen barrier film 5 and on a part of the interlayer insulating film 41. As the insulating hydrogen barrier film 6, an Al ₂ O ₃ film, a Si ₃ N ₄ film, or a multilayer film thereof is formed to a thickness of about several tens of nm to about several hundreds of nm by CVD or sputtering.

(I) Next, as shown in FIG. 7, an interlayer insulating film 42 is formed on the entire surface of the device. As the interlayer insulating film 42, an oxide film, a nitride film, or the like is formed by CVD. Here, after the formation of the interlayer insulating film 42, a step of planarization by a chemical mechanical polishing (CMP) technique may be applied.

(J) Next, as shown in FIG. 8, after the formation of the interlayer insulating film 42, the VIA electrode 26 is formed. As a material of the VIA electrode 26, for example, W, Cu, or the like is applied together with miniaturization of the memory cell transistor.

  Here, the process of forming the VIA electrode 26 with a W-plug is the same as the process (a) described above, and thus the description thereof is omitted.

  FIG. 9 shows an X-ray rocking curve when an IrTa film is formed as a conductive barrier film in the method for manufacturing a ferroelectric memory device according to the present embodiment. The vertical axis represents relative intensity (arbitrary unit), and the horizontal axis represents an angle 2θ (°) that is twice the black angle θ in X-ray diffraction.

When the composition is Ir _0.45 Ta _0.55 , it can be seen that a peak indicating crystallization is not observed both after film formation and after annealing at 650 ° C. in an oxygen atmosphere and remains amorphous. On the other hand, in the case of Ir _0.6 Ta _0.4 , a peak indicating crystallization is observed after the film formation, and further, the peak is maintained even after annealing, and it can be seen that it is still crystallized.

The relationship between the sheet resistance (Ω / □) of the Ir _x Ta _1-x (0 <x <1) film and the Ir / (Ir + Ta) ratio x is expressed as shown in FIG. Moreover, the schematic cross-sectional structure of the sample used for the measurement of Fig.10 (a) is represented as shown in FIG.10 (b). If the value of the Ir / (Ir + Ta) ratio x is greater than about 0.5, it will crystallize, and therefore will oxidize if annealed in an oxygen atmosphere. On the other hand, when the value of the Ir / (Ir + Ta) ratio x is smaller than about 0.5, the Ir _x Ta _1-x (0 <x <1) film remains amorphous. Moreover, when annealing is performed in an oxygen atmosphere at 650 ° C., the sheet resistance (Ω / □) does not change much, but when annealed in an oxygen atmosphere at 700 ° C., the sheet resistance ( The graph shape of (Ω / □) has changed greatly. However, even when annealed in a 700 ° C. oxygen atmosphere, if the value of the Ir / (Ir + Ta) ratio x is about 0.4 or more and about 0.45 or less, the sheet resistance (Ω / □) Little change is observed in the value of. Annealed at 700 ° C. in an oxygen atmosphere - even when _{Le, Ir x Ta 1-x (} 0 <x <1) W under film is not _{oxidized, Ir x Ta 1-x (} 0 <x <1) film Oxygen barrier properties have been confirmed.

  FIG. 11A shows the SIMS analysis result of hydrogen distribution in the IrTa film after hydrogen sintering. FIG. 11B shows a schematic cross-sectional structure of the sample used for the measurement in FIG. In Ir where the depth direction measured from the surface side of the Ir / IrTa structure is about 120 nm, the secondary ion intensity (counts / sec) of SIMS increases, but in IrTa, the secondary ion intensity (counts) of SIMS increases. / Sec) is unchanged. This shows that hydrogen is blocked at the Ir / IrTa interface. Therefore, it was observed that the IrTa film also functions as a hydrogen barrier film.

  FIG. 12 shows the result of measuring the residual polarization amount of the ferroelectric film 3 after the M1 to M4 electrode forming steps in the manufacturing method of the ferroelectric memory device according to the present embodiment. The vertical axis represents the normalized amount of remanent polarization, and the amount of remanent polarization of the ferroelectric film 3 measured before the M1 electrode formation step is 1. Even after the steps of forming the M1 electrode to the M4 electrode as shown in FIG. 1, a decrease in the residual polarization amount of the ferroelectric film 3 is not so much observed. From this, it can be seen that the ferroelectric capacitor multilayer structure in the ferroelectric memory device according to the present embodiment has both a hydrogen barrier property and an oxygen barrier property.

  According to the present embodiment, a ferroelectric memory device having an oxygen barrier property and a hydrogen barrier property, a simplified structure of a ferroelectric capacitor, and an easy manufacturing method, and a manufacturing method thereof are provided.

[Other embodiments]
As described above, the present invention has been described according to the first embodiment. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are exemplary and limit the present invention. Absent. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention includes various embodiments that are not described herein.

  The ferroelectric memory device of the present invention includes a nonvolatile memory, an LSI embedded (embedded) memory, a piezoelectric device, a display device, an optical communication switch, an optical modulator, a laser printer, a copying machine, an optical modulator of a holographic memory, It can be applied to a wide range of fields such as optical arithmetic units and encryption circuits.

1 is a schematic sectional view of a ferroelectric memory device according to a first embodiment of the present invention. FIG. 2 is an enlarged schematic cross-sectional structure diagram of the ferroelectric capacitor of the ferroelectric memory device according to the first embodiment of the present invention. 1 is a circuit configuration diagram of a memory matrix configuration of a ferroelectric memory device according to a first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the ferroelectric memory device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the ferroelectric memory device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the ferroelectric memory device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the ferroelectric memory device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining a step in the method for manufacturing the ferroelectric memory device according to the first embodiment of the present invention. In the method for manufacturing a ferroelectric memory device according to the first embodiment of the present invention, an X-ray rocking curve is obtained when an IrTa film is formed as a conductive barrier film, and Ir _0.45 Ta before and after annealing. _The figure explaining that _0.55 is amorphous. (A) Relation between sheet resistance of IrTa film and Ir / (Ir + Ta) composition ratio, (b) Typical cross-sectional structure diagram of sample used for measurement of (a). (A) SIMS analysis result of the hydrogen distribution in the IrTa film after hydrogen sintering, illustrating that the IrTa film also functions as a hydrogen barrier film, (b) Schematic of the sample used for the measurement in (a) FIG. Relationship between wiring process and normalized residual polarization. FIG. 6 is an enlarged schematic cross-sectional structure diagram of a conventional ferroelectric capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Conductive barrier film 2 ... Lower electrode 3 ... Ferroelectric film 4 ... Upper electrode 5 ... Conductive hydrogen barrier film 6 ... Insulating hydrogen barrier film 8 ... Ferroelectric capacitor laminated structure 10 ... Semiconductor substrate 12, 13 ... Source area or rain area (S / D area)
14: Element isolation region (STI)
16 ... High resistance region 18 ... Gate insulating film 19 ... Side wall insulating film 20 ... Gate electrode 22 ... Cap insulating films 24, 25 ... Plug electrodes 26, 29 ... VIA electrodes 27, 28 ... M1 electrode 30 ... M2 electrode 32 ... M3 electrode 34 ... M4 electrodes 41, 42, 43, 44, 45, 46 ... Interlayer insulating film 200 ... Ferroelectric memory cell 201 ... Memory cell transistor (Q _M )
202 ... Ferroelectric capacitor (C _F )
BL, BL1, BL2,... Bit line WL, WL1, WL2,.

Claims (20)

A first electrode;
A conductive barrier film disposed on the first electrode;
A lower electrode disposed on the conductive barrier film and connected to the first electrode through the conductive barrier film;
A ferroelectric film disposed on the lower electrode;
An upper electrode disposed on the ferroelectric film;
A conductive hydrogen barrier film disposed on the upper electrode;
A second electrode disposed on the conductive hydrogen barrier film and connected to the upper electrode via the conductive hydrogen barrier film;
An insulating hydrogen barrier film disposed on the conductive hydrogen barrier film, and on the conductive barrier film, the lower electrode, the ferroelectric film, the upper electrode, and a sidewall of the conductive hydrogen barrier film; A ferroelectric memory device comprising: The ferroelectric memory device according to claim 1, wherein the conductive barrier film is made of Ir _x Ta _1-x (0 <x <1). The conductive hydrogen barrier film, Ir _x Ta _1-x ferroelectric memory device according to claim 1 or 2, characterized in that it consists of (0 <x <1). 2. The ferroelectric memory device according to claim 1, wherein the conductive barrier film is formed of an amorphous metal made of Ir _x Ta _1-x (0 <x <1). 2. The ferroelectric memory device according to claim 1, wherein the conductive hydrogen barrier film is formed of an amorphous metal made of Ir _x Ta _1-x (0 <x <1). 6. The strong composition according to claim 2, wherein the composition ratio x of iridium in the Ir _x Ta _1-x (0 <x <1) is 0.3 or more and 0.5 or less. Dielectric memory device. The ferroelectric film is formed of any one of PZT, PLZT, BST, SBT, LiNbO ₃ , SBN, TiBaO ₃ , LSCO, KDP, KTN, PMN-PT based ceramic film, and PZN-PT based ceramic film. The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device is a semiconductor memory device. The ferroelectric memory device according to claim 1, wherein the insulating hydrogen barrier film is formed of Al ₂ O ₃ , Si ₃ N _4, or a multilayer film thereof.   9. The ferroelectric memory device according to claim 1, wherein the lower electrode is formed of any one of Pt, Ir, and SRO.   10. The ferroelectric memory device according to claim 1, wherein the upper electrode is formed of any one of Pt, Ir, iridium oxide, ITO, ZnO, and SRO. Forming a first electrode;
Forming a conductive barrier film on the first electrode;
Forming a lower electrode on the conductive barrier film;
Forming a ferroelectric film on the lower electrode;
Forming an upper electrode on the ferroelectric film;
Forming a conductive hydrogen barrier film on the upper electrode;
Forming an insulating hydrogen barrier film on the conductive hydrogen barrier film and on the conductive barrier film, the lower electrode, the ferroelectric film, the upper electrode, and a sidewall of the conductive hydrogen barrier film; ,
Forming a second electrode on the conductive hydrogen barrier film. A method of manufacturing a ferroelectric memory device, comprising: The conductive barrier film, Ir _x Ta _1-x method of manufacturing a ferroelectric memory device according to claim 11, characterized in that it consists of (0 <x <1). 13. The method of manufacturing a ferroelectric memory device according to claim 11, wherein the conductive hydrogen barrier film is made of Ir _x Ta _1-x (0 <x <1). The conductive barrier film, Ir _x Ta _1-x method of manufacturing a ferroelectric memory device according to claim 11, characterized in that it is formed of amorphous metal consisting of (0 <x <1). The conductive hydrogen barrier film, Ir _x Ta _1-x method of manufacturing a ferroelectric memory device according to claim 11, characterized in that it is formed of amorphous metal consisting of (0 <x <1). The iridium composition ratio x in the Ir _x Ta _1-x (0 <x <1) is 0.3 or more and 0.5 or less, and the strength according to claim 12, A method of manufacturing a dielectric memory device. The ferroelectric film is formed of any one of PZT, PLZT, BST, SBT, LiNbO ₃ , SBN, TiBaO ₃ , LSCO, KDP, KTN, PMN-PT based ceramic film, and PZN-PT based ceramic film. The method of manufacturing a ferroelectric memory device according to claim 11, wherein the ferroelectric memory device is a semiconductor memory device. The insulating hydrogen barrier _{film, Al 2 O 3, Si 3} N 4 or the method of manufacturing a ferroelectric memory device according to any one of claims 11 to 17, characterized in that it is formed by these multilayer films .   The method of manufacturing a ferroelectric memory device according to claim 11, wherein the lower electrode is formed of any one of Pt, Ir, and SRO.   20. The method of manufacturing a ferroelectric memory device according to claim 11, wherein the upper electrode is formed of any one of Pt, Ir, iridium oxide, ITO, ZnO, and SRO. .

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