JP2013080786A - Silicon device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon device having a structure which inhibits or prevents metal atoms in a ferroelectric layer from diffusing in a silicon layer and achieves the downsizing and the improvement of characteristics.SOLUTION: An ink jet printer head 1 serving as a silicon device includes: a silicon substrate 2; a silicon oxide layer 5B formed on the silicon substrate 2; a diffusion prevention film 70 formed on the silicon oxide layer 5B; and a piezoelectric element 6 provided on the diffusion prevention film 70. A compression chamber 62 serving as an ink accumulation part is formed on the silicon substrate 2, and a thin silicon layer 5A and the silicon oxide layer 5B, located on a top plate part of the compression chamber 62, form a vibration film 5. The piezoelectric element 6 includes: a lower electrode 7 contacting with the diffusion prevention film 70; a piezoelectric layer 8 provided on the lower electrode 7; and an upper electrode 9 provided on the piezoelectric layer 8. The diffusion prevention film 70 prevents the diffusion of metal atoms in the piezoelectric layer 8.

Description

  The present invention relates to a silicon device having a silicon layer and a ferroelectric layer. Such devices include those including a capacitor having a ferroelectric layer as a capacitor film, and those including an actuator or sensor having a ferroelectric layer as a piezoelectric body.

Patent Document 1 discloses a piezoelectric inkjet printer head. This is an example of an actuator composed of a silicon device. The ink jet printer head of Patent Document 1 includes a silicon substrate, a vibration film made of a silicon oxide film formed on the silicon substrate, and a piezoelectric element provided on the vibration film. A pressure chamber is formed in the silicon substrate by etching, and a vibration film faces the pressure chamber. Ink is introduced into the pressure chamber. The piezoelectric element includes a lower electrode formed on the vibration film, a piezoelectric body formed on the lower electrode, and an upper electrode formed on the piezoelectric body. The piezoelectric body is made of PZT (lead zirconate titanate Pb (Zr, Ti) O ₃ ). When the piezoelectric element is driven by applying a voltage between the upper electrode and the lower electrode, the vibrating membrane vibrates. As a result, the volume of the pressurizing chamber changes, and the ink in the pressurizing chamber can be ejected from the nozzle.

Patent Document 2 discloses a ferroelectric capacitor. The ferroelectric capacitor includes a lower electrode formed on the silicon substrate, a ferroelectric capacitor film formed on the lower electrode, and an upper electrode formed on the ferroelectric capacitor film. The ferroelectric capacitor film is made of SBT (bismuth strontium tantalate SrBi ₂ Ta ₂ O ₉ ), BST (barium strontium titanate (Ba, Sr) TiO ₃ ), or the like.

JP 2011-56939 A JP 2009-272319 A

Ferroelectric materials represented by PZT, SBT, and BST contain metal atoms. This metal atom may diffuse through the electrode film and reach the silicon substrate.
More specifically, in the piezoelectric element used in the conventional ink jet printer head, the piezoelectric material (on the vibration film having a thickness of about 50 μm as a whole of the silicon layer and the silicon oxide layer formed thereon) A piezoelectric element having a thickness of about 100 μm was disposed. In this structure, even when metal atoms (Pb in the case of PZT) diffuse into the silicon oxide layer and the silicon layer, the vibration film is sufficiently thick, so that the characteristics of the vibration film are not unacceptably deteriorated. . In addition, since the piezoelectric body is also formed thick, even if metal atoms escape, there is no unacceptable change in characteristics.

  However, recent ink jet printer heads are required to eject fine droplets of many colors of ink. For this reason, it is necessary to make the nozzle unit incorporated in the printer head small in order to eject ink of each color, and it is necessary to thin the piezoelectric body and the vibration film so that fine droplets can be ejected. If metal atoms escape from such a thin piezoelectric body, a sufficient driving force may not be obtained. Further, if metal atoms diffuse into the thin vibration film, the vibration film becomes brittle and the durability is impaired. Furthermore, when not only the printer head but also elements such as transistors constituting the drive circuit are built on the silicon substrate, the metal atoms diffused into the silicon substrate significantly deteriorate the characteristics of these elements. Let In particular, metal atoms are likely to diffuse during heat treatment for forming a piezoelectric body.

A device having a piezoelectric element on a vibration film formed on a silicon substrate as well as an inkjet printer head has the same problem.
Furthermore, the same problem occurs in the ferroelectric capacitor element using SBT and BST as the ferroelectric capacitor film. That is, when metal atoms in the ferroelectric capacitor film (strontium and bismuth in the case of SBT and barium and strontium in the case of BST) penetrate the electrode and diffuse to the silicon substrate, the ferroelectric capacitor film There is a possibility that the dielectric constant may be lowered or the characteristics of other elements built in the silicon substrate may be significantly changed. In particular, the smaller the overall device is, the more the ferroelectric capacitor element is disposed near other elements in the silicon substrate, and this problem becomes apparent.

  Therefore, the present invention provides a silicon device having a structure that can suppress or prevent the metal atoms in the ferroelectric layer from diffusing into the silicon layer, thereby reducing the size and improving the characteristics.

In order to achieve the above object, an invention according to claim 1 includes a silicon layer, a metal layer laminated on the silicon layer, a ferroelectric layer laminated on the metal layer and containing metal atoms, and the silicon A silicon device including a diffusion preventing film that is laminated so as to be interposed between a layer and the ferroelectric layer and prevents diffusion of metal atoms in the ferroelectric layer into the silicon layer.
According to this configuration, the diffusion preventing film is interposed between the silicon layer and the ferroelectric layer, and the diffusion preventing film suppresses diffusion of metal atoms in the ferroelectric layer into the silicon layer or Is prevented. As a result, it is possible to avoid deterioration of the characteristics (particularly brittleness) of the ferroelectric layer and the silicon layer and deterioration of the characteristics of the element formed in the silicon layer. As a result, the ferroelectric layer and the silicon layer can be thinned, and the distance between the element in the silicon layer and the ferroelectric layer can be shortened, so that a silicon device having a small size and good characteristics can be obtained. Can be provided.

An insulating film such as a silicon oxide layer may be formed between the silicon layer and the metal layer. In this case, the diffusion prevention film may be interposed between the insulating film and the metal layer.
In the invention according to claim 2, the thin part of the silicon substrate having a thick part and a thin part forms a vibration film including the silicon layer, and the ferroelectric layer is a piezoelectric layer, 2. The silicon device according to claim 1, wherein the piezoelectric element is configured by laminating the piezoelectric layer between the metal layer as a lower electrode and an upper electrode.

  According to this configuration, the thin part of the silicon substrate constitutes the vibration film including the silicon layer, and the piezoelectric element is in contact with the vibration film. Since a diffusion preventing film is interposed between the silicon layer forming the vibration film and the piezoelectric layer, it is possible to avoid diffusion of metal atoms in the piezoelectric layer into the silicon layer constituting the vibration film. As a result, it is possible to avoid deterioration of the characteristics of the diaphragm, particularly brittleness, due to the diffusion of metal atoms. Furthermore, when an element is formed on the silicon substrate, deterioration of the characteristics of the element can be avoided.

The piezoelectric layer may be a PZT (lead zirconate titanate Pb (Zr, Ti) O ₃ ) layer or a KNN (potassium sodium niobate (K, Na) NbO ₃ ) layer. In the case of the PZT layer, diffusion of lead atoms as metal atoms is suppressed or prevented by the diffusion preventing film. In the case of the KNN layer, diffusion of sodium atoms as metal atoms is suppressed or prevented by the diffusion preventing film.

An insulating layer such as a silicon oxide layer may be formed between the silicon layer and the lower electrode, and this insulating layer may form the vibration film together with the silicon layer. In this case, the diffusion prevention film may be interposed between the insulating layer and the lower electrode.
A third aspect of the present invention is the silicon device according to the second aspect, wherein the lower electrode, the piezoelectric layer, and the upper electrode constitute an actuator that deforms the vibration film.

  According to this configuration, by applying a driving voltage between the lower electrode and the upper electrode, the piezoelectric layer can be expanded / contracted by the inverse piezoelectric effect, thereby deforming (vibrating) the vibrating membrane. Can do. Since the metal atoms in the piezoelectric layer can be prevented from diffusing into the vibration film, the piezoelectric layer can generate a sufficient driving force. In addition, since it is possible to avoid deterioration of the characteristics of the diaphragm, particularly brittleness, the durability of the actuator having the diaphragm can be improved.

According to a fourth aspect of the present invention, there is formed an ink reservoir partitioned by the vibration film, and the silicon device deforms the vibration film to pressurize and discharge ink in the ink pool. The silicon device according to claim 3, comprising:
According to this configuration, it is possible to provide an ink nozzle having a structure in which the ink in the ink reservoir is pressurized and discharged by deforming (vibrating) the vibration film. This ink nozzle can be applied to an inkjet printer head. Even when the piezoelectric layer and the diaphragm are made thinner for miniaturization and micro droplet ejection, it is possible to avoid a decrease in driving force due to diffusion of metal atoms in the piezoelectric layer, and the diaphragm is brittle Deterioration can be avoided and sufficient durability can be realized.

In addition to ink nozzles, microphones (particularly silicon microphones manufactured by MEMS (Micro Electro Mechanical Systems) technology) are examples of actuators.
According to a fifth aspect of the present invention, the lower electrode, the piezoelectric layer, and the upper electrode constitute a sensor that extracts a voltage generated by the piezoelectric layer due to deformation of the vibration film. This is a silicon device.

According to this configuration, when the piezoelectric film is distorted due to deformation (vibration) of the vibration film, a voltage is generated between the upper electrode and the lower electrode due to the piezoelectric effect. The sensor is configured to extract this voltage. Due to the metal atom diffusion preventing effect of the diffusion preventing film, it is possible to avoid the deterioration of the characteristics of the piezoelectric layer and the deterioration of the characteristics of the vibration film.
Examples of the sensor include a pressure sensor, an acceleration sensor, an angular velocity sensor, an ultrasonic sensor, and a microphone. For example, in a pressure sensor, one side of a vibrating membrane faces a pressure measurement target space, the other side of the vibrating membrane faces a reference pressure space, and deformation of the vibrating membrane according to a pressure difference between both sides of the vibrating membrane It can be set as the structure detected by. The acceleration sensor can be configured, for example, such that a weight is formed on the vibration film, and the deformation of the vibration film due to the inertial force due to the acceleration is detected by a piezoelectric element.

A sixth aspect of the present invention is the silicon device according to any one of the first to fifth aspects, wherein the ferroelectric layer contains lead.
According to this configuration, since the diffusion preventing film can prevent the lead atoms from diffusing into the silicon layer, the characteristics (particularly brittleness) of the silicon layer are deteriorated, or an element (transistor element, etc.) formed in the silicon layer. It is possible to avoid the deterioration of the characteristics.

The ferroelectric layer containing lead may be PZT.
The invention according to claim 7 is the silicon device according to any one of claims 1 to 6, wherein the diffusion prevention film is an alumina film.
Since alumina has a crystal structure in which atoms are densely packed, the movement of metal atoms in the ferroelectric layer can be restricted to prevent its diffusion.

In addition to alumina, magnesium oxide, silicon carbide, and the like can similarly be applied as a diffusion preventing film because they have a crystal structure in which atoms are densely packed.
As the ferroelectric layer, in addition to the piezoelectric layer as described above, a ferroelectric capacitor film used as a capacitor film of a ferroelectric capacitor element can be exemplified. The ferroelectric capacitor film can be composed of an SBT (bismuth strontium tantalate SrBi ₂ Ta ₂ O ₉ ) film or a BST (barium strontium titanate (Ba, Sr) TiO ₃ ) film.

FIG. 1 is a schematic cross-sectional view of an ink jet printer head according to a first embodiment of the present invention. FIG. 2 is a partially enlarged cross-sectional view showing an enlarged configuration in the vicinity of the piezoelectric element. 3A is a schematic cross-sectional view showing a manufacturing process of the ink jet printer head shown in FIG. FIG. 3B is a schematic cross-sectional view showing a step that follows FIG. 3A. FIG. 3C is a schematic cross-sectional view showing a step that follows FIG. 3B. FIG. 3D is a schematic cross-sectional view showing a step that follows FIG. 3C. FIG. 3E is a schematic cross-sectional view showing a step that follows FIG. 3D. FIG. 3F is a schematic cross-sectional view showing a step that follows FIG. 3E. FIG. 3G is a schematic cross-sectional view showing a step that follows FIG. 3F. FIG. 3H is a schematic cross-sectional view showing a step that follows FIG. 3G. FIG. 3I is a schematic cross-sectional view showing a step that follows FIG. 3H. FIG. 3J is a schematic cross-sectional view showing a step that follows FIG. 3I. FIG. 3K is a schematic cross-sectional view showing a step that follows FIG. 3J. FIG. 3L is a schematic cross-sectional view showing a step that follows FIG. 3K. FIG. 3M is a schematic cross-sectional view showing a step that follows FIG. 3L. FIG. 3N is a schematic cross-sectional view showing a step that follows FIG. 3M. FIG. 3O is a schematic cross-sectional view showing a step that follows FIG. 3N. FIG. 3P is a schematic cross-sectional view showing a step that follows FIG. 3O. FIG. 3Q is a schematic cross-sectional view showing a step that follows FIG. 3P. FIG. 3R is a schematic cross-sectional view showing a step that follows FIG. 3Q. FIG. 3S is a schematic cross-sectional view showing a step that follows FIG. 3R. FIG. 4 is a schematic cross-sectional view for explaining the configuration of an ultrasonic sensor according to the second embodiment of the present invention. FIG. 5 is a schematic cross-sectional view for explaining the configuration of the high-frequency circuit device according to the third embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of an ink jet printer head according to a first embodiment of the present invention. The ink jet printer head 1 includes a silicon substrate 2, a chirality plate, and 10A, 10B, and 10C.
A nozzle formation region 3 and a circuit formation region 4 are set on the silicon substrate 2. Further, a pressure chamber 62 as an ink reservoir is formed on the silicon substrate 2. The cavity plate 10A is made of, for example, a silicon plate. The cavity plate 10A is bonded to the back surface of the silicon substrate 2 so as to form ink passages 10a and 11a. The ink passage 10 a is an ink supply passage that communicates with the pressurizing chamber 62 and supplies ink to the pressurizing chamber 62. The ink passage 11 a communicates with the pressurizing chamber 62 at a position different from the ink passage 10 a and forms a part of the ink discharge passage 11. The cavity plates 10B and 10C may be made of a plastic plate or a stainless plate. The cavity plate 10B is bonded to the cavity plate 10A, and an ink passage 11b aligned with the ink passage 11a of the cavity plate 10A is formed so as to penetrate in the thickness direction. The cavity plate 10C is bonded to the cavity plate 10B, and a nozzle passage 11c aligned with the ink passage 11b of the cavity plate 10B is formed so as to penetrate in the thickness direction. The ink passages 11 a and 11 b and the nozzle passage 11 c form an ink discharge passage 11. Ink is discharged from the pressure chamber 62 through the ink discharge passage 11 and from the discharge port 11d formed at the tip of the nozzle passage 11c. The ink passages 11a and 11b have a uniform flow path cross section from each inlet to the outlet. The nozzle passage 11c has an inlet that is aligned with the outlet of the ink passage 11b, and the cross section of the flow passage is tapered toward the ejection port 11d.

In the nozzle formation region 3, a vibration film 5 is formed on the surface of the silicon substrate 2. The vibration film 5 includes a silicon layer 5A and a silicon oxide (SiO ₂ ) layer 5B which is an insulating film. The thickness of the vibration film 5 is, for example, 0.5 μm to 2 μm. More specifically, the thickness of the silicon layer 5A is, for example, about 0.3 μm to 1.4 μm, and the thickness of the silicon oxide layer 5B is, for example, about 0.2 μm to 0.6 μm. The silicon layer 5 </ b> A is formed by partially etching the silicon substrate 2 from the back surface side in the nozzle formation region 3 to form the pressurizing chamber 62 and leaving a thin portion on the top surface portion of the pressurizing chamber 62. Yes. That is, the silicon substrate 2 has a thick portion (thickness 50 μm to 60 μm) other than the pressurizing chamber 62 and a thin portion that is a top surface portion of the pressurizing chamber 62, and the thin portion is a vibration film. 5 A constituting the silicon layer 5 is formed.

In the nozzle formation region 3, a diffusion prevention film 70 made of alumina (Al ₂ O ₃ ) is laminated on the surface of the vibration film 5, that is, the surface of the silicon oxide layer 5 B as shown in an enlarged view in FIG. . The film thickness of the diffusion preventing film 70 is, for example, 50 μm to 1 μm. On the diffusion prevention film 70, the piezoelectric element 6 is disposed. The piezoelectric element 6 includes a lower electrode 7 formed on the diffusion preventing film 70, a piezoelectric layer 8 formed on the lower electrode 7, and an upper electrode 9 formed on the piezoelectric layer 8. . In other words, the piezoelectric element 6 is formed by sandwiching the piezoelectric layer 8 between the upper electrode 9 and the lower electrode 7 from above and below. A diffusion prevention film 70 is interposed between the lower electrode 7 and the vibration film 5 (more specifically, the silicon oxide layer 5B). Thus, a structure in which the diffusion preventing film 70 is interposed between the piezoelectric layer 8 and the silicon layer 5A is formed.

The lower electrode 7 has a two-layer structure in which a Ti (titanium) layer and a Pt (platinum) layer (for example, 100 nm to 150 nm thickness) are sequentially stacked from the vibration film 5 side. In addition, the lower electrode can be formed of a single film such as an Au (gold) film, a Cr (chromium) film, or a Ni (nickel) film. When the lower electrode 7 is composed of a Ti / Pt laminated structure film, the Ti layer functions as an adhesive layer for adhering the Pt layer to the diffusion prevention film 70, and the interface between the Ti layer and the diffusion prevention film 70 has TiO _Two layers are formed. The lower electrode 7 has a main body portion 7A in contact with the piezoelectric layer 8 and an extension portion 7B extending laterally from the main body portion 7A.

The piezoelectric layer 8 is formed in the same shape as the main body portion 7A of the lower electrode 7 in plan view. The piezoelectric layer 8 is made of, for example, PZT (lead zirconate titanate: Pb (Zr, Ti) O ₃ ). That is, the piezoelectric layer 8 contains Pb which is a metal element. The diffusion preventing film 70 prevents the diffusion of Pb atoms and suppresses or prevents the Pb atoms from reaching the silicon layer 5A. The thickness of the piezoelectric layer 8 is preferably 1 μm to 5 μm. The total thickness of the vibration film 5 is preferably about the same as the thickness of the piezoelectric layer 8 or about 2/3 of the thickness of the piezoelectric layer 8. The piezoelectric layer 8 may be composed of a KNN (potassium sodium niobate (K, Na) NbO ₃ ) layer. In this case, the diffusion of sodium atoms as metal atoms is suppressed or prevented by the diffusion preventing film 70.

The upper electrode 9 is formed in the same shape as the piezoelectric layer 8 in plan view. The upper electrode 9 has a two-layer structure in which an IrO ₂ (iridium oxide) layer and an Ir (iridium) layer are sequentially laminated from the piezoelectric layer 8 side.
In the nozzle formation region 3, the surfaces of the vibration film 5 and the piezoelectric element 6 are covered with a hydrogen barrier film 13. The hydrogen barrier film 13 is made of Al ₂ O ₃ (alumina). Thereby, characteristic deterioration due to hydrogen reduction of the piezoelectric layer 8 can be prevented. An interlayer insulating film 14 is laminated on the hydrogen barrier film 13. Interlayer insulating film 14 is made of SiO _2. On the interlayer insulating film 14, wirings 15 and 16 are formed. The wirings 15 and 16 are made of a metal material containing Al (aluminum).

One end of the wiring 15 is disposed above the tip of the extension 7 </ b> B of the lower electrode 7. A through hole 17 that continuously penetrates the hydrogen barrier film 13 and the interlayer insulating film 14 is formed between one end of the wiring 15 and the extension 7B. One end of the wiring 15 enters the through hole 17 and is connected to the extension 7 </ b> B in the through hole 17.
One end of the wiring 16 is disposed above the peripheral edge of the upper electrode 9. A through hole 18 is formed between the one end of the wiring 16 and the upper electrode 9 so as to continuously penetrate the hydrogen barrier film 13 and the interlayer insulating film 14. One end of the wiring 16 enters the through hole 18 and is connected to the upper electrode 9 in the through hole 18.

The other end portions of the wirings 15 and 16 are connected to a drive circuit 72 described later.
In the circuit formation region 4, for example, an integrated circuit (CMOS integrated circuit) including an N-channel MOSFET (Negative-Channel Metal Oxide Semiconductor Field Effect Transistor) 21 and a P-channel MOSFET (Positive-Channel Metal Oxide Semiconductor Field Effect Transistor) 22. Is formed. This integrated circuit includes a drive circuit 72 for driving the piezoelectric element 6.

In the circuit formation region 4, the NMOS region 23 in which the N-channel MOSFET 21 is formed and the PMOS region 24 in which the P-channel MOSFET 22 is formed are insulated and isolated from each other by the element isolation unit 25. The element isolation portion 25 includes a thermal oxide film 27 formed on the inner surface of a groove (for example, a shallow trench having a depth of 0.2 μm to 0.5 μm) dug relatively shallowly from the surface of the silicon substrate 2, and thermal oxidation. And an insulator 28 filling the inside of the film 27. The insulator 28 is made of, for example, SiO ₂ . The surface of the insulator 28 is flush with the surface of the silicon substrate 2.

  A P-type well 31 is formed in the NMOS region 23. The depth of the P-type well 31 is larger than the depth of the groove 26. In the surface layer portion of the P-type well 31, an N-type source region 33 and a drain region 34 are formed with a channel region 32 interposed therebetween. The depth and impurity concentration of the end portions of the source region 33 and the drain region 34 on the channel region 32 side are reduced. That is, in the N-channel MOSFET 21, an LDD (Lightly Doped Drain) structure is applied.

A gate insulating film 35 is formed on the channel region 32. The gate insulating film 35 is made of SiO _2. A gate electrode 36 is formed on the gate insulating film 35. The gate electrode 36 is made of N-type polysilicon. Sidewalls 37 are formed around the gate insulating film 35 and the gate electrode 36. The sidewall 37 is made of SiN.
Silicides 38, 39, and 40 are formed on the surfaces of the source region 33, the drain region 34, and the gate electrode 36, respectively.

  An N-type well 41 is formed in the PMOS region 24. The depth of the N-type well 41 is larger than the depth of the groove 26. In the surface layer portion of the N-type well 41, a P-type source region 43 and a drain region 44 are formed with a channel region 42 interposed therebetween. The depth and impurity concentration of the end portions of the source region 43 and the drain region 44 on the channel region 42 side are reduced. That is, the LD channel structure is applied to the P-channel MOSFET 22.

A gate insulating film 45 is formed on the channel region 42. The gate insulating film 45 is made of SiO _2. A gate electrode 46 is formed on the gate insulating film 45. The gate electrode 46 is made of P-type polysilicon. A sidewall 47 is formed around the gate insulating film 45 and the gate electrode 46. The side wall 47 is made of SiN.
Silicides 48, 49, and 50 are formed on the surfaces of the source region 43, the drain region 44, and the gate electrode 46, respectively.

In the circuit formation region 4, an interlayer insulating film 51 is formed on the surface of the silicon substrate 2. Interlayer insulating film 51 is made of SiO _2. On the interlayer insulating film 51, wirings 52, 53, and 54 are formed. The wirings 52, 53, 54 are made of a metal material containing Al.
The wiring 52 is formed above the source region 33. Between the wiring 52 and the source region 33, the interlayer insulating film 51 is provided with a contact plug 55 for electrically connecting them. The contact plug 55 is made of W (tungsten).
The wiring 53 is formed above the drain region 34 and the drain region 44 so as to straddle them. Between the wiring 53 and the drain region 34, the interlayer insulating film 51 is provided with a contact plug 56 for electrically connecting them. In addition, between the wiring 53 and the drain region 44, a contact plug 57 is provided through the interlayer insulating film 51 to electrically connect them. The contact plugs 56 and 57 are made of W. The wiring 54 is formed above the source region 43. Between the wiring 54 and the source region 43, the interlayer insulating film 51 is provided with a contact plug 58 for electrically connecting them. The contact plug 58 is made of W.

A surface protective film 61 is formed on the outermost surface of the inkjet printer head 1. The surface protective film 61 is made of SiN. The interlayer insulating films 14 and 51 and the wirings 15, 16, 52, 53 and 54 are covered with a surface protective film 61.
In the silicon substrate 2, a pressurizing chamber 62 that opens to the back side is formed at a position facing the piezoelectric element 6. The pressurizing chamber 62 is formed, for example, in a substantially trapezoidal shape with a smaller width (opening area) toward the surface side of the silicon substrate 2. The pressurizing chamber 62 is filled with ink supplied from an ink tank (not shown) through the ink passage 10a. The vibration film 5 described above partitions the top surface portion of the pressurizing chamber 62 and faces the pressurizing chamber 62. The vibrating membrane 5 is supported by a portion (thick part) around the pressurizing chamber 62 of the silicon substrate 2 and can vibrate in a direction facing the pressurizing chamber 62 (in other words, the thickness direction of the vibrating membrane 5). Flexible.

When a drive voltage is applied from the drive circuit 72 to the piezoelectric element 6, the piezoelectric layer 8 is deformed by the inverse piezoelectric effect. As a result, the vibrating membrane 5 is deformed together with the piezoelectric element 6, thereby causing a volume change in the pressurizing chamber 62 and pressurizing the ink in the pressurizing chamber 62. The pressurized ink passes through the ink discharge passage 11 and is discharged as fine droplets from the discharge port 11d.
In the ink jet printer head 1, a diffusion prevention film 70 is interposed between the silicon substrate 2 and the piezoelectric layer 8, and the diffusion prevention film 70 allows metal atoms in the piezoelectric layer 8 to be in the silicon substrate 2. It is suppressed or prevented from diffusing. Thereby, the piezoelectric characteristics of the piezoelectric layer 8 are not deteriorated, and the characteristics (particularly brittleness) of the silicon layer 5A are not deteriorated, and further, the characteristics of the MOSFETs 21 and 22 built in the silicon substrate 2 are deteriorated. Can be avoided. As a result, the piezoelectric layer 8 and the silicon layer 5A can be thinned, and the distance between the MOSFETs 21 and 22 and the piezoelectric layer 8 in the silicon substrate 2 can be shortened. An inkjet printer head 1 having the above can be provided. That is, the piezoelectric element 6 can generate a necessary driving force, the vibration film 5 including the silicon layer 5A can have sufficient durability, and the MOSFETs 21 and 22 can have good element characteristics.

3A to 3S are schematic cross-sectional views sequentially showing manufacturing steps of the ink jet printer head shown in FIG. In FIGS. 3A to 3S, only the conductor and the piezoelectric layer are hatched, and the other portions are not hatched.
The manufacturing process of the ink jet printer head 1 includes a process of creating an element in the circuit forming area 4 (FIGS. 3A to 3J) and a process of creating an ink jet nozzle structure in the nozzle forming area 3 (FIGS. 3K to 3S).

First, as shown in FIG. 3A, an oxide film 81 made of SiO ₂ is formed on the surface of the silicon substrate 2 by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. Subsequently, a nitride film 82 made of SiN (silicon nitride) is formed by CVD. A resist pattern 83 is formed on the nitride film 82 by photolithography. The resist pattern 83 exposes only the portion of the silicon substrate 2 where the groove 26 is to be formed and covers the other portions.

Next, as shown in FIG. 3B, the nitride film 82, the oxide film 81, and the surface layer portion of the silicon substrate 2 are selectively removed in order by etching using the resist pattern 83 as a mask. As a result, a groove 26 is formed in the surface layer portion of the silicon substrate 2. After the formation of the groove 26, the resist pattern 83 is removed.
Thereafter, as shown in FIG. 3C, a thermal oxide film 27 is formed on the inner surface of the groove 26 by a thermal oxidation method. Next, the material of the insulator 28 is deposited on the thermal oxide film 27 and the nitride film 82 by the CVD method. Then, the deposited material and the nitride film 82 are polished by a CMP (Chemical Mechanical Polishing) method. This polishing is continued until the surface of the oxide film 81 is exposed. As a result, an insulator 28 is obtained on the thermal oxide film 27. At this point, the insulator 28 is flush with the surface of the oxide film 81.

  Thereafter, a resist pattern 84 is formed on the insulator 28 and the oxide film 81 by photolithography. The resist pattern 84 is formed over the entire region other than the PMOS region 24 on the insulator 28 and the oxide film 81. Then, an N-type impurity (for example, P (phosphorus)) is implanted into the PMOS region 24 by ion implantation using the resist pattern 84 as a mask. As a result, an N-type well 41 is formed in the PMOS region 24 as shown in FIG. 3D. After the implantation of the N-type impurity, the resist pattern 84 is removed.

  Next, a resist pattern 85 is formed on the insulator 28 and the oxide film 81 by photolithography. The resist pattern 85 is formed over the entire region other than the NMOS region 23 on the insulator 28 and the oxide film 81. Then, by ion implantation, a P-type impurity (for example, B (boron)) is implanted into the NMOS region 23 using the resist pattern 85 as a mask. As a result, a P-type well 31 is formed in the NMOS region 23 as shown in FIG. 3E. After the implantation of the P-type impurity, the resist pattern 85 is removed.

Thereafter, the oxide film 81 is removed by wet etching. At this time, the upper end portion of the insulator 28 is also etched, and the insulator 28 becomes substantially flush with the surface of the silicon substrate 2. Thereafter, a silicon oxide film 86 is formed over the entire surface of the silicon substrate 2 by thermal oxidation or CVD.
Subsequently, as shown in FIG. 3F, a polysilicon layer 87 is formed on the silicon oxide film 86 by the CVD method.

Thereafter, as shown in FIG. 3G, a resist pattern 88 is formed on the polysilicon layer 87 by photolithography. Resist pattern 88 covers only the portions of polysilicon layer 87 that are to become gate electrodes 36 and 46.
Then, the polysilicon layer 87 is patterned by etching using the resist pattern 88 as a mask. As a result, gate electrodes 36 and 46 are formed as shown in FIG. 3H. After the patterning of the polysilicon layer 87, the resist pattern 88 is removed. Thereafter, N-type impurities are implanted into the surface layer portion of the P-type well 31 and the gate electrode 36 by ion implantation. Also, P-type impurities are implanted into the surface layer portion of the N-type well 41 and the gate electrode 46 by ion implantation.

  Next, as shown in FIG. 3I, the silicon oxide film 86 is selectively removed by etching using the gate electrodes 36 and 46 as masks, and the gate insulating films 35 and 45 are obtained on the silicon substrate 2. Thereafter, SiN is deposited on the entire area of the silicon substrate 2 by the CVD method. Then, the sidewalls 37 and 47 are formed by etching back the deposited layer of SiN.

  After the formation of the sidewalls 37 and 47, as shown in FIG. 3J, the surface layer of the P-type well 31 is implanted to a position deeper than the N-type impurity into which the N-type impurity has been previously implanted by ion implantation. A source region 33 and a drain region 34 are formed. Further, by ion implantation, a source region 43 and a drain region 44 are formed in the surface layer portion of the N-type well 41 up to a position deeper than the P-type impurity into which the P-type impurity has been previously implanted. Thereafter, silicides 38, 39, 40, 48, 49, 50 are formed. Thus, the N channel MOSFET 21 is formed in the NMOS region 23 and the P channel MOSFET is formed in the PMOS region 24.

Next, as shown in FIG. 3K, a silicon oxide film is formed by a CVD method to become a silicon oxide layer 5B in the nozzle formation region 3 and an interlayer insulating film 51 in the circuit formation region 4. Further, a diffusion prevention film 70 made of an alumina film is formed thereon by, for example, sputtering.
Thereafter, as shown in FIG. 3L, a film 89 having the same laminated structure as that of the lower electrode 7 is formed on the entire region of the diffusion preventing film 70 by sputtering. Further, a film 90 (for example, a PZT film) made of the same material as that of the piezoelectric layer 8 is formed on the entire area of the film 89 by sputtering or sol-gel method. Further, a film 91 having the same laminated structure as that of the upper electrode 9 is formed over the entire area of the film 90 by sputtering. In the formation of the material film 90 of the piezoelectric layer 8 by the sol-gel method, a process of forming a material base film having a thickness of 50 nm to 100 nm is performed in a state where the substrate is heated to 700 ° C. to 800 ° C. A material base film is laminated. On the other hand, in forming the material film 90 of the piezoelectric layer 8 by sputtering, the piezoelectric material is deposited on the substrate by sputtering performed while the substrate is heated to 300 ° C. to 400 ° C. In any method, since the substrate is heated, if there is no diffusion prevention film 70, the metal atoms in the piezoelectric material diffuse to the silicon substrate 2, and the silicon layer 5 A forming the vibration film 5 is formed. There is a possibility that the characteristics of the elements 21 and 22 formed in the circuit formation region 4 are deteriorated.

Next, as shown in FIG. 3M, a resist pattern 92 is formed on the film 91 so as to cover the portion of the film 91 that becomes the upper electrode 9 by photolithography.
Thereafter, as shown in FIG. 3N, the film 91 is patterned by etching using the resist pattern 92 as a mask, and the upper electrode 9 is formed. Subsequently, the film 90 is patterned by etching, and the piezoelectric layer 8 is formed. After the formation of the piezoelectric layer 8, the resist pattern 92 is removed. Next, by photolithography, a new resist pattern (not shown) is formed on the film 89 so as to cover the part of the film 89 that becomes the lower electrode 7. Then, the film 89 is patterned by etching using a new resist pattern as a mask, and the lower electrode 7 is formed. After the formation of the lower electrode 7, the resist pattern is removed.

Thereafter, the diffusion prevention film 70 in the circuit formation region 4 is removed by photolithography and etching, and this diffusion prevention film 70 is selectively left in the nozzle formation region 3.
Thereafter, through holes that penetrate the interlayer insulating film 51 in the thickness direction are formed in portions of the interlayer insulating film 51 facing the source regions 33 and 43 and the drain regions 34 and 44 by photolithography and etching. Then, W is supplied into each through hole by the CVD method, and each through hole is filled with W. As a result, as shown in FIG. 3O, contact plugs 55 to 58 are formed. Thereafter, an alumina film 93 is formed on the entire area of the silicon substrate 2 by sputtering. Further, a silicon oxide film 94 is formed over the entire area of the alumina film 93 by the CVD method.

  Next, as shown in FIG. 3P, the silicon oxide film 94 and the alumina film 93 are removed from the circuit forming region 4 by photolithography and etching, and selected from the extension 7B of the lower electrode 7 and the upper electrode 9 Removed. As a result, the alumina film 93 and the silicon oxide film 94 become the hydrogen barrier film 13 and the interlayer insulating film 14, respectively, and through holes 17 and 18 that continuously penetrate the hydrogen barrier film 13 and the interlayer insulating film 14 are formed.

Thereafter, an Al film is formed on the interlayer insulating films 14 and 51 by sputtering. Then, the Al film is patterned by photolithography and etching, and wirings 15, 16, 52, 53, and 54 are formed as shown in FIG. 3Q.
Thereafter, as shown in FIG. 3R, a surface protective film 61 is formed on the interlayer insulating films 14 and 51 by the CVD method.

  After the surface protective film 61 is formed, a resist pattern (not shown) is formed on the back surface of the silicon substrate 2 by photolithography. This resist pattern exposes a portion to be the pressurizing chamber 62 in the silicon substrate 2 and covers other portions. Then, as shown in FIG. 3S, a pressurizing chamber 62 is formed in the silicon substrate 2 by wet etching using the resist pattern as a mask. That is, the pressure chamber 62 is formed by etching the silicon substrate 2 from the back side so as to leave the thin silicon layer 5A. At the same time, the vibration film 5 in which the thin silicon layer 5 </ b> A and the silicon oxide layer 5 </ b> B are stacked is formed on the ceiling portion of the pressurizing chamber 62.

  Thereafter, as shown in FIG. 1, a cavity plate 10 </ b> A in which ink passages 10 a and 11 a are formed in advance is attached to the back surface of the silicon substrate 2. Further, a cavity plate 10B in which an ink passage 11b is formed in advance is attached to the back surface of the cavity plate 10A, and a cavity plate 10C in which a nozzle passage 11c is formed in advance is attached to the back surface of the cavity plate 10B. Thus, the ink jet printer head 1 is obtained.

  In this manner, semiconductor elements such as the N-channel MOSFET 21 and the P-channel MOSFET 22 can be formed using the silicon substrate 2. Further, wirings 52, 53, 54 are formed on the silicon substrate 2 with an interlayer insulating film 51 interposed therebetween, and these wirings 52, 53, 54 are connected to the N-channel MOSFET 21 and the P-channel MOSFET 22 through contact plugs 55-58. Thus, the ink jet printer head 1 can be formed in the same chip as the circuit such as the drive circuit 72. That is, since the drive circuit 72 for applying a voltage to the piezoelectric element 6 is formed on the silicon substrate 2 provided with the vibration film 5, the main body portion of the ink jet printer head 1 and the drive circuit 72 are formed in one chip. Configuration (single chip) is possible.

  On the other hand, the diffusion preventing film 70 prevents the metal atoms (lead atoms in the case of PZT) in the piezoelectric layer 8 from diffusing into the silicon substrate 2. As a result, the piezoelectric layer 8 can have good characteristics, and the diffusion of metal atoms to the silicon layer 5A constituting the vibration film 5 can be prevented, and deterioration of the brittleness can be avoided. In addition, since the diffusion of metal atoms to the circuit formation region 4 of the silicon substrate 2 is prevented, it is possible to avoid deterioration of the characteristics of the elements 21 and 22 formed in the circuit formation region 4. Therefore, the main body portion of the ink jet printer head 1 and the drive circuit 72 can be integrated into one chip, and the elements constituting the drive circuit 72 can have good characteristics.

  FIG. 4 is a schematic cross-sectional view for explaining the configuration of an ultrasonic sensor according to the second embodiment of the present invention. The ultrasonic sensor 180 includes an SOI (Silicon on Insulator) substrate 181, a silicon oxide layer 182 that is an insulating film formed on the SOI substrate 181, a diffusion prevention film 183 formed on the silicon oxide layer 182, a diffusion And a piezoelectric element 184 formed on the prevention film 183.

  The SOI substrate 181 includes a base silicon substrate 185, a buried oxide film 186 formed on the surface of the base silicon substrate 185, and a silicon layer 187 formed on the buried oxide film 186. The base silicon substrate 185 is dug from the back side (the side opposite to the silicon layer 187), thereby forming a substantially trapezoidal cavity 191 in cross section. The portion of the buried oxide film 186 that faces the cavity 191 is also removed, and the top surface of the cavity 191 is partitioned by the silicon layer 187. Thus, a vibration film 192 in which the silicon layer 187 and the silicon oxide layer 182 are stacked is formed on the top surface portion of the cavity 191. The vibration film 192 is supported by a thick SOI substrate 181 around the cavity 191. That is, the silicon layer 187 and the silicon oxide layer 182 cover the entire top surface portion of the cavity 191 and further extend around the periphery.

The piezoelectric element 184 includes a lower electrode 188 in contact with the diffusion prevention film 183, a piezoelectric layer 189 stacked on the lower electrode 188, and an upper electrode 190 stacked on the piezoelectric layer 188. That is, in a state where the piezoelectric layer 188 is sandwiched between the lower electrode 188 and the upper electrode 190, they are stacked on the diffusion prevention film 183.
The lower electrode 188 is made of, for example, a laminated structure film in which a Pt layer in contact with the diffusion prevention film 183 and a Ti layer laminated on the Pt layer are laminated. The piezoelectric layer 189 is made of, for example, PZT or KNN. The upper electrode 190 is made of, for example, a Pt layer.

  The lower electrode 188 covers the entire top surface of the cavity 191 and further extends to the periphery thereof. Similarly, the piezoelectric layer 189 covers the entire top surface of the cavity 191 and further extends to the periphery thereof. In the piezoelectric layer 189, an opening that exposes the lower electrode 188 is formed in a region outside the cavity 191. The surface of the lower electrode 188 exposed from the opening serves as a pad 188a for external connection. In this embodiment, the upper electrode 190 is formed above the central region of the top surface portion of the cavity 191.

With this configuration, when the vibration film 192 is vibrated by ultrasonic waves, the piezoelectric layer 189 is deformed accordingly. Due to the piezoelectric effect accompanying this deformation, a voltage is generated between the lower electrode 188 and the upper electrode 190. An electrical signal corresponding to the ultrasonic wave can be obtained by taking out this voltage and performing an appropriate process such as amplification.
The diffusion prevention film 183 is made of an alumina film, for example. The diffusion prevention film 183 prevents diffusion of metal atoms in the piezoelectric layer 189 made of PZT or KNN. As a result, metal atoms can be prevented from diffusing into the silicon layer 187 constituting the vibration film 192, so that the characteristics of the piezoelectric layer 189 can be maintained well and the brittleness of the vibration film 192 is deteriorated. This can improve the durability of the ultrasonic sensor.

  In the silicon layer 187, a semiconductor element such as a transistor element can be formed in a circuit formation region provided in a region other than the region where the ultrasonic sensor 180 is formed. In this case, the diffusion preventing film 183 can prevent the metal atoms from diffusing into the silicon layer 187 in the circuit formation region. Thereby, it is possible to avoid deterioration of the characteristics of the element formed in the circuit formation region. A processing circuit for processing the output of the ultrasonic sensor 180 may be formed in the circuit formation region. Thereby, the ultrasonic sensor which made the processing circuit 1 chip | tip can be provided.

FIG. 5 is a schematic cross-sectional view for explaining the configuration of a high-frequency circuit device including a capacitor element according to the third embodiment of the present invention. In FIG. 5, parts corresponding to the parts shown in FIG. 1 are given the same reference numerals.
The high-frequency circuit device 100 has a circuit formation region 4 and a capacitor formation region 103 on the silicon substrate 2. In the circuit formation region 4, an N-channel MOSFET 21 and a P-channel MOSFET 22 are formed, whereby the circuit formation region 4 forms a CMOS integrated circuit. For example, the circuit formation region 4 forms a switching circuit 111. A ferroelectric capacitor element 105 is formed in the capacitor forming region 103. The ferroelectric capacitor element 105 is used as a constituent element of the filter circuit 112, for example.

In the capacitor formation region 103, a silicon oxide layer 109 that is an insulating film is formed on the surface of the silicon substrate 2. The thickness of the silicon oxide layer 109 is, for example, about 0.2 μm to 0.6 μm. Further, in the capacitor formation region 103, a diffusion prevention film 110 made of alumina (Al ₂ O ₃ ) is laminated on the surface of the silicon oxide layer 109. A ferroelectric capacitor element 105 is disposed on the diffusion prevention film 110.

  The ferroelectric capacitor element 105 includes a lower electrode 106 formed on the diffusion prevention film 110, a ferroelectric layer 107 (ferroelectric capacitor film) formed on the lower electrode 106, and the ferroelectric layer 107. The upper electrode 108 is formed. In other words, the ferroelectric capacitor element 105 has a structure in which the ferroelectric layer 107 is sandwiched between the upper electrode 108 and the lower electrode 106 from above and below. A diffusion prevention film 110 is interposed between the lower electrode 106 and the silicon substrate 2 (more specifically, the silicon oxide layer 109). Thus, a structure in which the diffusion preventing film 110 is interposed between the ferroelectric capacitor element 105 and the silicon substrate 2 is formed.

The lower electrode 106 is made of, for example, a Ti (titanium) layer.
The ferroelectric layer 107 is made of, for example, an SBT (bismuth strontium tantalate SrBi ₂ Ta ₂ O ₉ ) film or a BST (barium strontium titanate (Ba, Sr) TiO ₃ ) film. That is, the ferroelectric layer 107 contains a metal element (strontium and bismuth in the case of SBT, barium and strontium in the case of BST). The diffusion prevention film 110 prevents diffusion of metal atoms, prevents metal atoms from escaping from the ferroelectric layer 107, and prevents metal atoms from reaching the silicon substrate 2.

The upper electrode 108 is formed on the ferroelectric layer 107. The upper electrode 108 is made of, for example, a Pt (platinum) layer.
In the capacitor formation region 103, the surfaces of the ferroelectric capacitor element 105 and the silicon oxide layer 109 are covered with an interlayer insulating film 114. Interlayer insulating film 114 is made of SiO _2. On the interlayer insulating film 114, wirings 115 and 116 are formed. The wirings 115 and 116 are made of a metal material containing Al (aluminum).

One end of the wiring 115 is disposed above the tip of the extension 113 of the lower electrode 106. A through hole 117 that penetrates the interlayer insulating film 114 is formed between one end of the wiring 115 and the extension 113. One end of the wiring 115 enters the through hole 117 and is connected to the extension 113 in the through hole 117.
One end of the wiring 116 is disposed above the peripheral edge of the upper electrode 108. A through hole 118 penetrating the interlayer insulating film 114 is formed between one end of the wiring 116 and the upper electrode 108. One end of the wiring 116 enters the through hole 118 and is connected to the upper electrode 108 in the through hole 118.

The configuration of the circuit formation region 4 shown in FIG. 5 is the same as the configuration shown in FIG. However, the semiconductor elements (MOSFETs 21 and 22) and the like formed in the circuit formation region 4 constitute a switching circuit, and the circuit configuration is different from the drive circuit 72 shown in FIG.
As described above, according to this embodiment, the diffusion prevention film 110 is interposed between the ferroelectric capacitor element 105 and the silicon substrate 2, and the metal atoms in the ferroelectric layer 107 are applied to the silicon substrate 2. Diffusion is prevented. Thereby, the characteristics of the ferroelectric layer 107 can be maintained, and the deterioration of the characteristics of the semiconductor elements 21 and 22 formed in the circuit formation region 4 of the silicon substrate 2 can be avoided. That is, while the ferroelectric capacitor element 105 and the semiconductor elements 21 and 22 are formed on the same silicon substrate 2 to form one chip, both the ferroelectric capacitor element 105 and the semiconductor elements 21 and 22 have excellent element characteristics. Can have.

  As mentioned above, although several embodiment of this invention has been described, this invention can also be implemented with another form. For example, in the above-described embodiment, a structure in which the diffusion prevention films 70, 183, and 110 are interposed between the silicon oxide layers 5B, 182, and 109 and the piezoelectric elements 6, 184 or the ferroelectric capacitor element 105 is shown. However, a similar diffusion preventing film may be interposed between the silicon oxide layers 5B, 182, and 109 and the silicon layer (silicon substrate 2 or silicon layer 187). Even with such a structure, it is possible to avoid the diffusion of metal atoms in the ferroelectric layer (piezoelectric layers 8, 189, ferroelectric layer 107) into the silicon layer.

  Further, the present invention can be applied to other devices having a ferroelectric layer on a silicon layer in addition to an inkjet printer head, an ultrasonic sensor, and a ferroelectric capacitor element. As such a device, in addition to the above-described example, a micro structure device represented by a silicon microphone, a micro speaker, a pressure sensor, an acceleration sensor, and the like manufactured using the MEMS technology can be exemplified.

  In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Inkjet printer head 2 Silicon substrate 3 Nozzle formation area 4 Circuit formation area 5 Vibration film 5A Silicon layer 5B Silicon oxide layer 6 Piezoelectric element 7 Lower electrode 8 Piezoelectric layer 9 Upper electrode 21 N channel MOSFET (semiconductor element)
22 P-channel MOSFET (semiconductor element)
23 NMOS region 24 PMOS region 31 P-type well 41 N-type well 51 Interlayer insulating film 61 Surface protective film 62 Pressurization chamber 70 Diffusion prevention film (alumina film)
72 Driver (Drive circuit)
DESCRIPTION OF SYMBOLS 100 High frequency circuit apparatus 103 Capacitor formation area 105 Ferroelectric capacitor element 106 Lower electrode 107 Ferroelectric layer 108 Upper electrode 109 Silicon oxide layer 110 Diffusion prevention film 111 Switching circuit 112 Filter circuit 114 Interlayer insulation film 180 Ultrasonic sensor 181 SOI substrate 182 Silicon oxide layer 183 Diffusion prevention film 184 Piezoelectric element 185 Underlying silicon substrate 186 Embedded oxide film 187 Silicon layer 188 Lower electrode 189 Piezoelectric layer 190 Upper electrode 191 Vibration film

Claims (7)

A silicon layer;
A metal layer laminated on the silicon layer;
A ferroelectric layer stacked on the metal layer and containing metal atoms;
A silicon device, comprising: a diffusion preventing film that is laminated so as to be interposed between the silicon layer and the ferroelectric layer and prevents diffusion of metal atoms in the ferroelectric layer into the silicon layer. The thin part of the silicon substrate having a thick part and a thin part forms a vibration film including the silicon layer;
The ferroelectric layer is a piezoelectric layer,
The silicon device according to claim 1, wherein the piezoelectric element is configured by laminating the piezoelectric layer between the metal layer as a lower electrode and an upper electrode.   The silicon device according to claim 2, wherein the lower electrode, the piezoelectric layer, and the upper electrode constitute an actuator that deforms the vibration film. An ink reservoir partitioned by the vibrating membrane is formed;
The silicon device according to claim 3, wherein the silicon device constitutes an ink nozzle that pressurizes and discharges ink in the ink reservoir by deforming the vibration film.   The silicon device according to claim 2, wherein the lower electrode, the piezoelectric layer, and the upper electrode constitute a sensor that extracts a voltage generated by the piezoelectric layer due to deformation of the vibration film.   The silicon device according to claim 1, wherein the ferroelectric layer contains lead.   The silicon device according to claim 1, wherein the diffusion prevention film is an alumina film.

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