JP2009257959A - Semiconductor tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor tester for performing a test at a high speed even when the test of a device to be measured is performed over a plurality of pin cards. <P>SOLUTION: This semiconductor tester includes a tester controller for controlling a test sequence, and the plurality of pin cards connected to this tester controller via a control bus, and measures the device to be measured based on a command of the tester controller. The plurality of pin cards have a bus schedule management section for performing bus control via the control bus independently of the control of the tester controller. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for testing a plurality of devices under measurement in parallel, and more particularly to a semiconductor test apparatus capable of performing a test at a high speed even when a device under test is tested across a plurality of pin cards.

  Generally, a semiconductor test apparatus (tester) determines the quality of a DUT based on the output of the DUT obtained by giving a test signal to an IC, LSI, or the like, which is a device under test (hereinafter also referred to as a DUT). . Prior art documents related to such a semiconductor test apparatus include the following.

JP 2005-321238 A

By the way, in order to shorten the test time, such a tester measures a plurality of DUTs in parallel with a plurality of pin cards. Here, the number that the tester can measure the DUT in parallel is determined by the total number of measurement pins provided in the tester and the number of measurement pins of the DUT. That is, for the number of measurement pins necessary for measuring one DUT, the number obtained by dividing the total number of measurement pins provided in the tester by the required number is the number that can be tested simultaneously.

As an example, if the tester has 1024 measurement pins, if 32 measurement pins are required per DUT,
1024 ÷ 32 = 32 pieces,
Parallel measurement can be performed simultaneously.

In addition, a general tester is a tester having thousands of measurement pins mounted on a board (hereinafter referred to as a pin card) on which measurement pins are mounted in units of several tens of pins on a single board. To do. In that case, a pin connected to one DUT may be a single pin card, or a plurality of pin cards may be required.

Hereinafter, a configuration example of a tester for testing a plurality of DUTs in parallel will be described with reference to FIG. The configuration of the pin card 1 will be described. The BUS I / F (bus interface) 10 is an interface that passes signals input / output via the control bus 60 to the local bus 11.

The pattern generator 12 generates various patterns to be output to the DUT 161. Drivers 121, 122, and 123 are drive circuits. These drivers also output the patterns generated by the pattern generator 12 to the DUTs 161, 162, and 163.

A pattern output from the DUT 161 is input to the comparison circuit 13 via the comparator 131 together with the pattern generated by the pattern generation unit 12. Similarly, the pattern output from the DUT 162 is input to the comparison circuit 14 through the comparator 141 together with the pattern generated by the pattern generator 12. The pattern output from the DUT 163 is input to the comparison circuit 15 through the comparator 151 together with the pattern generated by the pattern generator 12. The configuration of the pin card 2 and the pin card 3 is the same as that of the pin card 1 and will not be described.

The tester controller 50 includes a test sequence control unit 51 and a BUS I / F 52. The test sequence control unit 51 controls the test sequence of the entire tester. The BUS I / F 52 exchanges signals with the BUS I / F mounted on each pin card via the control BUS 60.

As shown in FIG. 6, when the DUT to be measured requires one comparator per driver, three DUTs can be measured with one pin card. In this case, the test result can be obtained in a state completed with a single pin card. That is, it is not necessary to match the test result of one DUT with the test result of the measurement pins of other slots.

Next, referring to FIG. 7, a block diagram when the measurement pins of the DUT are connected across two pin cards is shown. FIG. 7 shows a configuration example when measuring a DUT 164 that requires six drivers and six comparators. In this case, when judging Pass / Fail of the test result, it is understood only with the result of the adjacent pin card. That is, the DUT measurement is not completed with one pin card.

Usually, in order to obtain information on the adjacent pin card, it is necessary to obtain information by performing bus communication using the control bus 60. In this case, the phase and latency (the delay time from when the test sequence control unit 51 requests data transfer to when the data is actually transferred) becomes a problem.

As an example, a timing chart of the control bus 60 is shown with reference to FIG. The control signal is controlled by an address strobe signal (ADD_stb) for recognizing each card and a data strobe signal (Data_stb) which is a control signal for outputting data to the bus.

When acquiring information on a specific card by the tester controller 50, it takes time to specify an address (Tad), which is an overhead, and therefore it takes a measurement time when more pin cards are required for DUT measurement. Is delayed.

As described above, in the conventional tester, when a plurality of pin cards are required for the DUT measurement, the tester controller 50 sometimes takes in the information measured by each pin card.

In general, when the test conditions do not change during the test, it is sufficient to capture the measurement results for each DUT in the tester controller 50 after all the tests are completed.

However, even when measuring one DUT, in the case of a test program in which the test conditions must be sequentially changed from the determination results of other pins, all test information is taken into the tester controller 50 that controls the test sequence. Based on the information, the tester controller 50 must determine the next test condition.

Also, in the case of a test program in which the test conditions must be sequentially changed from other DUT determination results, all the test information must be taken into the tester controller 50 in the same manner.

Further, even when the tester controller 50 does not need to take in the test information, when the test information is exchanged between the pin cards, the tester controller 50 needs to mediate through the control bus 60.

In either case, as shown in the timing chart of FIG. 8, since the time (Tad) for setting the address of the pin card to be taken in is required as overhead, the transfer time of the test result becomes long and the measurement time increases. Cause the test throughput to deteriorate.

  Next, problems will be described using test examples. This test determination is performed in the pin card for each DUT. FIG. 9 is a state transition of a test for each DUT. First, test conditions are set (S1), and power is turned on (S2).

Then, consider a case where the state has advanced to the point of test 1 (S3), and it is necessary to proceed to S41 as a result of the determination at S4 of the next step. In this case, when a plurality of pin cards are not required for measurement of the same DUT as shown in FIG. 6, the determination results can be aggregated in the one pin card, so that the control bus 60 is not used. Each pin card can go to the next step at the same time.

However, when one DUT is measured using two pin cards as shown in FIG. 7, the information on the pin card 2 side is transferred to the pin card 1 side and the determination is made by the pin card 1. That is, when a test is performed based on information of another pin card, it is necessary to collect data using the control bus 60.

In addition, normally, as shown in FIG. 7, the pin card is not composed of two sheets but is composed of several tens of sheets. Therefore, if the bus control is performed via the tester controller 50, the throughput is lowered.

The present invention has been made in view of these problems, and provides a semiconductor test apparatus capable of performing a test at a high speed even when a test of a device under test is performed across a plurality of pin cards. Objective.

In order to achieve such a problem, the invention according to claim 1
In a semiconductor test apparatus comprising a tester controller for controlling a test sequence and a plurality of pin cards connected to the tester controller via a control bus, and measuring a device under test based on an instruction from the tester controller,
The plurality of pin cards include a bus schedule management unit that performs bus control via the control bus independently of control of the tester controller.

According to a second aspect of the present invention, in the semiconductor test apparatus of the first aspect,
The bus schedule management unit
A state in which the bus is enabled among the plurality of pin cards is set exclusively for each state.

According to a third aspect of the present invention, in the semiconductor test apparatus according to the second aspect,
The bus schedule management unit
Management is performed by time division or bit division so that the bus enable state among the plurality of pin cards is set exclusively for each state.

  The present invention has the following effects. Since the bus enable state between each pin card is set exclusively for each state, the bus schedule management unit is provided, so when exchanging data according to a predetermined sequence, The overhead of specifying addresses is reduced, and data can be exchanged at high speed.

Hereinafter, the block diagram of the pin card of the present invention will be described with reference to FIG. However, the same components as those in FIG.

The bus schedule management unit 17 is a newly added configuration and manages the bus schedule. The bus schedule management unit 17 has the following two roles. First, the access timing to the control bus 60 is controlled independently for each card. Second, the pin cards are synchronized based on control signals output from the tester controller 50 and the test pattern generator 12.

FIG. 2 is a configuration diagram of the bus schedule management unit 17 and the BUS I / F 10. The BUS I / F 10 transfers the test sequence state address 175 output from the tester controller 50 to the bus schedule management unit 17 through the bus transceiver 101 under the control of the bus control circuit, and also outputs it from a lookup table 173 described later. The BUS_En (bus enable) 174 is output to the control bus 60.

The memory 171 stores a test sequence state address 175 given from the tester controller 50. The bus enable state machine 172 is used to control the bus.

Next, the operation will be described. First, it is assumed that the test is performed in a test sequence as shown in FIG. The tester controller 50 controls the state of the test sequence as shown in FIG. Specifically, a test sequence state address 175 indicating the state of each test is sent to each pin card. Each pin card receives this signal at the BUS I / F 10 and transfers it to the bus schedule management unit 17.

The bus schedule management unit 17 outputs BUS_act 176 based on the stored contents of the memory 171 and operates the bus enable state machine 172. Here, in the test state of FIG. 9, the state in which data is exchanged using the control bus 60 is during the determination of S4 and S6. This condition is programmed in the memory 171.

FIG. 3A shows an example programmed in the memory 171. In the figure, when a hatched position (S4 and S6) is accessed, a signal BUS_act means that data can be exchanged using the control bus 60 as shown in FIG. (Reference numeral 500 in FIG. 3B) is output.

The bus enable state machine 172 operates in response to the BUS_act signal. In this example, the bus enable address (reference numeral 501 in FIG. 3B) is incremented from the state sbe0 to sbe8 for easy understanding.

FIG. 4 shows an example of a lookup table 173 mounted for each pin card, in which the timing of bus access to the control bus 60 is programmed. In this example, the bus enable state is set exclusively for each state (sbe0 to sbe8) so that the bus does not collide between the pin cards 1, 2, and 3. For this reason, as is apparent from the timing chart of FIG. 3B, the BUS_En signal (reference numeral 502 in FIG. 3B) of each pin card is exclusively asserted.

  As described above, the bus schedule management unit 17 controls the buses so that the buses do not collide between the pin cards. Therefore, when data is exchanged according to a predetermined sequence, the overhead for designating the address of the other party The data can be exchanged at high speed.

  Next, application examples of the present invention will be described. In general, when a bus is used, the time division is performed. However, in the present invention, the bus schedule management unit 17 can set the state of the lookup table 173 independently by each pin card, thereby dividing the bus into bits. An example of using this is shown below. FIG. 5 shows a configuration example when the bus is divided into bits. However, as a hardware configuration, FIG. 5 is similar to FIG.

As a bit division method, the bus access timing is set by the test sequence state address 175 set by the test sequence controller 50. Therefore, since the connection destination is determined for each bit in advance, mutual connection is possible during bus access. In FIG. 5, it is assumed that black square terminals are connected to each other and data can be exchanged individually.

  This bus bit division method is effective when the total amount of data exchanged is small and there are many combinations of connection partners, reducing overhead for specifying the address of the other party, and exchanging data at high speed. Can do.

It is a block diagram of the pin card of this invention. It is a detailed block diagram of a bus schedule management part and BUS I / F. It is a timing chart of the present invention. This is the contents of the lookup table for each pin card. It is a block diagram of the application example of this invention. It is a block diagram of the semiconductor test apparatus which performs the conventional parallel measurement. It is a block diagram of a semiconductor test apparatus when a measurement pin of a DUT extends over a plurality of pin cards. It is a timing chart of a control bus. It is a state transition diagram of the test of DUT.

Explanation of symbols

1 pin card 10 BUS I / F
11 Local Bus 12 Pattern Generation Unit 13 Comparison Circuit 14 Comparison Circuit 15 Comparison Circuit 17 BUS Schedule Management Unit 60 Control Bus 101 Bus Transceiver 121 Driver 122 Driver 123 Driver 131 Comparator 141 Comparator 151 Comparator 171 Memory 172 Bus Enable State Machine 173 Lookup table

Claims (3)

In a semiconductor test apparatus comprising a tester controller for controlling a test sequence and a plurality of pin cards connected to the tester controller via a control bus, and measuring a device under test based on an instruction from the tester controller,
The plurality of pin cards include a bus schedule management unit that performs bus control via the control bus independently of control of the tester controller. The bus schedule management unit
2. The semiconductor test apparatus according to claim 1, wherein a state in which a bus is enabled between the plurality of pin cards is managed so as to be set exclusively for each state. The bus schedule management unit
3. The semiconductor test apparatus according to claim 2, wherein a state in which the bus is enabled among the plurality of pin cards is managed by time division or bit division so that each state is set exclusively.

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