JP2009216419A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of facilitating a test by arranging input and output data from an outside. <P>SOLUTION: This semiconductor integrated circuit device is provided with a first delay regulation circuit 14 for regulating a delay amount of the input data of a test pattern input from the outside, a first memory 15 for storing the input data of the test pattern output from the first delay regulation circuit 14, a device 1 to be tested for processing the input data of the test pattern output in parallel from the first memory 15, to output an output expected value, a second memory 25 for storing an output expected value data output in parallel from the device 1 to be tested, and a second delay regulation circuit 24 for regulating a delay amount of a data output from the second memory 25, and an output from the second delay regulation circuit 24 is output to the outside as an expected value. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device having a test circuit for testing a semiconductor integrated circuit.

  Conventionally, a test of a semiconductor integrated circuit has been performed by a system as shown in FIG. As shown in FIG. 4, the input side of a device under test (DUT) 100 to be measured is connected to an input terminal 103 via a buffer 102, and the output side is connected to an output terminal 104 via a buffer 4. It is connected.

  The test LSI tester 106 inputs a test pattern to the input terminal 103 via the interface 107. This test pattern is input from the input terminal 103 via the buffer 102 to the input side of a device under test (DUT: Device undertest) 100 of the LSI to be measured and processed, and the output expected value as a result is processed. From the output side to the output terminal 105 via the buffer 104.

  The expected output value is input to the LSI tester 106 via the interface 108, and the test result is determined by comparing the expected output value with the test pattern.

  Incidentally, a high-performance high-speed LSI tester is required to perform a high-speed LSI test using the system shown in FIG. However, the high-speed LSI tester is very expensive, and there is a problem that a large amount of cost is required only by preparing this high-speed LSI tester. Actual measurement is performed by placing a test board (not shown) on a high-speed LSI tester, placing a socket (not shown) thereon, and connecting the LSI to be measured to this socket. Characteristics (noise, reflection characteristics, etc.) of test boards (corresponding to interfaces 107 and 108) for realizing high-speed transmission of test patterns, probe cards (not shown) necessary for testing LSIs in a wafer state, etc. Must be suitable for high-speed transmission, and a large amount of time and time are required for the development cost, development time, adjustment, etc. of a measuring jig having satisfactory performance.

  Therefore, as an LSI high-speed test system that does not use an expensive high-speed LSI tester or measurement jig and can perform high-speed LSI testing at a low cost with a short preparation time, the first side is connected to the input side of the internal circuit to be tested. The first storage means is provided with the second storage means on the output side, and a low-speed test pattern inputted from the outside is stored in the first storage means at a low speed by a low-speed clock, and the stored test pattern is stored in the oscillation circuit. Reading is performed at high speed by the generated high-speed clock and input to the internal circuit. Then, a high-speed output expected value output from the internal circuit is stored in the second storage means at high speed with a high-speed clock, and the stored output expected value is read out at low speed with a low-speed clock ( Patent Document 1).

  By the way, when testing a circuit that requires input / output of parallel data, the test external terminal may also be used as a normal operation external terminal. FIG. 4 shows a circuit example when the test external terminal is also used as the normal operation external terminal. As shown in FIG. 4, an input side of a device under test (DUT) 100 to be measured is connected to an input terminal 103 via a buffer 102 and a selector 111, and a selector 112 and a buffer 4 are connected to an output side. Via the output terminal 104. Although not shown, a test LSI tester is connected between the input terminal 103 and the output terminal 104 as in FIG.

The selector 112 is given a test mode switching signal by the control circuit 110a, and the input terminal 102 is switched between a test mode and a normal mode. Further, the selector 112 is given a test mode switching signal by the control circuit control circuit 110b, and the output terminal 105 is switched between the test use and the normal operation use. Conventionally, when the external input / output terminals 103 and 105 are also used for normal operation for input / output of parallel data, wiring delay occurs depending on the positions of the external input / output terminals 103 and 105. Further, various delay circuits 120 exist up to the device under test 100 at the input / output terminal 103. In FIG. 4, the delay circuit 120 is represented by the number of buffers. As shown in FIG. 4, the number of buffers differs depending on the position of the input terminal 103, and the delay amount differs. As a result, it has become difficult to capture with the same clock as the operation becomes faster.
Japanese Patent Laid-Open No. 2003-4809

  When testing a circuit that requires input / output of parallel data, as shown in FIG. 4, if the test external terminal is also used as a normal operation external terminal, the delay of the input data to the test target circuit However, the skew of the output data is not uniform and it is difficult to align the expected values. Further, when inputting / outputting parallel data, many external test terminals are required. Further, in the above-mentioned Patent Document 1, no consideration is given to eliminating the delay of input data to the test target circuit.

  An object of the present invention is to provide a semiconductor integrated circuit device that can be easily tested by aligning input / output data from the outside, in view of the above-described conventional problems. Another object of the present invention is to reduce the number of external test input / output terminals (including dual-purpose terminals).

  A semiconductor integrated circuit device according to the present invention stores a first delay adjustment circuit for adjusting a delay amount of input data of a test pattern inputted from the outside, and test pattern input data outputted from the first delay circuit. First storage means for processing, an internal circuit for processing input data of the test pattern output in parallel from the first storage means and outputting an expected output value, and an output expectation output in parallel from the internal circuit A second storage means for storing value data, a second delay adjustment circuit for adjusting a delay amount of data output from the second storage means, and an output from the second delay adjustment circuit as an expected value. As an external output.

  Further, test pattern input data is given in parallel to the first delay circuit, test pattern input data is given in parallel from the first delay circuit to the first storage means, and the second storage means is provided. The output expected value may be output in parallel to the second delay adjustment circuit, and the expected value may be output in parallel from the second delay adjustment circuit.

  The first and second delay adjustment circuits can be configured to have a plurality of flip-flops.

  According to the present invention, test pattern input data is serially given to the first delay circuit, and the data is stored in the first storage means and then output in parallel to the internal circuit. The output expected value is serially output to the second delay circuit, and parallel data can be input / output with the number of external input / output terminals smaller than the data width.

  According to the present invention, the timing can be easily adjusted by receiving the input data by the first delay adjustment circuit synchronized with the clock. Similarly, the skew adjustment of the external output parallel data can be facilitated by the second delay adjustment circuit synchronized with the clock on the output side.

  Further, by configuring the delay adjustment circuit flip-flops in a plurality of stages, adjustment is possible even for a long wiring distance.

  In addition, by inputting serially to the first storage means and outputting serially from the second storage means, parallel data can be input / output via a single external input / output terminal. Terminals can be reduced, and the chip size can be reduced.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated in order to avoid duplication of description.

  FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention.

  As shown in FIG. 1, the input side of a device under test (DUT: Device undertest) 1 that is an object to be measured, which is an internal circuit, is connected to an input terminal 11 via a buffer 12 and a selector 13. The output side is connected to the output terminal 21 via the selector 23 and the buffer 22. The selector 13 is connected to a first delay adjustment circuit 14 for input data. The delay adjustment circuit 14 receives external input data and outputs the data to the first memory 15. The delay adjustment circuit 14 is configured by a circuit synchronized with a clock such as flip-flops connected in multiple stages. The delay adjustment circuit 14 adjusts the delay amount between the input terminals 11 and stores the input test pattern data provided from the selector 14 in the memory 15. give. Data of an input test pattern stored in the memory 15 is input to the device under test 1.

  The selector 13 and the memory 15 are controlled by the control circuit 16. The control circuit 16 performs switching control of the external input terminal 11 and read / write switching of the memory 15 during normal operation and test.

  Data of the expected output value input from the memory 15 to the device under test 1 and processed by the device under test 1 is stored in the second memory 25. The data stored in the memory 25 is supplied to the second delay adjustment circuit 24 and is output from the selector 23 to the output terminal 21 via the buffer 22. The delay adjustment circuit 24 is configured by a circuit synchronized with a clock such as flip-flops connected in multiple stages. The delay adjustment circuit 24 adjusts the amount of delay between the output terminals 21 and converts the data read from the memory 25 into the selector 23 and the buffer 21. To the output terminal 21.

  The selector 23 and the memory 25 are controlled by the control circuit 26. The control circuit 26 performs switching control of the external output terminal 21 during normal operation and testing and switching control of read / write of the memory 25.

  Note that a control clock is supplied to the control circuit 16, the control circuit 26, and the delay adjustment circuits 14 and 24.

  Although not shown, a test LSI tester is connected between the input terminal 13 and the output terminal 21 as in FIG. A test pattern is applied to the input terminal 11 from the LSI tester. This test pattern is stored in the memory 15 from the input terminal 11 through the buffer 12, the selector 13, and the delay adjustment circuit 14. After being input from the memory 15 to the input side of the device under test 1 of the LSI under test 1 and processed, the expected output value is stored in the memory 25 from the output side of the device under test 1, and after the storage is completed, The signal is output to the output terminal 21 via the delay adjustment circuit 24, the selector 23, and the buffer 22. The output expected value output from the output terminal 21 is input to the LSI tester, and the test is performed by comparing the output expected value with the test pattern.

  Next, the operation when the device under test 1 is tested will be described. Input data given from the tester is given to the input terminal 11, the delay is adjusted by the delay adjustment circuit 14 that outputs the data to the memory 15 via the buffer 12 and the selector 13, and the input test pattern is stored in the memory 15. At this time, the control circuit 16 controls the selector 13 during the test and controls the memory 15 to the write state.

  After the data is stored in the memory 15, the control circuit 16 switches to the operation for reading the memory 15, and inputs the data in the memory 15 to the device under test 1 in parallel. The parallel output of the output expected value of the device under test 1 is stored in the output side memory 25, and after the output of the device under test 1 is completed, the output side memory 25 is read by the control circuit 26 and synchronized with a clock like a flip-flop. The output is output to the output terminal 21 via the selector 23 and the buffer 22 through the delay adjustment circuit 24.

  Conventionally, when the external input / output terminal is also used for normal operation for parallel data input / output, the wiring delay varies depending on the position of the external input / output terminal as described above, and the delay is caused by the selector etc. to the test target circuit. In addition, it was difficult to capture with the same clock as the operation speed increased.

  In contrast, in this embodiment, as shown in FIG. 1, timing adjustment can be facilitated by receiving input data by a delay adjustment circuit 14 synchronized with a clock such as a flip-flop. Similarly, a delay adjustment circuit 24 synchronized with a clock such as an output side flip-flop can easily adjust the skew of external output parallel data.

  In the case of a large-scale circuit, the wiring becomes longer and delay adjustment becomes difficult. Therefore, as shown in FIG. 1, when delay adjustment is difficult as in a large-scale circuit, the delay adjustment circuits 14 and 24 are configured by inserting a plurality of flip-flops. As described above, by inserting a plurality of flip-flops, adjustment is possible even for a long wiring distance. In addition, by using the circuit configuration shown in FIG. 1, it is possible to easily adjust the timing of the input / output data during the test and to align the input / output data, thereby enabling high-speed parallel data input / output testing. Become.

  As shown in FIG. 1, by using a circuit configuration in which a plurality of stages of flip-flops are inserted as the delay adjustment circuits 14 and 24, it is possible to easily adjust the timing of input / output data at the same time even in a large-scale circuit. Since the input / output data can be aligned, the parallel data input / output test can be performed at a high speed.

  Next, a second embodiment of the present invention will be described with reference to FIG. The configuration shown in FIG. 2 makes it possible to reduce the number of external terminals. As shown in FIG. 2, a memory 15a as a storage device is connected to the input side of the device under test 1, and external test input patterns stored in the memory 15a are given to the device under test 1 in parallel. A test input from the outside is serially input from the input / output terminal 31 to the memory 15a via the buffer 12a, the selector 13a, and the delay adjustment circuit 14a, and is stored in the memory 15a. The delay adjustment circuit 14a is composed of a circuit synchronized with a clock such as a multi-stage connection of flip-flops. The delay adjustment circuit 14a adjusts the delay amount of the input / output terminal 31 and converts the input test pattern provided from the selector 13a as serial data into the memory 15a. To give.

  A memory 25a serving as a storage device is connected to the output side of the device under test 1 that is the object to be measured, and is input from the memory 15a to the input side of the device under test 1 of the LSI to be measured and processed. A certain expected output value is output in parallel to the memory 25a from the output side of the device under test 1, and stored in the memory 25a.

  Expected output value data is read serially from the memory 25a, delayed by the delay adjusting circuit 24a, and output to the input / output terminal 31a via the selector 23a and the buffer 22a.

  The selectors 13 a and 23 a and the memories 15 a and 25 a are controlled by the control circuit 16. The control circuit 16 performs switching of the input / output terminal 11 during normal operation and testing, control of the selectors 13a and 23a for switching between input and output of data, and switching control of read / write of the memories 15a and 25a.

  As shown in FIG. 2, by having the memory 15a, an external test input given from the input / output terminal 31 is serially input, stored in the memory 15a, and output to the device under test 1 in parallel. The number of input / output terminals 31 can be reduced. Similarly, external test output can be reduced by storing parallel data from the device under test 1 in the memory 25a and then outputting the data serially to the outside.

  In this way, by using the circuit configuration shown in FIG. 2, the memories 15a and 25a are connected to the device under test 1, so that parallel data input / output can be performed by a single external input / output terminal 31. External input / output terminals can be reduced, and the chip size can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.

1 is a circuit diagram showing a configuration of a first embodiment of the present invention. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention. 1 is a block diagram showing a system for testing a semiconductor integrated circuit. It is a circuit diagram in the case of using the conventional test external terminal also as an external terminal for normal operation.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Device under test (DUT), 11 input terminal, 12 buffer, 13 selector, 14 1st delay circuit, 15 1st memory, 16 control circuit, 21 output terminal, 22 buffer, 23 selector, 24 2nd delay Circuit, 25 second memory, 26 control circuit.

Claims (4)

  A first delay adjusting circuit for adjusting a delay amount of test pattern input data input from the outside, a first storage means for storing test pattern input data output from the first delay circuit, and An internal circuit that processes input data of a test pattern output in parallel from the first storage means and outputs an expected output value, and a second storage that stores output expected value data output in parallel from the internal circuit And a second delay adjustment circuit for adjusting a delay amount of data output from the second storage means, and an output from the second delay adjustment circuit is output to the outside as an expected value. A semiconductor integrated circuit device.   Test pattern input data is given in parallel to the first delay circuit, test pattern input data is given in parallel from the first delay circuit to the first storage means, and from the second storage means, 2. The semiconductor integrated circuit device according to claim 1, wherein an output expected value is output in parallel to the second delay adjustment circuit, and an expected value is output in parallel from the second delay adjustment circuit.   3. The semiconductor integrated circuit device according to claim 1, wherein each of the first and second delay adjustment circuits has a plurality of flip-flops.   Test pattern input data is serially applied to the first delay circuit, and after the data is stored in the first storage means, the data is output in parallel to the internal circuit and from the second storage means to the second delay. 2. The semiconductor integrated circuit device according to claim 1, wherein an expected output value is serially output to the circuit, and parallel data is input / output with the number of external input / output terminals smaller than the data width.

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